o3-timing.py revision 4390
12391SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
22391SN/A# All rights reserved.
32391SN/A#
42391SN/A# Redistribution and use in source and binary forms, with or without
52391SN/A# modification, are permitted provided that the following conditions are
62391SN/A# met: redistributions of source code must retain the above copyright
72391SN/A# notice, this list of conditions and the following disclaimer;
82391SN/A# redistributions in binary form must reproduce the above copyright
92391SN/A# notice, this list of conditions and the following disclaimer in the
102391SN/A# documentation and/or other materials provided with the distribution;
112391SN/A# neither the name of the copyright holders nor the names of its
122391SN/A# contributors may be used to endorse or promote products derived from
132391SN/A# this software without specific prior written permission.
142391SN/A#
152391SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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262391SN/A#
272391SN/A# Authors: Steve Reinhardt
282391SN/A
292391SN/Aimport m5
302391SN/Afrom m5.objects import *
312391SN/Am5.AddToPath('../configs/common')
322391SN/A
332391SN/Aclass MyCache(BaseCache):
342391SN/A    assoc = 2
352391SN/A    block_size = 64
362462SN/A    latency = 1
372414SN/A    mshrs = 10
382415SN/A    tgts_per_mshr = 5
392415SN/A
402416SN/Acpu = DerivO3CPU(cpu_id=0)
412416SN/Acpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
422462SN/A                              MyCache(size = '2MB'))
432391SN/Acpu.clock = '2GHz'
442391SN/A
452391SN/Asystem = System(cpu = cpu,
462462SN/A                physmem = PhysicalMemory(),
472391SN/A                membus = Bus())
482413SN/Asystem.physmem.port = system.membus.port
492413SN/Acpu.connectMemPorts(system.membus)
502413SN/A
512413SN/Aroot = Root(system = system)
522413SN/A