o3-timing-mt.py revision 3096
12810SN/A# Copyright (c) 2006 The Regents of The University of Michigan
212728Snikos.nikoleris@arm.com# All rights reserved.
39347SAndreas.Sandberg@arm.com#
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139347SAndreas.Sandberg@arm.com# this software without specific prior written permission.
142810SN/A#
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262810SN/A#
272810SN/A# Authors: Steve Reinhardt
282810SN/A
292810SN/Aimport m5
302810SN/Afrom m5.objects import *
312810SN/Am5.AddToPath('../configs/common')
322810SN/Afrom FullO3Config import *
332810SN/A
342810SN/Aclass MyCache(BaseCache):
352810SN/A    assoc = 2
362810SN/A    block_size = 64
372810SN/A    latency = 1
382810SN/A    mshrs = 10
392810SN/A    tgts_per_mshr = 5
402810SN/A
412810SN/Acpu = DetailedO3CPU()
422810SN/Acpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
432810SN/A                              MyCache(size = '2MB'))
442810SN/Acpu.mem = cpu.dcache
452810SN/A
462810SN/Asystem = System(cpu = cpu,
472810SN/A                physmem = PhysicalMemory(),
482810SN/A                membus = Bus())
4912492Sodanrc@yahoo.com.brsystem.physmem.port = system.membus.port
5012492Sodanrc@yahoo.com.brcpu.connectMemPorts(system.membus)
512810SN/A
5212727Snikos.nikoleris@arm.comroot = Root(system = system)
5312728Snikos.nikoleris@arm.com