o3-timing-mp.py revision 9288:3d6da8559605 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33# --------------------
34# Base L1 Cache
35# ====================
36
37class L1(BaseCache):
38    hit_latency = 2
39    response_latency = 2
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 20
43    is_top_level = True
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50    block_size = 64
51    hit_latency = 20
52    response_latency = 20
53    mshrs = 92
54    tgts_per_mshr = 16
55    write_buffers = 8
56
57nb_cores = 4
58cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
59
60# system simulated
61system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
62
63# l2cache & bus
64system.toL2Bus = CoherentBus(clock = '2GHz')
65system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.master
67
68# connect l2c to membus
69system.l2c.mem_side = system.membus.slave
70
71# add L1 caches
72for cpu in cpus:
73    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
74                                L1(size = '32kB', assoc = 4))
75    # create the interrupt controller
76    cpu.createInterruptController()
77    # connect cpu level-1 caches to shared level-2 cache
78    cpu.connectAllPorts(system.toL2Bus, system.membus)
79    cpu.clock = '2GHz'
80
81# connect memory to membus
82system.physmem.port = system.membus.master
83
84# connect system port to membus
85system.system_port = system.membus.slave
86
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root( full_system = False, system = system )
92root.system.mem_mode = 'timing'
93#root.trace.flags="Bus Cache"
94#root.trace.flags = "BusAddrRanges"
95