o3-timing-mp.py revision 8833:2870638642bd
16157Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26157Snate@binkert.org# All rights reserved. 36157Snate@binkert.org# 46157Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56157Snate@binkert.org# modification, are permitted provided that the following conditions are 66157Snate@binkert.org# met: redistributions of source code must retain the above copyright 76157Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86157Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96157Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106157Snate@binkert.org# documentation and/or other materials provided with the distribution; 116157Snate@binkert.org# neither the name of the copyright holders nor the names of its 126157Snate@binkert.org# contributors may be used to endorse or promote products derived from 136157Snate@binkert.org# this software without specific prior written permission. 146157Snate@binkert.org# 156157Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166157Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176157Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186157Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196157Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206157Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216157Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226157Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236157Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246157Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256157Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266157Snate@binkert.org# 276157Snate@binkert.org# Authors: Ron Dreslinski 286157Snate@binkert.org 296157Snate@binkert.orgimport m5 306157Snate@binkert.orgfrom m5.objects import * 316157Snate@binkert.orgm5.util.addToPath('../configs/common') 326157Snate@binkert.org 336168Snate@binkert.org# -------------------- 346168Snate@binkert.org# Base L1 Cache 356168Snate@binkert.org# ==================== 366157Snate@binkert.org 376157Snate@binkert.orgclass L1(BaseCache): 386157Snate@binkert.org latency = '1ns' 396157Snate@binkert.org block_size = 64 406157Snate@binkert.org mshrs = 4 41 tgts_per_mshr = 20 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 50 latency = '10ns' 51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.port 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache 75 cpu.connectAllPorts(system.toL2Bus, system.membus) 76 cpu.clock = '2GHz' 77 78# connect memory to membus 79system.physmem.port = system.membus.port 80 81# connect system port to membus 82system.system_port = system.membus.port 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Bus Cache" 91#root.trace.flags = "BusAddrRanges" 92