o3-timing-mp-ruby.py revision 8808:8af87554ad7e
15703SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 25703SN/A# All rights reserved. 35703SN/A# 45703SN/A# Redistribution and use in source and binary forms, with or without 55703SN/A# modification, are permitted provided that the following conditions are 65703SN/A# met: redistributions of source code must retain the above copyright 75703SN/A# notice, this list of conditions and the following disclaimer; 85703SN/A# redistributions in binary form must reproduce the above copyright 95703SN/A# notice, this list of conditions and the following disclaimer in the 105703SN/A# documentation and/or other materials provided with the distribution; 115703SN/A# neither the name of the copyright holders nor the names of its 125703SN/A# contributors may be used to endorse or promote products derived from 135703SN/A# this software without specific prior written permission. 145703SN/A# 155703SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165703SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175703SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185703SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195703SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205703SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215703SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225703SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235703SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245703SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255703SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265703SN/A# 275703SN/A# Authors: Ron Dreslinski 285703SN/A 295703SN/Aimport m5 3011680SCurtis.Dunham@arm.comfrom m5.objects import * 315703SN/Am5.util.addToPath('../configs/common') 325703SN/A 335703SN/Anb_cores = 4 345703SN/Acpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 355703SN/A 365703SN/Aimport ruby_config 375703SN/Aruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 385703SN/A 395703SN/A# system simulated 405703SN/Asystem = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 415703SN/A 425703SN/Afor cpu in cpus: 435703SN/A cpu.connectAllPorts(system.membus) 445703SN/A cpu.clock = '2GHz' 455703SN/A 465703SN/A# connect memory to membus 475703SN/Asystem.physmem.port = system.membus.port 485703SN/A 495703SN/A# Connect the system port for loading of binaries etc 505703SN/Asystem.system_port = system.membus.port 515703SN/A 525703SN/A# ----------------------- 535703SN/A# run simulation 545703SN/A# ----------------------- 555703SN/A 565703SN/Aroot = Root(full_system = False, system = system) 575703SN/Aroot.system.mem_mode = 'timing' 585703SN/A