o3-timing-checker.py revision 9288:3d6da8559605
113606Sciro.santilli@arm.com# Copyright (c) 2011 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 145323Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 152934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 162934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 172934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 182934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 192934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 202934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 212934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 222934Sktlim@umich.edu# this software without specific prior written permission. 232934Sktlim@umich.edu# 242934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352934Sktlim@umich.edu# 362934Sktlim@umich.edu# Authors: Geoffrey Blake 372934Sktlim@umich.edu 382934Sktlim@umich.eduimport m5 392934Sktlim@umich.edufrom m5.objects import * 402934Sktlim@umich.edum5.util.addToPath('../configs/common') 412934Sktlim@umich.edu 4212564Sgabeblack@google.comclass MyCache(BaseCache): 4312564Sgabeblack@google.com assoc = 2 442934Sktlim@umich.edu block_size = 64 452995Ssaidi@eecs.umich.edu hit_latency = 2 4610046Snilay@cs.wisc.edu response_latency = 2 4711688Sandreas.hansson@arm.com mshrs = 10 482934Sktlim@umich.edu tgts_per_mshr = 5 4910747SChris.Emmons@arm.com 5010747SChris.Emmons@arm.comclass MyL1Cache(MyCache): 5110747SChris.Emmons@arm.com is_top_level = True 5210747SChris.Emmons@arm.com tgts_per_mshr = 20 5310747SChris.Emmons@arm.com 5410747SChris.Emmons@arm.comcpu = DerivO3CPU(cpu_id=0) 5510747SChris.Emmons@arm.comcpu.createInterruptController() 5610747SChris.Emmons@arm.comcpu.addCheckerCpu() 5710747SChris.Emmons@arm.comcpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 5812026Sweipingliao@google.com MyL1Cache(size = '256kB'), 5912026Sweipingliao@google.com MyCache(size = '2MB')) 6010747SChris.Emmons@arm.com# @todo Note that the L2 latency here is unmodified and 2 cycles, 6110747SChris.Emmons@arm.com# should set hit latency and response latency to 20 cycles as for 622934Sktlim@umich.edu# other scripts 632934Sktlim@umich.educpu.clock = '2GHz' 642934Sktlim@umich.edu 652934Sktlim@umich.edusystem = System(cpu = cpu, 662934Sktlim@umich.edu physmem = SimpleMemory(), 672934Sktlim@umich.edu membus = CoherentBus()) 682934Sktlim@umich.edusystem.system_port = system.membus.slave 6910720Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master 706122SSteve.Reinhardt@amd.comcpu.connectAllPorts(system.membus) 716122SSteve.Reinhardt@amd.com 726122SSteve.Reinhardt@amd.comroot = Root(full_system = False, system = system) 7310594Sgabeblack@google.com