memtest.py revision 9788:5558ee8dd7d9
16145Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26145Snate@binkert.org# All rights reserved. 36145Snate@binkert.org# 46145Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56145Snate@binkert.org# modification, are permitted provided that the following conditions are 66145Snate@binkert.org# met: redistributions of source code must retain the above copyright 76145Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86145Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96145Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106145Snate@binkert.org# documentation and/or other materials provided with the distribution; 116145Snate@binkert.org# neither the name of the copyright holders nor the names of its 126145Snate@binkert.org# contributors may be used to endorse or promote products derived from 136145Snate@binkert.org# this software without specific prior written permission. 146145Snate@binkert.org# 156145Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166145Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176145Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186145Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196145Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206145Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216145Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226145Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236145Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246145Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256145Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266145Snate@binkert.org# 276145Snate@binkert.org# Authors: Ron Dreslinski 286145Snate@binkert.org 297454Snate@binkert.orgimport m5 307454Snate@binkert.orgfrom m5.objects import * 318645Snilay@cs.wisc.edum5.util.addToPath('../configs/common') 327454Snate@binkert.orgfrom Caches import * 337054Snate@binkert.org 347054Snate@binkert.org#MAX CORES IS 8 with the fals sharing method 357054Snate@binkert.orgnb_cores = 8 368259SBrad.Beckmann@amd.comcpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 376154Snate@binkert.org 386154Snate@binkert.org# system simulated 396145Snate@binkert.orgsystem = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 407055Snate@binkert.org funcbus = NoncoherentBus(), 417454Snate@binkert.org physmem = SimpleMemory(), 427454Snate@binkert.org membus = CoherentBus(width=16)) 437055Snate@binkert.org 449274Snilay@cs.wisc.edu# l2cache & bus 456145Snate@binkert.orgsystem.toL2Bus = CoherentBus(clock="2GHz", width=16) 469274Snilay@cs.wisc.edusystem.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 476145Snate@binkert.orgsystem.l2c.cpu_side = system.toL2Bus.master 486145Snate@binkert.org 496145Snate@binkert.org# connect l2c to membus 506145Snate@binkert.orgsystem.l2c.mem_side = system.membus.slave 517054Snate@binkert.org 526145Snate@binkert.org# add L1 caches 537054Snate@binkert.orgfor cpu in cpus: 547454Snate@binkert.org cpu.l1c = L1Cache(size = '32kB', assoc = 4) 556145Snate@binkert.org cpu.l1c.cpu_side = cpu.test 567054Snate@binkert.org cpu.l1c.mem_side = system.toL2Bus.slave 577454Snate@binkert.org system.funcbus.slave = cpu.functional 586145Snate@binkert.org 596145Snate@binkert.orgsystem.system_port = system.membus.slave 607054Snate@binkert.org 619274Snilay@cs.wisc.edu# connect reference memory to funcbus 629274Snilay@cs.wisc.edusystem.funcmem.port = system.funcbus.master 639274Snilay@cs.wisc.edu 649274Snilay@cs.wisc.edu# connect memory to membus 659274Snilay@cs.wisc.edusystem.physmem.port = system.membus.master 669274Snilay@cs.wisc.edu 679274Snilay@cs.wisc.edu 687454Snate@binkert.org# ----------------------- 696145Snate@binkert.org# run simulation 709508Snilay@cs.wisc.edu# ----------------------- 719508Snilay@cs.wisc.edu 729508Snilay@cs.wisc.eduroot = Root( full_system = False, system = system ) 739508Snilay@cs.wisc.eduroot.system.mem_mode = 'timing' 749508Snilay@cs.wisc.edu#root.trace.flags="Cache CachePort MemoryAccess" 756145Snate@binkert.org#root.trace.cycle=1 766145Snate@binkert.org 777054Snate@binkert.org