memtest.py revision 8839:eeb293859255
16657Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26657Snate@binkert.org# All rights reserved. 36657Snate@binkert.org# 46657Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56657Snate@binkert.org# modification, are permitted provided that the following conditions are 66657Snate@binkert.org# met: redistributions of source code must retain the above copyright 76657Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86657Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96657Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106657Snate@binkert.org# documentation and/or other materials provided with the distribution; 116657Snate@binkert.org# neither the name of the copyright holders nor the names of its 126657Snate@binkert.org# contributors may be used to endorse or promote products derived from 136657Snate@binkert.org# this software without specific prior written permission. 146657Snate@binkert.org# 156657Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166657Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176657Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186657Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196657Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206657Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216657Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226657Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236657Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246657Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256657Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266657Snate@binkert.org# 276657Snate@binkert.org# Authors: Ron Dreslinski 286657Snate@binkert.org 296657Snate@binkert.orgimport m5 306657Snate@binkert.orgfrom m5.objects import * 316657Snate@binkert.org 326657Snate@binkert.org# -------------------- 336657Snate@binkert.org# Base L1 Cache 346657Snate@binkert.org# ==================== 356657Snate@binkert.org 366657Snate@binkert.orgclass L1(BaseCache): 376657Snate@binkert.org latency = '1ns' 386657Snate@binkert.org block_size = 64 396657Snate@binkert.org mshrs = 12 406657Snate@binkert.org tgts_per_mshr = 8 416657Snate@binkert.org is_top_level = True 426657Snate@binkert.org 436657Snate@binkert.org# ---------------------- 446657Snate@binkert.org# Base L2 Cache 456657Snate@binkert.org# ---------------------- 466657Snate@binkert.org 476657Snate@binkert.orgclass L2(BaseCache): 486657Snate@binkert.org block_size = 64 497839Snilay@cs.wisc.edu latency = '10ns' 506657Snate@binkert.org mshrs = 92 517839Snilay@cs.wisc.edu tgts_per_mshr = 16 526657Snate@binkert.org write_buffers = 8 536657Snate@binkert.org 546657Snate@binkert.org#MAX CORES IS 8 with the fals sharing method 556657Snate@binkert.orgnb_cores = 8 567839Snilay@cs.wisc.educpus = [ MemTest() for i in xrange(nb_cores) ] 576657Snate@binkert.org 586657Snate@binkert.org# system simulated 596657Snate@binkert.orgsystem = System(cpu = cpus, funcmem = PhysicalMemory(), 606657Snate@binkert.org physmem = PhysicalMemory(), 616657Snate@binkert.org membus = Bus(clock="500GHz", width=16)) 626657Snate@binkert.org 637567SBrad.Beckmann@amd.com# l2cache & bus 646657Snate@binkert.orgsystem.toL2Bus = Bus(clock="500GHz", width=16) 656657Snate@binkert.orgsystem.l2c = L2(size='64kB', assoc=8) 666882SBrad.Beckmann@amd.comsystem.l2c.cpu_side = system.toL2Bus.master 676657Snate@binkert.org 686657Snate@binkert.org# connect l2c to membus 696657Snate@binkert.orgsystem.l2c.mem_side = system.membus.slave 706657Snate@binkert.org 716657Snate@binkert.org# add L1 caches 726657Snate@binkert.orgfor cpu in cpus: 736657Snate@binkert.org cpu.l1c = L1(size = '32kB', assoc = 4) 746657Snate@binkert.org cpu.l1c.cpu_side = cpu.test 757567SBrad.Beckmann@amd.com cpu.l1c.mem_side = system.toL2Bus.slave 76 system.funcmem.port = cpu.functional 77 78system.system_port = system.membus.slave 79 80# connect memory to membus 81system.physmem.port = system.membus.master 82 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Cache CachePort MemoryAccess" 91#root.trace.cycle=1 92 93