memtest-ruby.py revision 9577:91cac7c9c636
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 29796Sprakash.ramrakhyani@arm.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 39796Sprakash.ramrakhyani@arm.com# All rights reserved. 49796Sprakash.ramrakhyani@arm.com# 59796Sprakash.ramrakhyani@arm.com# Redistribution and use in source and binary forms, with or without 69796Sprakash.ramrakhyani@arm.com# modification, are permitted provided that the following conditions are 79796Sprakash.ramrakhyani@arm.com# met: redistributions of source code must retain the above copyright 89796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer; 99796Sprakash.ramrakhyani@arm.com# redistributions in binary form must reproduce the above copyright 109796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer in the 119796Sprakash.ramrakhyani@arm.com# documentation and/or other materials provided with the distribution; 129796Sprakash.ramrakhyani@arm.com# neither the name of the copyright holders nor the names of its 139796Sprakash.ramrakhyani@arm.com# contributors may be used to endorse or promote products derived from 142810SN/A# this software without specific prior written permission. 152810SN/A# 162810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A# 282810SN/A# Authors: Ron Dreslinski 292810SN/A 302810SN/Aimport m5 312810SN/Afrom m5.objects import * 322810SN/Afrom m5.defines import buildEnv 332810SN/Afrom m5.util import addToPath 342810SN/Aimport os, optparse, sys 352810SN/A 362810SN/A# Get paths we might need 372810SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 382810SN/Aconfig_root = os.path.dirname(config_path) 392810SN/Am5_root = os.path.dirname(config_root) 402810SN/AaddToPath(config_root+'/configs/common') 412810SN/AaddToPath(config_root+'/configs/ruby') 422810SN/AaddToPath(config_root+'/configs/topologies') 432810SN/A 442810SN/Aimport Ruby 452810SN/Aimport Options 462810SN/A 472810SN/Aparser = optparse.OptionParser() 482810SN/AOptions.addCommonOptions(parser) 4911486Snikos.nikoleris@arm.com 5011486Snikos.nikoleris@arm.com# Add the ruby specific and protocol specific options 518229Snate@binkert.orgRuby.define_options(parser) 525338Sstever@gmail.com 532810SN/A(options, args) = parser.parse_args() 542810SN/A 552810SN/A# 562810SN/A# Set the default cache size and associativity to be very small to encourage 579796Sprakash.ramrakhyani@arm.com# races between requests and writebacks. 589796Sprakash.ramrakhyani@arm.com# 5910693SMarco.Balboni@ARM.comoptions.l1d_size="256B" 6010360Sandreas.hansson@arm.comoptions.l1i_size="256B" 619796Sprakash.ramrakhyani@arm.comoptions.l2_size="512B" 629796Sprakash.ramrakhyani@arm.comoptions.l3_size="1kB" 639796Sprakash.ramrakhyani@arm.comoptions.l1d_assoc=2 642810SN/Aoptions.l1i_assoc=2 652810SN/Aoptions.l2_assoc=2 662810SN/Aoptions.l3_assoc=2 6710360Sandreas.hansson@arm.com 682810SN/A#MAX CORES IS 8 with the fals sharing method 692810SN/Anb_cores = 8 702810SN/A 712810SN/A# ruby does not support atomic, functional, or uncacheable accesses 729796Sprakash.ramrakhyani@arm.comcpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50, 732810SN/A percent_uncacheable=0, suppress_func_warnings=True) \ 742810SN/A for i in xrange(nb_cores) ] 752810SN/A 762810SN/A# overwrite options.num_cpus with the nb_cores value 779796Sprakash.ramrakhyani@arm.comoptions.num_cpus = nb_cores 782810SN/A 792810SN/A# system simulated 802810SN/Asystem = System(cpu = cpus, 812810SN/A funcmem = SimpleMemory(in_addr_map = False), 822810SN/A physmem = SimpleMemory(null = True), 839796Sprakash.ramrakhyani@arm.com funcbus = NoncoherentBus()) 842810SN/A 852810SN/ARuby.create_system(options, system) 862810SN/A 872810SN/Aassert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 889796Sprakash.ramrakhyani@arm.com 892810SN/Afor (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): 902810SN/A # 912810SN/A # Tie the cpu test and functional ports to the ruby cpu ports and 922810SN/A # physmem, respectively 939796Sprakash.ramrakhyani@arm.com # 942810SN/A cpus[i].test = ruby_port.slave 952810SN/A cpus[i].functional = system.funcbus.slave 962810SN/A 972810SN/A # 989796Sprakash.ramrakhyani@arm.com # Since the memtester is incredibly bursty, increase the deadlock 992810SN/A # threshold to 1 million cycles 1002810SN/A # 1012810SN/A ruby_port.deadlock_threshold = 1000000 1022810SN/A 1032810SN/A# connect reference memory to funcbus 1042810SN/Asystem.funcmem.port = system.funcbus.master 1059796Sprakash.ramrakhyani@arm.com 1062810SN/A# ----------------------- 1072810SN/A# run simulation 1082810SN/A# ----------------------- 1096978SLisa.Hsu@amd.com 1108833Sdam.sunwoo@arm.comroot = Root(full_system = False, system = system) 1119796Sprakash.ramrakhyani@arm.comroot.system.mem_mode = 'timing' 1128833Sdam.sunwoo@arm.com 1136978SLisa.Hsu@amd.com# Not much point in this being higher than the L1 latency 1146978SLisa.Hsu@amd.comm5.ticks.setGlobalFrequency('1ns') 1158833Sdam.sunwoo@arm.com