memtest-ruby.py revision 9113
12440SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22440SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 32440SN/A# All rights reserved. 42440SN/A# 52440SN/A# Redistribution and use in source and binary forms, with or without 62440SN/A# modification, are permitted provided that the following conditions are 72440SN/A# met: redistributions of source code must retain the above copyright 82440SN/A# notice, this list of conditions and the following disclaimer; 92440SN/A# redistributions in binary form must reproduce the above copyright 102440SN/A# notice, this list of conditions and the following disclaimer in the 112440SN/A# documentation and/or other materials provided with the distribution; 122440SN/A# neither the name of the copyright holders nor the names of its 132440SN/A# contributors may be used to endorse or promote products derived from 142440SN/A# this software without specific prior written permission. 152440SN/A# 162440SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A# 282665SN/A# Authors: Ron Dreslinski 292440SN/A 302440SN/Aimport m5 316329Sgblack@eecs.umich.edufrom m5.objects import * 326329Sgblack@eecs.umich.edufrom m5.defines import buildEnv 332440SN/Afrom m5.util import addToPath 348961Sgblack@eecs.umich.eduimport os, optparse, sys 356327SN/A 366329Sgblack@eecs.umich.edu# Get paths we might need 372440SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 385569SN/Aconfig_root = os.path.dirname(config_path) 392972SN/Am5_root = os.path.dirname(config_root) 406329Sgblack@eecs.umich.eduaddToPath(config_root+'/configs/common') 416329Sgblack@eecs.umich.eduaddToPath(config_root+'/configs/ruby') 426327SN/AaddToPath(config_root+'/configs/topologies') 439046SAli.Saidi@ARM.com 449046SAli.Saidi@ARM.comimport Ruby 459046SAli.Saidi@ARM.comimport Options 466329Sgblack@eecs.umich.edu 476329Sgblack@eecs.umich.eduparser = optparse.OptionParser() 486327SN/AOptions.addCommonOptions(parser) 496329Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options 516329Sgblack@eecs.umich.eduRuby.define_options(parser) 526327SN/A 536329Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 546329Sgblack@eecs.umich.edu 556327SN/A# 569920Syasuko.eckert@amd.com# Set the default cache size and associativity to be very small to encourage 579920Syasuko.eckert@amd.com# races between requests and writebacks. 589920Syasuko.eckert@amd.com# 596329Sgblack@eecs.umich.eduoptions.l1d_size="256B" 606329Sgblack@eecs.umich.eduoptions.l1i_size="256B" 616329Sgblack@eecs.umich.eduoptions.l2_size="512B" 626329Sgblack@eecs.umich.eduoptions.l3_size="1kB" 636329Sgblack@eecs.umich.eduoptions.l1d_assoc=2 646329Sgblack@eecs.umich.eduoptions.l1i_assoc=2 656321SN/Aoptions.l2_assoc=2 666329Sgblack@eecs.umich.eduoptions.l3_assoc=2 676329Sgblack@eecs.umich.edu 686329Sgblack@eecs.umich.edu#MAX CORES IS 8 with the fals sharing method 696329Sgblack@eecs.umich.edunb_cores = 8 706329Sgblack@eecs.umich.edu 716329Sgblack@eecs.umich.edu# ruby does not support atomic, functional, or uncacheable accesses 727699Sgblack@eecs.umich.educpus = [ MemTest(atomic=False, percent_functional=50, 737699Sgblack@eecs.umich.edu percent_uncacheable=0, suppress_func_warnings=True) \ 746329Sgblack@eecs.umich.edu for i in xrange(nb_cores) ] 755569SN/A 766329Sgblack@eecs.umich.edu# overwrite options.num_cpus with the nb_cores value 776329Sgblack@eecs.umich.eduoptions.num_cpus = nb_cores 786329Sgblack@eecs.umich.edu 796329Sgblack@eecs.umich.edu# system simulated 806329Sgblack@eecs.umich.edusystem = System(cpu = cpus, 816329Sgblack@eecs.umich.edu funcmem = SimpleMemory(in_addr_map = False), 826329Sgblack@eecs.umich.edu physmem = SimpleMemory()) 836329Sgblack@eecs.umich.edu 846329Sgblack@eecs.umich.eduRuby.create_system(options, system) 856329Sgblack@eecs.umich.edu 866329Sgblack@eecs.umich.eduassert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 876329Sgblack@eecs.umich.edu 886329Sgblack@eecs.umich.edufor (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): 896329Sgblack@eecs.umich.edu # 906329Sgblack@eecs.umich.edu # Tie the cpu test and functional ports to the ruby cpu ports and 916329Sgblack@eecs.umich.edu # physmem, respectively 926329Sgblack@eecs.umich.edu # 936329Sgblack@eecs.umich.edu cpus[i].test = ruby_port.slave 946329Sgblack@eecs.umich.edu cpus[i].functional = system.funcmem.port 956329Sgblack@eecs.umich.edu 966329Sgblack@eecs.umich.edu # 979920Syasuko.eckert@amd.com # Since the memtester is incredibly bursty, increase the deadlock 989917Ssteve.reinhardt@amd.com # threshold to 1 million cycles 996329Sgblack@eecs.umich.edu # 1006329Sgblack@eecs.umich.edu ruby_port.deadlock_threshold = 1000000 1017699Sgblack@eecs.umich.edu 1026329Sgblack@eecs.umich.edu # 1036329Sgblack@eecs.umich.edu # Ruby doesn't need the backing image of memory when running with 1046329Sgblack@eecs.umich.edu # the tester. 1056329Sgblack@eecs.umich.edu # 1069918Ssteve.reinhardt@amd.com ruby_port.access_phys_mem = False 1079918Ssteve.reinhardt@amd.com 1089920Syasuko.eckert@amd.com# ----------------------- 10910935Snilay@cs.wisc.edu# run simulation 1109918Ssteve.reinhardt@amd.com# ----------------------- 1116329Sgblack@eecs.umich.edu 1125569SN/Aroot = Root(full_system = False, system = system) 1132440SN/Aroot.system.mem_mode = 'timing' 1142440SN/A 1155569SN/A# Not much point in this being higher than the L1 latency 116m5.ticks.setGlobalFrequency('1ns') 117