memtest-ruby.py revision 8732:fd510b6e124d
15390SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 25445SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 35390SN/A# All rights reserved. 45390SN/A# 55390SN/A# Redistribution and use in source and binary forms, with or without 65390SN/A# modification, are permitted provided that the following conditions are 75390SN/A# met: redistributions of source code must retain the above copyright 85390SN/A# notice, this list of conditions and the following disclaimer; 95390SN/A# redistributions in binary form must reproduce the above copyright 105390SN/A# notice, this list of conditions and the following disclaimer in the 115390SN/A# documentation and/or other materials provided with the distribution; 125390SN/A# neither the name of the copyright holders nor the names of its 135390SN/A# contributors may be used to endorse or promote products derived from 145390SN/A# this software without specific prior written permission. 155390SN/A# 165390SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A# 285390SN/A# Authors: Ron Dreslinski 295390SN/A 305390SN/Aimport m5 315636Sgblack@eecs.umich.edufrom m5.objects import * 325636Sgblack@eecs.umich.edufrom m5.defines import buildEnv 335390SN/Afrom m5.util import addToPath 345636Sgblack@eecs.umich.eduimport os, optparse, sys 355636Sgblack@eecs.umich.edu 365390SN/Aif buildEnv['FULL_SYSTEM']: 375390SN/A panic("This script requires system-emulation mode (*_SE).") 385390SN/A 395390SN/A# Get paths we might need 405445SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 415445SN/Aconfig_root = os.path.dirname(config_path) 425636Sgblack@eecs.umich.edum5_root = os.path.dirname(config_root) 435390SN/AaddToPath(config_root+'/configs/common') 445445SN/AaddToPath(config_root+'/configs/ruby') 455636Sgblack@eecs.umich.edu 465636Sgblack@eecs.umich.eduimport Ruby 475445SN/A 485445SN/Aparser = optparse.OptionParser() 495445SN/A 505445SN/A# 515445SN/A# Add the ruby specific and protocol specific options 525445SN/A# 535445SN/ARuby.define_options(parser) 545445SN/A 555445SN/Aexecfile(os.path.join(config_root, "configs/common", "Options.py")) 565445SN/A 575390SN/A(options, args) = parser.parse_args() 585636Sgblack@eecs.umich.edu 595390SN/A# 605636Sgblack@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 615636Sgblack@eecs.umich.edu# races between requests and writebacks. 625636Sgblack@eecs.umich.edu# 635636Sgblack@eecs.umich.eduoptions.l1d_size="256B" 645636Sgblack@eecs.umich.eduoptions.l1i_size="256B" 655636Sgblack@eecs.umich.eduoptions.l2_size="512B" 665636Sgblack@eecs.umich.eduoptions.l3_size="1kB" 675826Sgblack@eecs.umich.eduoptions.l1d_assoc=2 685636Sgblack@eecs.umich.eduoptions.l1i_assoc=2 695636Sgblack@eecs.umich.eduoptions.l2_assoc=2 705636Sgblack@eecs.umich.eduoptions.l3_assoc=2 715390SN/A 725390SN/A#MAX CORES IS 8 with the fals sharing method 735390SN/Anb_cores = 8 745390SN/A 755390SN/A# ruby does not support atomic, functional, or uncacheable accesses 765390SN/Acpus = [ MemTest(atomic=False, percent_functional=50, 775390SN/A percent_uncacheable=0, suppress_func_warnings=True) \ 785390SN/A for i in xrange(nb_cores) ] 795636Sgblack@eecs.umich.edu 80# overwrite options.num_cpus with the nb_cores value 81options.num_cpus = nb_cores 82 83# system simulated 84system = System(cpu = cpus, 85 funcmem = PhysicalMemory(), 86 physmem = PhysicalMemory()) 87 88Ruby.create_system(options, system) 89 90assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 91 92for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): 93 # 94 # Tie the cpu test and functional ports to the ruby cpu ports and 95 # physmem, respectively 96 # 97 cpus[i].test = ruby_port.port 98 cpus[i].functional = system.funcmem.port 99 100 # 101 # Since the memtester is incredibly bursty, increase the deadlock 102 # threshold to 1 million cycles 103 # 104 ruby_port.deadlock_threshold = 1000000 105 106 # 107 # Ruby doesn't need the backing image of memory when running with 108 # the tester. 109 # 110 ruby_port.access_phys_mem = False 111 112# ----------------------- 113# run simulation 114# ----------------------- 115 116root = Root(system = system) 117root.system.mem_mode = 'timing' 118 119# Not much point in this being higher than the L1 latency 120m5.ticks.setGlobalFrequency('1ns') 121