memtest-ruby.py revision 7938:685719afafe6
110259SAndrew.Bardsley@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 210259SAndrew.Bardsley@arm.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 310259SAndrew.Bardsley@arm.com# All rights reserved. 410259SAndrew.Bardsley@arm.com# 510259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com# 1610259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com# 2810259SAndrew.Bardsley@arm.com# Authors: Ron Dreslinski 2910259SAndrew.Bardsley@arm.com 3010259SAndrew.Bardsley@arm.comimport m5 3110259SAndrew.Bardsley@arm.comfrom m5.objects import * 3210259SAndrew.Bardsley@arm.comfrom m5.defines import buildEnv 3310259SAndrew.Bardsley@arm.comfrom m5.util import addToPath 3410259SAndrew.Bardsley@arm.comimport os, optparse, sys 3510259SAndrew.Bardsley@arm.com 3610259SAndrew.Bardsley@arm.comif buildEnv['FULL_SYSTEM']: 3710259SAndrew.Bardsley@arm.com panic("This script requires system-emulation mode (*_SE).") 3810259SAndrew.Bardsley@arm.com 3910259SAndrew.Bardsley@arm.com# Get paths we might need 4010259SAndrew.Bardsley@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 4110259SAndrew.Bardsley@arm.comconfig_root = os.path.dirname(config_path) 4210259SAndrew.Bardsley@arm.comm5_root = os.path.dirname(config_root) 4310259SAndrew.Bardsley@arm.comaddToPath(config_root+'/configs/common') 4410259SAndrew.Bardsley@arm.comaddToPath(config_root+'/configs/ruby') 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.comimport Ruby 4710259SAndrew.Bardsley@arm.com 4810259SAndrew.Bardsley@arm.comparser = optparse.OptionParser() 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com# 5110259SAndrew.Bardsley@arm.com# Add the ruby specific and protocol specific options 5210259SAndrew.Bardsley@arm.com# 5310259SAndrew.Bardsley@arm.comRuby.define_options(parser) 5410259SAndrew.Bardsley@arm.com 5510259SAndrew.Bardsley@arm.comexecfile(os.path.join(config_root, "configs/common", "Options.py")) 5610259SAndrew.Bardsley@arm.com 5710259SAndrew.Bardsley@arm.com(options, args) = parser.parse_args() 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.com# 6010259SAndrew.Bardsley@arm.com# Set the default cache size and associativity to be very small to encourage 6110259SAndrew.Bardsley@arm.com# races between requests and writebacks. 6210259SAndrew.Bardsley@arm.com# 6310259SAndrew.Bardsley@arm.comoptions.l1d_size="256B" 6410259SAndrew.Bardsley@arm.comoptions.l1i_size="256B" 6510259SAndrew.Bardsley@arm.comoptions.l2_size="512B" 6610259SAndrew.Bardsley@arm.comoptions.l3_size="1kB" 67options.l1d_assoc=2 68options.l1i_assoc=2 69options.l2_assoc=2 70options.l3_assoc=2 71 72#MAX CORES IS 8 with the fals sharing method 73nb_cores = 8 74 75# ruby does not support atomic, functional, or uncacheable accesses 76cpus = [ MemTest(atomic=False, percent_functional=0, \ 77 percent_uncacheable=0) \ 78 for i in xrange(nb_cores) ] 79 80# overwrite options.num_cpus with the nb_cores value 81options.num_cpus = nb_cores 82 83# system simulated 84system = System(cpu = cpus, 85 funcmem = PhysicalMemory(), 86 physmem = PhysicalMemory()) 87 88system.ruby = Ruby.create_system(options, system) 89 90assert(len(cpus) == len(system.ruby.cpu_ruby_ports)) 91 92for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports): 93 # 94 # Tie the cpu test and functional ports to the ruby cpu ports and 95 # physmem, respectively 96 # 97 cpus[i].test = ruby_port.port 98 cpus[i].functional = system.funcmem.port 99 100 # 101 # Since the memtester is incredibly bursty, increase the deadlock 102 # threshold to 1 million cycles 103 # 104 ruby_port.deadlock_threshold = 1000000 105 106# ----------------------- 107# run simulation 108# ----------------------- 109 110root = Root(system = system) 111root.system.mem_mode = 'timing' 112 113# Not much point in this being higher than the L1 latency 114m5.ticks.setGlobalFrequency('1ns') 115