memtest-ruby.py revision 10524:fff17530cef6
13569Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23569Sgblack@eecs.umich.edu# Copyright (c) 2010 Advanced Micro Devices, Inc. 33569Sgblack@eecs.umich.edu# All rights reserved. 43569Sgblack@eecs.umich.edu# 53569Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63569Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 73569Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93569Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113569Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123569Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133569Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143569Sgblack@eecs.umich.edu# this software without specific prior written permission. 153569Sgblack@eecs.umich.edu# 163569Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173569Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183569Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193569Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203569Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213569Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223569Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233569Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243569Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253569Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263569Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273569Sgblack@eecs.umich.edu# 283804Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 293569Sgblack@eecs.umich.edu 303569Sgblack@eecs.umich.eduimport m5 313918Ssaidi@eecs.umich.edufrom m5.objects import * 323918Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 333804Ssaidi@eecs.umich.edufrom m5.util import addToPath 347678Sgblack@eecs.umich.eduimport os, optparse, sys 356335Sgblack@eecs.umich.edu 363569Sgblack@eecs.umich.edu# Get paths we might need 373824Ssaidi@eecs.umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 383811Ssaidi@eecs.umich.educonfig_root = os.path.dirname(config_path) 398229Snate@binkert.orgm5_root = os.path.dirname(config_root) 403811Ssaidi@eecs.umich.eduaddToPath(config_root+'/configs/common') 418232Snate@binkert.orgaddToPath(config_root+'/configs/ruby') 428232Snate@binkert.orgaddToPath(config_root+'/configs/topologies') 433823Ssaidi@eecs.umich.edu 443823Ssaidi@eecs.umich.eduimport Ruby 458751Sgblack@eecs.umich.eduimport Options 464103Ssaidi@eecs.umich.edu 473569Sgblack@eecs.umich.eduparser = optparse.OptionParser() 483804Ssaidi@eecs.umich.eduOptions.addCommonOptions(parser) 493804Ssaidi@eecs.umich.edu 504088Sbinkertn@umich.edu# Add the ruby specific and protocol specific options 513569Sgblack@eecs.umich.eduRuby.define_options(parser) 525034Smilesck@eecs.umich.edu 535358Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 548374Sksewell@umich.edu 553804Ssaidi@eecs.umich.edu# 563804Ssaidi@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 573804Ssaidi@eecs.umich.edu# races between requests and writebacks. 585555Snate@binkert.org# 593569Sgblack@eecs.umich.eduoptions.l1d_size="256B" 603804Ssaidi@eecs.umich.eduoptions.l1i_size="256B" 613918Ssaidi@eecs.umich.eduoptions.l2_size="512B" 623881Ssaidi@eecs.umich.eduoptions.l3_size="1kB" 633881Ssaidi@eecs.umich.eduoptions.l1d_assoc=2 643881Ssaidi@eecs.umich.eduoptions.l1i_assoc=2 654990Sgblack@eecs.umich.eduoptions.l2_assoc=2 664990Sgblack@eecs.umich.eduoptions.l3_assoc=2 674990Sgblack@eecs.umich.eduoptions.ports=32 684990Sgblack@eecs.umich.edu 694990Sgblack@eecs.umich.edu#MAX CORES IS 8 with the fals sharing method 704990Sgblack@eecs.umich.edunb_cores = 8 714990Sgblack@eecs.umich.edu 724990Sgblack@eecs.umich.edu# ruby does not support atomic, functional, or uncacheable accesses 734990Sgblack@eecs.umich.educpus = [ MemTest(atomic=False, percent_functional=50, 746022Sgblack@eecs.umich.edu percent_uncacheable=0, suppress_func_warnings=True) \ 756022Sgblack@eecs.umich.edu for i in xrange(nb_cores) ] 766022Sgblack@eecs.umich.edu 773804Ssaidi@eecs.umich.edu# overwrite options.num_cpus with the nb_cores value 783569Sgblack@eecs.umich.eduoptions.num_cpus = nb_cores 793804Ssaidi@eecs.umich.edu 803804Ssaidi@eecs.umich.edu# system simulated 813804Ssaidi@eecs.umich.edusystem = System(cpu = cpus, 823804Ssaidi@eecs.umich.edu funcmem = SimpleMemory(in_addr_map = False), 833881Ssaidi@eecs.umich.edu funcbus = NoncoherentXBar()) 843804Ssaidi@eecs.umich.edu# Dummy voltage domain for all our clock domains 853804Ssaidi@eecs.umich.edusystem.voltage_domain = VoltageDomain() 863804Ssaidi@eecs.umich.edusystem.clk_domain = SrcClockDomain(clock = '1GHz', 873804Ssaidi@eecs.umich.edu voltage_domain = system.voltage_domain) 883804Ssaidi@eecs.umich.edu 893804Ssaidi@eecs.umich.edu# Create a seperate clock domain for components that should run at 903804Ssaidi@eecs.umich.edu# CPUs frequency 913569Sgblack@eecs.umich.edusystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 923569Sgblack@eecs.umich.edu voltage_domain = system.voltage_domain) 933804Ssaidi@eecs.umich.edu 943804Ssaidi@eecs.umich.edu# All cpus are associated with cpu_clk_domain 953826Ssaidi@eecs.umich.edufor cpu in cpus: 963804Ssaidi@eecs.umich.edu cpu.clk_domain = system.cpu_clk_domain 973804Ssaidi@eecs.umich.edu 983826Ssaidi@eecs.umich.edusystem.mem_ranges = AddrRange('256MB') 993907Ssaidi@eecs.umich.edu 1003826Ssaidi@eecs.umich.eduRuby.create_system(options, False, system) 1013811Ssaidi@eecs.umich.edu 1023836Ssaidi@eecs.umich.edu# Create a separate clock domain for Ruby 1033915Ssaidi@eecs.umich.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1043907Ssaidi@eecs.umich.edu voltage_domain = system.voltage_domain) 1053881Ssaidi@eecs.umich.edu 1063881Ssaidi@eecs.umich.eduassert(len(cpus) == len(system.ruby._cpu_ports)) 1073881Ssaidi@eecs.umich.edu 1083881Ssaidi@eecs.umich.edufor (i, ruby_port) in enumerate(system.ruby._cpu_ports): 1093907Ssaidi@eecs.umich.edu # 1103881Ssaidi@eecs.umich.edu # Tie the cpu test and functional ports to the ruby cpu ports and 1115555Snate@binkert.org # physmem, respectively 1125555Snate@binkert.org # 1135555Snate@binkert.org cpus[i].test = ruby_port.slave 1143881Ssaidi@eecs.umich.edu cpus[i].functional = system.funcbus.slave 1153881Ssaidi@eecs.umich.edu 1163907Ssaidi@eecs.umich.edu # 1173907Ssaidi@eecs.umich.edu # Since the memtester is incredibly bursty, increase the deadlock 1183907Ssaidi@eecs.umich.edu # threshold to 1 million cycles 1193907Ssaidi@eecs.umich.edu # 1203907Ssaidi@eecs.umich.edu ruby_port.deadlock_threshold = 1000000 1213907Ssaidi@eecs.umich.edu 1223907Ssaidi@eecs.umich.edu# connect reference memory to funcbus 1233907Ssaidi@eecs.umich.edusystem.funcmem.port = system.funcbus.master 1243907Ssaidi@eecs.umich.edu 1253907Ssaidi@eecs.umich.edu# ----------------------- 1263907Ssaidi@eecs.umich.edu# run simulation 1273907Ssaidi@eecs.umich.edu# ----------------------- 1283907Ssaidi@eecs.umich.edu 1293907Ssaidi@eecs.umich.eduroot = Root(full_system = False, system = system) 1303907Ssaidi@eecs.umich.eduroot.system.mem_mode = 'timing' 1313907Ssaidi@eecs.umich.edu 1323907Ssaidi@eecs.umich.edu# Not much point in this being higher than the L1 latency 1333907Ssaidi@eecs.umich.edum5.ticks.setGlobalFrequency('1ns') 1343907Ssaidi@eecs.umich.edu