memtest-ruby.py revision 13718
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210028SGiacomo.Gabrielli@arm.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 310028SGiacomo.Gabrielli@arm.com# All rights reserved. 410028SGiacomo.Gabrielli@arm.com# 510028SGiacomo.Gabrielli@arm.com# Redistribution and use in source and binary forms, with or without 610028SGiacomo.Gabrielli@arm.com# modification, are permitted provided that the following conditions are 710028SGiacomo.Gabrielli@arm.com# met: redistributions of source code must retain the above copyright 810028SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer; 910028SGiacomo.Gabrielli@arm.com# redistributions in binary form must reproduce the above copyright 1010028SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer in the 1110028SGiacomo.Gabrielli@arm.com# documentation and/or other materials provided with the distribution; 1210028SGiacomo.Gabrielli@arm.com# neither the name of the copyright holders nor the names of its 1310028SGiacomo.Gabrielli@arm.com# contributors may be used to endorse or promote products derived from 142810SN/A# this software without specific prior written permission. 152810SN/A# 162810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A# 282810SN/A# Authors: Ron Dreslinski 292810SN/A 302810SN/Aimport m5 312810SN/Afrom m5.objects import * 322810SN/Afrom m5.defines import buildEnv 332810SN/Afrom m5.util import addToPath 342810SN/Aimport os, optparse, sys 352810SN/A 362810SN/Am5.util.addToPath('../configs/') 372810SN/A 382810SN/Afrom ruby import Ruby 392810SN/Afrom common import Options 402810SN/A 412810SN/Aparser = optparse.OptionParser() 422810SN/AOptions.addCommonOptions(parser) 432810SN/A 442810SN/A# Add the ruby specific and protocol specific options 453861SN/ARuby.define_options(parser) 462810SN/A 472810SN/A(options, args) = parser.parse_args() 482810SN/A 492810SN/A# 502810SN/A# Set the default cache size and associativity to be very small to encourage 518229Snate@binkert.org# races between requests and writebacks. 528229Snate@binkert.org# 535338Sstever@gmail.comoptions.l1d_size="256B" 548831Smrinmoy.ghosh@arm.comoptions.l1i_size="256B" 552810SN/Aoptions.l2_size="512B" 563861SN/Aoptions.l3_size="1kB" 572810SN/Aoptions.l1d_assoc=2 582810SN/Aoptions.l1i_assoc=2 592810SN/Aoptions.l2_assoc=2 605875Ssteve.reinhardt@amd.comoptions.l3_assoc=2 615875Ssteve.reinhardt@amd.comoptions.ports=32 625875Ssteve.reinhardt@amd.com 635875Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method 645875Ssteve.reinhardt@amd.comnb_cores = 8 655875Ssteve.reinhardt@amd.com 665875Ssteve.reinhardt@amd.com# ruby does not support atomic, functional, or uncacheable accesses 675875Ssteve.reinhardt@amd.comcpus = [ MemTest(percent_functional=50, 682810SN/A percent_uncacheable=0, suppress_func_warnings=True) \ 692810SN/A for i in range(nb_cores) ] 705875Ssteve.reinhardt@amd.com 715875Ssteve.reinhardt@amd.com# overwrite options.num_cpus with the nb_cores value 7210028SGiacomo.Gabrielli@arm.comoptions.num_cpus = nb_cores 732810SN/A 745875Ssteve.reinhardt@amd.com# system simulated 755875Ssteve.reinhardt@amd.comsystem = System(cpu = cpus) 762810SN/A# Dummy voltage domain for all our clock domains 775875Ssteve.reinhardt@amd.comsystem.voltage_domain = VoltageDomain() 782810SN/Asystem.clk_domain = SrcClockDomain(clock = '1GHz', 792810SN/A voltage_domain = system.voltage_domain) 802810SN/A 818831Smrinmoy.ghosh@arm.com# Create a seperate clock domain for components that should run at 828831Smrinmoy.ghosh@arm.com# CPUs frequency 832810SN/Asystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 842810SN/A voltage_domain = system.voltage_domain) 852810SN/A 862810SN/A# All cpus are associated with cpu_clk_domain 872810SN/Afor cpu in cpus: 883349SN/A cpu.clk_domain = system.cpu_clk_domain 899288Sandreas.hansson@arm.com 902810SN/Asystem.mem_ranges = AddrRange('256MB') 912810SN/A 922810SN/ARuby.create_system(options, False, system) 93 94# Create a separate clock domain for Ruby 95system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 96 voltage_domain = system.voltage_domain) 97 98assert(len(cpus) == len(system.ruby._cpu_ports)) 99 100for (i, ruby_port) in enumerate(system.ruby._cpu_ports): 101 # 102 # Tie the cpu port to the ruby cpu ports and 103 # physmem, respectively 104 # 105 cpus[i].port = ruby_port.slave 106 107 # 108 # Since the memtester is incredibly bursty, increase the deadlock 109 # threshold to 1 million cycles 110 # 111 ruby_port.deadlock_threshold = 1000000 112 113# ----------------------- 114# run simulation 115# ----------------------- 116 117root = Root(full_system = False, system = system) 118root.system.mem_mode = 'timing' 119