memtest-ruby.py revision 10519
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26928SBrad.Beckmann@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 36166Ssteve.reinhardt@amd.com# All rights reserved. 46166Ssteve.reinhardt@amd.com# 56166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 66166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 76166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 86166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 96166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 106166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 116166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 126166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 136166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 146166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 156166Ssteve.reinhardt@amd.com# 166166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276166Ssteve.reinhardt@amd.com# 286166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski 296166Ssteve.reinhardt@amd.com 306166Ssteve.reinhardt@amd.comimport m5 316166Ssteve.reinhardt@amd.comfrom m5.objects import * 326919SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336919SBrad.Beckmann@amd.comfrom m5.util import addToPath 346919SBrad.Beckmann@amd.comimport os, optparse, sys 356166Ssteve.reinhardt@amd.com 366919SBrad.Beckmann@amd.com# Get paths we might need 376919SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 386919SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 396919SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 406919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common') 416919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby') 429113SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/topologies') 436919SBrad.Beckmann@amd.com 446919SBrad.Beckmann@amd.comimport Ruby 458920Snilay@cs.wisc.eduimport Options 466919SBrad.Beckmann@amd.com 476919SBrad.Beckmann@amd.comparser = optparse.OptionParser() 488920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 496919SBrad.Beckmann@amd.com 507570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 517570SBrad.Beckmann@amd.comRuby.define_options(parser) 526919SBrad.Beckmann@amd.com 536919SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 546166Ssteve.reinhardt@amd.com 557570SBrad.Beckmann@amd.com# 567570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 577570SBrad.Beckmann@amd.com# races between requests and writebacks. 587570SBrad.Beckmann@amd.com# 597570SBrad.Beckmann@amd.comoptions.l1d_size="256B" 607570SBrad.Beckmann@amd.comoptions.l1i_size="256B" 617570SBrad.Beckmann@amd.comoptions.l2_size="512B" 627570SBrad.Beckmann@amd.comoptions.l3_size="1kB" 637570SBrad.Beckmann@amd.comoptions.l1d_assoc=2 647570SBrad.Beckmann@amd.comoptions.l1i_assoc=2 657570SBrad.Beckmann@amd.comoptions.l2_assoc=2 667570SBrad.Beckmann@amd.comoptions.l3_assoc=2 679841Snilay@cs.wisc.eduoptions.ports=32 687570SBrad.Beckmann@amd.com 696166Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method 706166Ssteve.reinhardt@amd.comnb_cores = 8 716928SBrad.Beckmann@amd.com 726928SBrad.Beckmann@amd.com# ruby does not support atomic, functional, or uncacheable accesses 739793Sakash.bagdia@arm.comcpus = [ MemTest(atomic=False, percent_functional=50, 748436SBrad.Beckmann@amd.com percent_uncacheable=0, suppress_func_warnings=True) \ 756928SBrad.Beckmann@amd.com for i in xrange(nb_cores) ] 766166Ssteve.reinhardt@amd.com 776919SBrad.Beckmann@amd.com# overwrite options.num_cpus with the nb_cores value 786919SBrad.Beckmann@amd.comoptions.num_cpus = nb_cores 796919SBrad.Beckmann@amd.com 806919SBrad.Beckmann@amd.com# system simulated 816919SBrad.Beckmann@amd.comsystem = System(cpu = cpus, 828931Sandreas.hansson@arm.com funcmem = SimpleMemory(in_addr_map = False), 839577Snilay@cs.wisc.edu physmem = SimpleMemory(null = True), 8410405Sandreas.hansson@arm.com funcbus = NoncoherentXBar()) 859827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 869827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain() 879827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 889827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 899793Sakash.bagdia@arm.com 909793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 919793Sakash.bagdia@arm.com# CPUs frequency 929827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 939827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 949793Sakash.bagdia@arm.com 959793Sakash.bagdia@arm.com# All cpus are associated with cpu_clk_domain 969793Sakash.bagdia@arm.comfor cpu in cpus: 979793Sakash.bagdia@arm.com cpu.clk_domain = system.cpu_clk_domain 986289Snate@binkert.org 999826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB') 1009826Sandreas.hansson@arm.com 10110519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 1026166Ssteve.reinhardt@amd.com 1039793Sakash.bagdia@arm.com# Create a separate clock domain for Ruby 1049827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1059827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 1069793Sakash.bagdia@arm.com 10710120Snilay@cs.wisc.eduassert(len(cpus) == len(system.ruby._cpu_ports)) 1086166Ssteve.reinhardt@amd.com 10910120Snilay@cs.wisc.edufor (i, ruby_port) in enumerate(system.ruby._cpu_ports): 1106919SBrad.Beckmann@amd.com # 1116919SBrad.Beckmann@amd.com # Tie the cpu test and functional ports to the ruby cpu ports and 1126919SBrad.Beckmann@amd.com # physmem, respectively 1136919SBrad.Beckmann@amd.com # 1148839Sandreas.hansson@arm.com cpus[i].test = ruby_port.slave 1159120Sandreas.hansson@arm.com cpus[i].functional = system.funcbus.slave 1167938SBrad.Beckmann@amd.com 1177938SBrad.Beckmann@amd.com # 1187938SBrad.Beckmann@amd.com # Since the memtester is incredibly bursty, increase the deadlock 1197938SBrad.Beckmann@amd.com # threshold to 1 million cycles 1207938SBrad.Beckmann@amd.com # 1217938SBrad.Beckmann@amd.com ruby_port.deadlock_threshold = 1000000 1226166Ssteve.reinhardt@amd.com 1239120Sandreas.hansson@arm.com# connect reference memory to funcbus 1249120Sandreas.hansson@arm.comsystem.funcmem.port = system.funcbus.master 1259120Sandreas.hansson@arm.com 1266166Ssteve.reinhardt@amd.com# ----------------------- 1276166Ssteve.reinhardt@amd.com# run simulation 1286166Ssteve.reinhardt@amd.com# ----------------------- 1296166Ssteve.reinhardt@amd.com 1308801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 1316166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'timing' 1326928SBrad.Beckmann@amd.com 1336928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1346928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 135