base_config.py revision 9835
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37# Andreas Hansson 38 39from abc import ABCMeta, abstractmethod 40import m5 41from m5.objects import * 42from m5.proxy import * 43m5.util.addToPath('../configs/common') 44import FSConfig 45from Caches import * 46 47_have_kvm_support = 'BaseKvmCPU' in globals() 48 49class BaseSystem(object): 50 """Base system builder. 51 52 This class provides some basic functionality for creating an ARM 53 system with the usual peripherals (caches, GIC, etc.). It allows 54 customization by defining separate methods for different parts of 55 the initialization process. 56 """ 57 58 __metaclass__ = ABCMeta 59 60 def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 61 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): 62 """Initialize a simple base system. 63 64 Keyword Arguments: 65 mem_mode -- String describing the memory mode (timing or atomic) 66 mem_class -- Memory controller class to use 67 cpu_class -- CPU class to use 68 num_cpus -- Number of CPUs to instantiate 69 checker -- Set to True to add checker CPUs 70 """ 71 self.mem_mode = mem_mode 72 self.mem_class = mem_class 73 self.cpu_class = cpu_class 74 self.num_cpus = num_cpus 75 self.checker = checker 76 77 def create_cpus(self, cpu_clk_domain): 78 """Return a list of CPU objects to add to a system.""" 79 cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, 80 cpu_id=i) 81 for i in range(self.num_cpus) ] 82 if self.checker: 83 for c in cpus: 84 c.addCheckerCpu() 85 return cpus 86 87 def create_caches_private(self, cpu): 88 """Add private caches to a CPU. 89 90 Arguments: 91 cpu -- CPU instance to work on. 92 """ 93 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 94 L1Cache(size='32kB', assoc=4)) 95 96 def create_caches_shared(self, system): 97 """Add shared caches to a system. 98 99 Arguments: 100 system -- System to work on. 101 102 Returns: 103 A bus that CPUs should use to connect to the shared cache. 104 """ 105 system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) 106 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 107 size='4MB', assoc=8) 108 system.l2c.cpu_side = system.toL2Bus.master 109 system.l2c.mem_side = system.membus.slave 110 return system.toL2Bus 111 112 def init_cpu(self, system, cpu, sha_bus): 113 """Initialize a CPU. 114 115 Arguments: 116 system -- System to work on. 117 cpu -- CPU to initialize. 118 """ 119 if not cpu.switched_out: 120 self.create_caches_private(cpu) 121 cpu.createInterruptController() 122 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 123 system.membus) 124 125 def init_kvm(self, system): 126 """Do KVM-specific system initialization. 127 128 Arguments: 129 system -- System to work on. 130 """ 131 system.vm = KvmVM() 132 133 def init_system(self, system): 134 """Initialize a system. 135 136 Arguments: 137 system -- System to initialize. 138 """ 139 self.create_clk_src(system) 140 system.cpu = self.create_cpus(system.cpu_clk_domain) 141 142 if _have_kvm_support and \ 143 any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 144 self.init_kvm(system) 145 146 sha_bus = self.create_caches_shared(system) 147 for cpu in system.cpu: 148 self.init_cpu(system, cpu, sha_bus) 149 150 def create_clk_src(self,system): 151 # Create system clock domain. This provides clock value to every 152 # clocked object that lies beneath it unless explicitly overwritten 153 # by a different clock domain. 154 system.voltage_domain = VoltageDomain() 155 system.clk_domain = SrcClockDomain(clock = '1GHz', 156 voltage_domain = 157 system.voltage_domain) 158 159 # Create a seperate clock domain for components that should 160 # run at CPUs frequency 161 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 162 voltage_domain = 163 system.voltage_domain) 164 165 @abstractmethod 166 def create_system(self): 167 """Create an return an initialized system.""" 168 pass 169 170 @abstractmethod 171 def create_root(self): 172 """Create and return a simulation root using the system 173 defined by this class.""" 174 pass 175 176class BaseSESystem(BaseSystem): 177 """Basic syscall-emulation builder.""" 178 179 def __init__(self, **kwargs): 180 BaseSystem.__init__(self, **kwargs) 181 182 def init_system(self, system): 183 BaseSystem.init_system(self, system) 184 185 def create_system(self): 186 system = System(physmem = self.mem_class(), 187 membus = CoherentBus(), 188 mem_mode = self.mem_mode) 189 system.system_port = system.membus.slave 190 system.physmem.port = system.membus.master 191 self.init_system(system) 192 return system 193 194 def create_root(self): 195 system = self.create_system() 196 m5.ticks.setGlobalFrequency('1THz') 197 return Root(full_system=False, system=system) 198 199class BaseSESystemUniprocessor(BaseSESystem): 200 """Basic syscall-emulation builder for uniprocessor systems. 201 202 Note: This class is only really needed to provide backwards 203 compatibility in existing test cases. 204 """ 205 206 def __init__(self, **kwargs): 207 BaseSESystem.__init__(self, **kwargs) 208 209 def create_caches_private(self, cpu): 210 # The atomic SE configurations do not use caches 211 if self.mem_mode == "timing": 212 # @todo We might want to revisit these rather enthusiastic L1 sizes 213 cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), 214 L1Cache(size='256kB'), 215 L2Cache(size='2MB')) 216 217 def create_caches_shared(self, system): 218 return None 219 220class BaseFSSystem(BaseSystem): 221 """Basic full system builder.""" 222 223 def __init__(self, **kwargs): 224 BaseSystem.__init__(self, **kwargs) 225 226 def init_system(self, system): 227 BaseSystem.init_system(self, system) 228 229 # create the memory controllers and connect them, stick with 230 # the physmem name to avoid bumping all the reference stats 231 system.physmem = [self.mem_class(range = r) 232 for r in system.mem_ranges] 233 for i in xrange(len(system.physmem)): 234 system.physmem[i].port = system.membus.master 235 236 # create the iocache, which by default runs at the system clock 237 system.iocache = IOCache(addr_ranges=system.mem_ranges) 238 system.iocache.cpu_side = system.iobus.master 239 system.iocache.mem_side = system.membus.slave 240 241 def create_root(self): 242 system = self.create_system() 243 m5.ticks.setGlobalFrequency('1THz') 244 return Root(full_system=True, system=system) 245 246class BaseFSSystemUniprocessor(BaseFSSystem): 247 """Basic full system builder for uniprocessor systems. 248 249 Note: This class is only really needed to provide backwards 250 compatibility in existing test cases. 251 """ 252 253 def __init__(self, **kwargs): 254 BaseFSSystem.__init__(self, **kwargs) 255 256 def create_caches_private(self, cpu): 257 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 258 L1Cache(size='32kB', assoc=4), 259 L2Cache(size='4MB', assoc=8)) 260 261 def create_caches_shared(self, system): 262 return None 263 264class BaseFSSwitcheroo(BaseFSSystem): 265 """Uniprocessor system prepared for CPU switching""" 266 267 def __init__(self, cpu_classes, **kwargs): 268 BaseFSSystem.__init__(self, **kwargs) 269 self.cpu_classes = tuple(cpu_classes) 270 271 def create_cpus(self, cpu_clk_domain): 272 cpus = [ cclass(clk_domain = cpu_clk_domain, 273 cpu_id=0, 274 switched_out=True) 275 for cclass in self.cpu_classes ] 276 cpus[0].switched_out = False 277 return cpus 278