base_config.py revision 9654:64b653b3d72f
110235Syasuko.eckert@amd.com# Copyright (c) 2012 ARM Limited 210235Syasuko.eckert@amd.com# All rights reserved. 310235Syasuko.eckert@amd.com# 410235Syasuko.eckert@amd.com# The license below extends only to copyright in the software and shall 510235Syasuko.eckert@amd.com# not be construed as granting a license to any other intellectual 610235Syasuko.eckert@amd.com# property including but not limited to intellectual property relating 710235Syasuko.eckert@amd.com# to a hardware implementation of the functionality of the software 810235Syasuko.eckert@amd.com# licensed hereunder. You may use the software subject to the license 910235Syasuko.eckert@amd.com# terms below provided that you ensure that this notice is replicated 1010235Syasuko.eckert@amd.com# unmodified and in its entirety in all distributions of the software, 1110235Syasuko.eckert@amd.com# modified or unmodified, in source code or in binary form. 1210235Syasuko.eckert@amd.com# 1310235Syasuko.eckert@amd.com# Redistribution and use in source and binary forms, with or without 1410235Syasuko.eckert@amd.com# modification, are permitted provided that the following conditions are 1510235Syasuko.eckert@amd.com# met: redistributions of source code must retain the above copyright 1610235Syasuko.eckert@amd.com# notice, this list of conditions and the following disclaimer; 1710235Syasuko.eckert@amd.com# redistributions in binary form must reproduce the above copyright 1810235Syasuko.eckert@amd.com# notice, this list of conditions and the following disclaimer in the 1910235Syasuko.eckert@amd.com# documentation and/or other materials provided with the distribution; 2010235Syasuko.eckert@amd.com# neither the name of the copyright holders nor the names of its 2110235Syasuko.eckert@amd.com# contributors may be used to endorse or promote products derived from 2210235Syasuko.eckert@amd.com# this software without specific prior written permission. 2310235Syasuko.eckert@amd.com# 2410235Syasuko.eckert@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510235Syasuko.eckert@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610235Syasuko.eckert@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710235Syasuko.eckert@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810235Syasuko.eckert@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910235Syasuko.eckert@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010235Syasuko.eckert@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110235Syasuko.eckert@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210235Syasuko.eckert@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310235Syasuko.eckert@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410235Syasuko.eckert@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510235Syasuko.eckert@amd.com# 3610235Syasuko.eckert@amd.com# Authors: Andreas Sandberg 3710235Syasuko.eckert@amd.com 3810235Syasuko.eckert@amd.comfrom abc import ABCMeta, abstractmethod 3910235Syasuko.eckert@amd.comimport m5 4010235Syasuko.eckert@amd.comfrom m5.objects import * 4110235Syasuko.eckert@amd.comfrom m5.proxy import * 4210235Syasuko.eckert@amd.comm5.util.addToPath('../configs/common') 4310235Syasuko.eckert@amd.comimport FSConfig 4410235Syasuko.eckert@amd.comfrom Caches import * 4510235Syasuko.eckert@amd.com 4610235Syasuko.eckert@amd.com_have_kvm_support = 'BaseKvmCPU' in globals() 4710235Syasuko.eckert@amd.com 4810235Syasuko.eckert@amd.comclass BaseSystem(object): 4910235Syasuko.eckert@amd.com """Base system builder. 5010235Syasuko.eckert@amd.com 5110235Syasuko.eckert@amd.com This class provides some basic functionality for creating an ARM 5210235Syasuko.eckert@amd.com system with the usual peripherals (caches, GIC, etc.). It allows 5310235Syasuko.eckert@amd.com customization by defining separate methods for different parts of 5410235Syasuko.eckert@amd.com the initialization process. 5510235Syasuko.eckert@amd.com """ 5610235Syasuko.eckert@amd.com 5710235Syasuko.eckert@amd.com __metaclass__ = ABCMeta 5810235Syasuko.eckert@amd.com 5910235Syasuko.eckert@amd.com def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, 6010235Syasuko.eckert@amd.com num_cpus=1, checker=False): 6110235Syasuko.eckert@amd.com """Initialize a simple ARM system. 6210235Syasuko.eckert@amd.com 6310235Syasuko.eckert@amd.com Keyword Arguments: 6410235Syasuko.eckert@amd.com mem_mode -- String describing the memory mode (timing or atomic) 65 cpu_class -- CPU class to use 66 num_cpus -- Number of CPUs to instantiate 67 checker -- Set to True to add checker CPUs 68 """ 69 self.mem_mode = mem_mode 70 self.cpu_class = cpu_class 71 self.num_cpus = num_cpus 72 self.checker = checker 73 74 def create_cpus(self): 75 """Return a list of CPU objects to add to a system.""" 76 cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 77 for i in range(self.num_cpus) ] 78 if self.checker: 79 for c in cpus: 80 c.addCheckerCpu() 81 return cpus 82 83 def create_caches_private(self, cpu): 84 """Add private caches to a CPU. 85 86 Arguments: 87 cpu -- CPU instance to work on. 88 """ 89 cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 90 L1Cache(size='32kB', assoc=4)) 91 92 def create_caches_shared(self, system): 93 """Add shared caches to a system. 94 95 Arguments: 96 system -- System to work on. 97 98 Returns: 99 A bus that CPUs should use to connect to the shared cache. 100 """ 101 system.toL2Bus = CoherentBus(clock='2GHz') 102 system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) 103 system.l2c.cpu_side = system.toL2Bus.master 104 system.l2c.mem_side = system.membus.slave 105 return system.toL2Bus 106 107 def init_cpu(self, system, cpu): 108 """Initialize a CPU. 109 110 Arguments: 111 system -- System to work on. 112 cpu -- CPU to initialize. 113 """ 114 cpu.createInterruptController() 115 116 def init_kvm(self, system): 117 """Do KVM-specific system initialization. 118 119 Arguments: 120 system -- System to work on. 121 """ 122 system.vm = KvmVM() 123 124 def init_system(self, system): 125 """Initialize a system. 126 127 Arguments: 128 system -- System to initialize. 129 """ 130 system.cpu = self.create_cpus() 131 132 if _have_kvm_support and \ 133 any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 134 self.init_kvm(system) 135 136 sha_bus = self.create_caches_shared(system) 137 for cpu in system.cpu: 138 if not cpu.switched_out: 139 self.create_caches_private(cpu) 140 self.init_cpu(system, cpu) 141 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 142 system.membus) 143 else: 144 self.init_cpu(system, cpu) 145 146 @abstractmethod 147 def create_system(self): 148 """Create an return an initialized system.""" 149 pass 150 151 @abstractmethod 152 def create_root(self): 153 """Create and return a simulation root using the system 154 defined by this class.""" 155 pass 156 157class BaseFSSystem(BaseSystem): 158 """Basic full system builder.""" 159 160 def __init__(self, **kwargs): 161 BaseSystem.__init__(self, **kwargs) 162 163 def init_system(self, system): 164 BaseSystem.init_system(self, system) 165 166 #create the iocache 167 system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges) 168 system.iocache.cpu_side = system.iobus.master 169 system.iocache.mem_side = system.membus.slave 170 171 def create_root(self): 172 system = self.create_system() 173 m5.ticks.setGlobalFrequency('1THz') 174 return Root(full_system=True, system=system) 175 176class BaseFSSystemUniprocessor(BaseFSSystem): 177 """Basic full system builder for uniprocessor systems. 178 179 Note: This class is only really needed to provide backwards 180 compatibility in existing test cases. 181 """ 182 183 def __init__(self, **kwargs): 184 BaseFSSystem.__init__(self, **kwargs) 185 186 def create_caches_private(self, cpu): 187 cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 188 L1Cache(size='32kB', assoc=4), 189 L2Cache(size='4MB', assoc=8)) 190 191 def create_caches_shared(self, system): 192 return None 193 194class BaseFSSwitcheroo(BaseFSSystem): 195 """Uniprocessor system prepared for CPU switching""" 196 197 def __init__(self, cpu_classes, **kwargs): 198 BaseFSSystem.__init__(self, **kwargs) 199 self.cpu_classes = tuple(cpu_classes) 200 201 def create_cpus(self): 202 cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) 203 for cclass in self.cpu_classes ] 204 cpus[0].switched_out = False 205 return cpus 206