base_config.py revision 9380 
1# Copyright (c) 2012 ARM Limited
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35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46class BaseSystem(object):
47    """Base system builder.
48
49    This class provides some basic functionality for creating an ARM
50    system with the usual peripherals (caches, GIC, etc.). It allows
51    customization by defining separate methods for different parts of
52    the initialization process.
53    """
54
55    __metaclass__ = ABCMeta
56
57    def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
58                 num_cpus=1, checker=False):
59        """Initialize a simple ARM system.
60
61        Keyword Arguments:
62          mem_mode -- String describing the memory mode (timing or atomic)
63          cpu_class -- CPU class to use
64          num_cpus -- Number of CPUs to instantiate
65          checker -- Set to True to add checker CPUs
66        """
67        self.mem_mode = mem_mode
68        self.cpu_class = cpu_class
69        self.num_cpus = num_cpus
70        self.checker = checker
71
72    def create_cpus(self):
73        """Return a list of CPU objects to add to a system."""
74        cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
75                 for i in range(self.num_cpus) ]
76        if self.checker:
77            for c in cpus:
78                c.addCheckerCpu()
79        return cpus
80
81    def create_caches_private(self, cpu):
82        """Add private caches to a CPU.
83
84        Arguments:
85          cpu -- CPU instance to work on.
86        """
87        cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
88                                    L1Cache(size='32kB', assoc=4))
89
90    def create_caches_shared(self, system):
91        """Add shared caches to a system.
92
93        Arguments:
94          system -- System to work on.
95
96        Returns:
97          A bus that CPUs should use to connect to the shared cache.
98        """
99        system.toL2Bus = CoherentBus(clock='2GHz')
100        system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
101        system.l2c.cpu_side = system.toL2Bus.master
102        system.l2c.mem_side = system.membus.slave
103        return system.toL2Bus
104
105    def init_cpu(self, system, cpu):
106        """Initialize a CPU.
107
108        Arguments:
109          system -- System to work on.
110          cpu -- CPU to initialize.
111        """
112        cpu.createInterruptController()
113
114    def init_system(self, system):
115        """Initialize a system.
116
117        Arguments:
118          system -- System to initialize.
119        """
120        system.cpu = self.create_cpus()
121
122        sha_bus = self.create_caches_shared(system)
123        for cpu in system.cpu:
124            self.create_caches_private(cpu)
125            self.init_cpu(system, cpu)
126            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
127                                system.membus)
128
129    @abstractmethod
130    def create_system(self):
131        """Create an return an initialized system."""
132        pass
133
134    @abstractmethod
135    def create_root(self):
136        """Create and return a simulation root using the system
137        defined by this class."""
138        pass
139
140class BaseFSSystem(BaseSystem):
141    """Basic full system builder."""
142
143    def __init__(self, **kwargs):
144        BaseSystem.__init__(self, **kwargs)
145
146    def init_system(self, system):
147        BaseSystem.init_system(self, system)
148
149        #create the iocache
150        system.iocache = IOCache(clock='1GHz', addr_ranges=[system.physmem.range])
151        system.iocache.cpu_side = system.iobus.master
152        system.iocache.mem_side = system.membus.slave
153
154    def create_root(self):
155        system = self.create_system()
156        m5.ticks.setGlobalFrequency('1THz')
157        return Root(full_system=True, system=system)
158
159class BaseFSSystemUniprocessor(BaseFSSystem):
160    """Basic full system builder for uniprocessor systems.
161
162    Note: This class is only really needed to provide backwards
163    compatibility in existing test cases.
164    """
165
166    def __init__(self, **kwargs):
167        BaseFSSystem.__init__(self, **kwargs)
168
169    def create_caches_private(self, cpu):
170        cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
171                                      L1Cache(size='32kB', assoc=4),
172                                      L2Cache(size='4MB', assoc=8))
173
174    def create_caches_shared(self, system):
175        return None
176