base_config.py revision 10512 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/common')
44import FSConfig
45from Caches import *
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50    """Base system builder.
51
52    This class provides some basic functionality for creating an ARM
53    system with the usual peripherals (caches, GIC, etc.). It allows
54    customization by defining separate methods for different parts of
55    the initialization process.
56    """
57
58    __metaclass__ = ABCMeta
59
60    def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61                 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False,
62                 mem_size=None):
63        """Initialize a simple base system.
64
65        Keyword Arguments:
66          mem_mode -- String describing the memory mode (timing or atomic)
67          mem_class -- Memory controller class to use
68          cpu_class -- CPU class to use
69          num_cpus -- Number of CPUs to instantiate
70          checker -- Set to True to add checker CPUs
71          mem_size -- Override the default memory size
72        """
73        self.mem_mode = mem_mode
74        self.mem_class = mem_class
75        self.cpu_class = cpu_class
76        self.num_cpus = num_cpus
77        self.checker = checker
78
79    def create_cpus(self, cpu_clk_domain):
80        """Return a list of CPU objects to add to a system."""
81        cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
82                                cpu_id=i)
83                 for i in range(self.num_cpus) ]
84        if self.checker:
85            for c in cpus:
86                c.addCheckerCpu()
87        return cpus
88
89    def create_caches_private(self, cpu):
90        """Add private caches to a CPU.
91
92        Arguments:
93          cpu -- CPU instance to work on.
94        """
95        cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
96                                    L1Cache(size='32kB', assoc=4))
97
98    def create_caches_shared(self, system):
99        """Add shared caches to a system.
100
101        Arguments:
102          system -- System to work on.
103
104        Returns:
105          A bus that CPUs should use to connect to the shared cache.
106        """
107        system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain)
108        system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
109                             size='4MB', assoc=8)
110        system.l2c.cpu_side = system.toL2Bus.master
111        system.l2c.mem_side = system.membus.slave
112        return system.toL2Bus
113
114    def init_cpu(self, system, cpu, sha_bus):
115        """Initialize a CPU.
116
117        Arguments:
118          system -- System to work on.
119          cpu -- CPU to initialize.
120        """
121        if not cpu.switched_out:
122            self.create_caches_private(cpu)
123            cpu.createInterruptController()
124            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
125                                system.membus)
126
127    def init_kvm(self, system):
128        """Do KVM-specific system initialization.
129
130        Arguments:
131          system -- System to work on.
132        """
133        system.vm = KvmVM()
134
135    def init_system(self, system):
136        """Initialize a system.
137
138        Arguments:
139          system -- System to initialize.
140        """
141        self.create_clk_src(system)
142        system.cpu = self.create_cpus(system.cpu_clk_domain)
143
144        if _have_kvm_support and \
145                any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
146            self.init_kvm(system)
147
148        sha_bus = self.create_caches_shared(system)
149        for cpu in system.cpu:
150            self.init_cpu(system, cpu, sha_bus)
151
152    def create_clk_src(self,system):
153        # Create system clock domain. This provides clock value to every
154        # clocked object that lies beneath it unless explicitly overwritten
155        # by a different clock domain.
156        system.voltage_domain = VoltageDomain()
157        system.clk_domain = SrcClockDomain(clock = '1GHz',
158                                           voltage_domain =
159                                           system.voltage_domain)
160
161        # Create a seperate clock domain for components that should
162        # run at CPUs frequency
163        system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
164                                               voltage_domain =
165                                               system.voltage_domain)
166
167    @abstractmethod
168    def create_system(self):
169        """Create an return an initialized system."""
170        pass
171
172    @abstractmethod
173    def create_root(self):
174        """Create and return a simulation root using the system
175        defined by this class."""
176        pass
177
178class BaseSESystem(BaseSystem):
179    """Basic syscall-emulation builder."""
180
181    def __init__(self, **kwargs):
182        BaseSystem.__init__(self, **kwargs)
183
184    def init_system(self, system):
185        BaseSystem.init_system(self, system)
186
187    def create_system(self):
188        system = System(physmem = self.mem_class(),
189                        membus = CoherentXBar(),
190                        mem_mode = self.mem_mode)
191        system.system_port = system.membus.slave
192        system.physmem.port = system.membus.master
193        self.init_system(system)
194        return system
195
196    def create_root(self):
197        system = self.create_system()
198        m5.ticks.setGlobalFrequency('1THz')
199        return Root(full_system=False, system=system)
200
201class BaseSESystemUniprocessor(BaseSESystem):
202    """Basic syscall-emulation builder for uniprocessor systems.
203
204    Note: This class is only really needed to provide backwards
205    compatibility in existing test cases.
206    """
207
208    def __init__(self, **kwargs):
209        BaseSESystem.__init__(self, **kwargs)
210
211    def create_caches_private(self, cpu):
212        # The atomic SE configurations do not use caches
213        if self.mem_mode == "timing":
214            # @todo We might want to revisit these rather enthusiastic L1 sizes
215            cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
216                                          L1Cache(size='256kB'),
217                                          L2Cache(size='2MB'))
218
219    def create_caches_shared(self, system):
220        return None
221
222class BaseFSSystem(BaseSystem):
223    """Basic full system builder."""
224
225    def __init__(self, **kwargs):
226        BaseSystem.__init__(self, **kwargs)
227
228    def init_system(self, system):
229        BaseSystem.init_system(self, system)
230
231        # create the memory controllers and connect them, stick with
232        # the physmem name to avoid bumping all the reference stats
233        system.physmem = [self.mem_class(range = r)
234                          for r in system.mem_ranges]
235        for i in xrange(len(system.physmem)):
236            system.physmem[i].port = system.membus.master
237
238        # create the iocache, which by default runs at the system clock
239        system.iocache = IOCache(addr_ranges=system.mem_ranges)
240        system.iocache.cpu_side = system.iobus.master
241        system.iocache.mem_side = system.membus.slave
242
243    def create_root(self):
244        system = self.create_system()
245        m5.ticks.setGlobalFrequency('1THz')
246        return Root(full_system=True, system=system)
247
248class BaseFSSystemUniprocessor(BaseFSSystem):
249    """Basic full system builder for uniprocessor systems.
250
251    Note: This class is only really needed to provide backwards
252    compatibility in existing test cases.
253    """
254
255    def __init__(self, **kwargs):
256        BaseFSSystem.__init__(self, **kwargs)
257
258    def create_caches_private(self, cpu):
259        cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
260                                      L1Cache(size='32kB', assoc=4),
261                                      L2Cache(size='4MB', assoc=8))
262
263    def create_caches_shared(self, system):
264        return None
265
266class BaseFSSwitcheroo(BaseFSSystem):
267    """Uniprocessor system prepared for CPU switching"""
268
269    def __init__(self, cpu_classes, **kwargs):
270        BaseFSSystem.__init__(self, **kwargs)
271        self.cpu_classes = tuple(cpu_classes)
272
273    def create_cpus(self, cpu_clk_domain):
274        cpus = [ cclass(clk_domain = cpu_clk_domain,
275                        cpu_id=0,
276                        switched_out=True)
277                 for cclass in self.cpu_classes ]
278        cpus[0].switched_out = False
279        return cpus
280