base_config.py revision 9792
19792Sandreas.hansson@arm.com# Copyright (c) 2012-2013 ARM Limited 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59380SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69380SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79380SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89380SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99380SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109380SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119380SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129380SAndreas.Sandberg@ARM.com# 139380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239380SAndreas.Sandberg@ARM.com# 249380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359380SAndreas.Sandberg@ARM.com# 369380SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379792Sandreas.hansson@arm.com# Andreas Hansson 389380SAndreas.Sandberg@ARM.com 399380SAndreas.Sandberg@ARM.comfrom abc import ABCMeta, abstractmethod 409380SAndreas.Sandberg@ARM.comimport m5 419380SAndreas.Sandberg@ARM.comfrom m5.objects import * 429380SAndreas.Sandberg@ARM.comfrom m5.proxy import * 439380SAndreas.Sandberg@ARM.comm5.util.addToPath('../configs/common') 449380SAndreas.Sandberg@ARM.comimport FSConfig 459380SAndreas.Sandberg@ARM.comfrom Caches import * 469380SAndreas.Sandberg@ARM.com 479654SAndreas.Sandberg@ARM.com_have_kvm_support = 'BaseKvmCPU' in globals() 489654SAndreas.Sandberg@ARM.com 499380SAndreas.Sandberg@ARM.comclass BaseSystem(object): 509380SAndreas.Sandberg@ARM.com """Base system builder. 519380SAndreas.Sandberg@ARM.com 529380SAndreas.Sandberg@ARM.com This class provides some basic functionality for creating an ARM 539380SAndreas.Sandberg@ARM.com system with the usual peripherals (caches, GIC, etc.). It allows 549380SAndreas.Sandberg@ARM.com customization by defining separate methods for different parts of 559380SAndreas.Sandberg@ARM.com the initialization process. 569380SAndreas.Sandberg@ARM.com """ 579380SAndreas.Sandberg@ARM.com 589380SAndreas.Sandberg@ARM.com __metaclass__ = ABCMeta 599380SAndreas.Sandberg@ARM.com 609792Sandreas.hansson@arm.com def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 619792Sandreas.hansson@arm.com cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): 629792Sandreas.hansson@arm.com """Initialize a simple base system. 639380SAndreas.Sandberg@ARM.com 649380SAndreas.Sandberg@ARM.com Keyword Arguments: 659380SAndreas.Sandberg@ARM.com mem_mode -- String describing the memory mode (timing or atomic) 669792Sandreas.hansson@arm.com mem_class -- Memory controller class to use 679380SAndreas.Sandberg@ARM.com cpu_class -- CPU class to use 689380SAndreas.Sandberg@ARM.com num_cpus -- Number of CPUs to instantiate 699380SAndreas.Sandberg@ARM.com checker -- Set to True to add checker CPUs 709380SAndreas.Sandberg@ARM.com """ 719380SAndreas.Sandberg@ARM.com self.mem_mode = mem_mode 729792Sandreas.hansson@arm.com self.mem_class = mem_class 739380SAndreas.Sandberg@ARM.com self.cpu_class = cpu_class 749380SAndreas.Sandberg@ARM.com self.num_cpus = num_cpus 759380SAndreas.Sandberg@ARM.com self.checker = checker 769380SAndreas.Sandberg@ARM.com 779380SAndreas.Sandberg@ARM.com def create_cpus(self): 789380SAndreas.Sandberg@ARM.com """Return a list of CPU objects to add to a system.""" 799380SAndreas.Sandberg@ARM.com cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 809380SAndreas.Sandberg@ARM.com for i in range(self.num_cpus) ] 819380SAndreas.Sandberg@ARM.com if self.checker: 829380SAndreas.Sandberg@ARM.com for c in cpus: 839380SAndreas.Sandberg@ARM.com c.addCheckerCpu() 849380SAndreas.Sandberg@ARM.com return cpus 859380SAndreas.Sandberg@ARM.com 869380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 879380SAndreas.Sandberg@ARM.com """Add private caches to a CPU. 889380SAndreas.Sandberg@ARM.com 899380SAndreas.Sandberg@ARM.com Arguments: 909380SAndreas.Sandberg@ARM.com cpu -- CPU instance to work on. 919380SAndreas.Sandberg@ARM.com """ 929380SAndreas.Sandberg@ARM.com cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 939380SAndreas.Sandberg@ARM.com L1Cache(size='32kB', assoc=4)) 949380SAndreas.Sandberg@ARM.com 959380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 969380SAndreas.Sandberg@ARM.com """Add shared caches to a system. 979380SAndreas.Sandberg@ARM.com 989380SAndreas.Sandberg@ARM.com Arguments: 999380SAndreas.Sandberg@ARM.com system -- System to work on. 1009380SAndreas.Sandberg@ARM.com 1019380SAndreas.Sandberg@ARM.com Returns: 1029380SAndreas.Sandberg@ARM.com A bus that CPUs should use to connect to the shared cache. 1039380SAndreas.Sandberg@ARM.com """ 1049380SAndreas.Sandberg@ARM.com system.toL2Bus = CoherentBus(clock='2GHz') 1059380SAndreas.Sandberg@ARM.com system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) 1069380SAndreas.Sandberg@ARM.com system.l2c.cpu_side = system.toL2Bus.master 1079380SAndreas.Sandberg@ARM.com system.l2c.mem_side = system.membus.slave 1089380SAndreas.Sandberg@ARM.com return system.toL2Bus 1099380SAndreas.Sandberg@ARM.com 1109674Snilay@cs.wisc.edu def init_cpu(self, system, cpu, sha_bus): 1119380SAndreas.Sandberg@ARM.com """Initialize a CPU. 1129380SAndreas.Sandberg@ARM.com 1139380SAndreas.Sandberg@ARM.com Arguments: 1149380SAndreas.Sandberg@ARM.com system -- System to work on. 1159380SAndreas.Sandberg@ARM.com cpu -- CPU to initialize. 1169380SAndreas.Sandberg@ARM.com """ 1179674Snilay@cs.wisc.edu if not cpu.switched_out: 1189674Snilay@cs.wisc.edu self.create_caches_private(cpu) 1199674Snilay@cs.wisc.edu cpu.createInterruptController() 1209674Snilay@cs.wisc.edu cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 1219674Snilay@cs.wisc.edu system.membus) 1229380SAndreas.Sandberg@ARM.com 1239654SAndreas.Sandberg@ARM.com def init_kvm(self, system): 1249654SAndreas.Sandberg@ARM.com """Do KVM-specific system initialization. 1259654SAndreas.Sandberg@ARM.com 1269654SAndreas.Sandberg@ARM.com Arguments: 1279654SAndreas.Sandberg@ARM.com system -- System to work on. 1289654SAndreas.Sandberg@ARM.com """ 1299654SAndreas.Sandberg@ARM.com system.vm = KvmVM() 1309654SAndreas.Sandberg@ARM.com 1319380SAndreas.Sandberg@ARM.com def init_system(self, system): 1329380SAndreas.Sandberg@ARM.com """Initialize a system. 1339380SAndreas.Sandberg@ARM.com 1349380SAndreas.Sandberg@ARM.com Arguments: 1359380SAndreas.Sandberg@ARM.com system -- System to initialize. 1369380SAndreas.Sandberg@ARM.com """ 1379790Sakash.bagdia@arm.com system.clock = '1GHz' 1389380SAndreas.Sandberg@ARM.com system.cpu = self.create_cpus() 1399380SAndreas.Sandberg@ARM.com 1409654SAndreas.Sandberg@ARM.com if _have_kvm_support and \ 1419654SAndreas.Sandberg@ARM.com any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 1429654SAndreas.Sandberg@ARM.com self.init_kvm(system) 1439654SAndreas.Sandberg@ARM.com 1449380SAndreas.Sandberg@ARM.com sha_bus = self.create_caches_shared(system) 1459380SAndreas.Sandberg@ARM.com for cpu in system.cpu: 1469674Snilay@cs.wisc.edu self.init_cpu(system, cpu, sha_bus) 1479380SAndreas.Sandberg@ARM.com 1489380SAndreas.Sandberg@ARM.com @abstractmethod 1499380SAndreas.Sandberg@ARM.com def create_system(self): 1509380SAndreas.Sandberg@ARM.com """Create an return an initialized system.""" 1519380SAndreas.Sandberg@ARM.com pass 1529380SAndreas.Sandberg@ARM.com 1539380SAndreas.Sandberg@ARM.com @abstractmethod 1549380SAndreas.Sandberg@ARM.com def create_root(self): 1559380SAndreas.Sandberg@ARM.com """Create and return a simulation root using the system 1569380SAndreas.Sandberg@ARM.com defined by this class.""" 1579380SAndreas.Sandberg@ARM.com pass 1589380SAndreas.Sandberg@ARM.com 1599792Sandreas.hansson@arm.comclass BaseSESystem(BaseSystem): 1609792Sandreas.hansson@arm.com """Basic syscall-emulation builder.""" 1619792Sandreas.hansson@arm.com 1629792Sandreas.hansson@arm.com def __init__(self, **kwargs): 1639792Sandreas.hansson@arm.com BaseSystem.__init__(self, **kwargs) 1649792Sandreas.hansson@arm.com 1659792Sandreas.hansson@arm.com def init_system(self, system): 1669792Sandreas.hansson@arm.com BaseSystem.init_system(self, system) 1679792Sandreas.hansson@arm.com 1689792Sandreas.hansson@arm.com def create_system(self): 1699792Sandreas.hansson@arm.com system = System(physmem = self.mem_class(), 1709792Sandreas.hansson@arm.com membus = CoherentBus(), 1719792Sandreas.hansson@arm.com mem_mode = self.mem_mode) 1729792Sandreas.hansson@arm.com system.system_port = system.membus.slave 1739792Sandreas.hansson@arm.com system.physmem.port = system.membus.master 1749792Sandreas.hansson@arm.com self.init_system(system) 1759792Sandreas.hansson@arm.com return system 1769792Sandreas.hansson@arm.com 1779792Sandreas.hansson@arm.com def create_root(self): 1789792Sandreas.hansson@arm.com system = self.create_system() 1799792Sandreas.hansson@arm.com m5.ticks.setGlobalFrequency('1THz') 1809792Sandreas.hansson@arm.com return Root(full_system=False, system=system) 1819792Sandreas.hansson@arm.com 1829792Sandreas.hansson@arm.comclass BaseSESystemUniprocessor(BaseSESystem): 1839792Sandreas.hansson@arm.com """Basic syscall-emulation builder for uniprocessor systems. 1849792Sandreas.hansson@arm.com 1859792Sandreas.hansson@arm.com Note: This class is only really needed to provide backwards 1869792Sandreas.hansson@arm.com compatibility in existing test cases. 1879792Sandreas.hansson@arm.com """ 1889792Sandreas.hansson@arm.com 1899792Sandreas.hansson@arm.com def __init__(self, **kwargs): 1909792Sandreas.hansson@arm.com BaseSESystem.__init__(self, **kwargs) 1919792Sandreas.hansson@arm.com 1929792Sandreas.hansson@arm.com def create_caches_private(self, cpu): 1939792Sandreas.hansson@arm.com # The atomic SE configurations do not use caches 1949792Sandreas.hansson@arm.com if self.mem_mode == "timing": 1959792Sandreas.hansson@arm.com # @todo We might want to revisit these rather enthusiastic L1 sizes 1969792Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), 1979792Sandreas.hansson@arm.com L1Cache(size='256kB'), 1989792Sandreas.hansson@arm.com L2Cache(size='2MB')) 1999792Sandreas.hansson@arm.com 2009792Sandreas.hansson@arm.com def create_caches_shared(self, system): 2019792Sandreas.hansson@arm.com return None 2029792Sandreas.hansson@arm.com 2039380SAndreas.Sandberg@ARM.comclass BaseFSSystem(BaseSystem): 2049380SAndreas.Sandberg@ARM.com """Basic full system builder.""" 2059380SAndreas.Sandberg@ARM.com 2069380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 2079380SAndreas.Sandberg@ARM.com BaseSystem.__init__(self, **kwargs) 2089380SAndreas.Sandberg@ARM.com 2099380SAndreas.Sandberg@ARM.com def init_system(self, system): 2109380SAndreas.Sandberg@ARM.com BaseSystem.init_system(self, system) 2119380SAndreas.Sandberg@ARM.com 2129788Sakash.bagdia@arm.com # create the iocache, which by default runs at the system clock 2139788Sakash.bagdia@arm.com system.iocache = IOCache(addr_ranges=system.mem_ranges) 2149380SAndreas.Sandberg@ARM.com system.iocache.cpu_side = system.iobus.master 2159380SAndreas.Sandberg@ARM.com system.iocache.mem_side = system.membus.slave 2169380SAndreas.Sandberg@ARM.com 2179380SAndreas.Sandberg@ARM.com def create_root(self): 2189380SAndreas.Sandberg@ARM.com system = self.create_system() 2199380SAndreas.Sandberg@ARM.com m5.ticks.setGlobalFrequency('1THz') 2209380SAndreas.Sandberg@ARM.com return Root(full_system=True, system=system) 2219380SAndreas.Sandberg@ARM.com 2229380SAndreas.Sandberg@ARM.comclass BaseFSSystemUniprocessor(BaseFSSystem): 2239380SAndreas.Sandberg@ARM.com """Basic full system builder for uniprocessor systems. 2249380SAndreas.Sandberg@ARM.com 2259380SAndreas.Sandberg@ARM.com Note: This class is only really needed to provide backwards 2269380SAndreas.Sandberg@ARM.com compatibility in existing test cases. 2279380SAndreas.Sandberg@ARM.com """ 2289380SAndreas.Sandberg@ARM.com 2299380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 2309380SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 2319380SAndreas.Sandberg@ARM.com 2329380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 2339380SAndreas.Sandberg@ARM.com cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 2349380SAndreas.Sandberg@ARM.com L1Cache(size='32kB', assoc=4), 2359380SAndreas.Sandberg@ARM.com L2Cache(size='4MB', assoc=8)) 2369380SAndreas.Sandberg@ARM.com 2379380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 2389380SAndreas.Sandberg@ARM.com return None 2399447SAndreas.Sandberg@ARM.com 2409447SAndreas.Sandberg@ARM.comclass BaseFSSwitcheroo(BaseFSSystem): 2419447SAndreas.Sandberg@ARM.com """Uniprocessor system prepared for CPU switching""" 2429447SAndreas.Sandberg@ARM.com 2439447SAndreas.Sandberg@ARM.com def __init__(self, cpu_classes, **kwargs): 2449447SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 2459447SAndreas.Sandberg@ARM.com self.cpu_classes = tuple(cpu_classes) 2469447SAndreas.Sandberg@ARM.com 2479447SAndreas.Sandberg@ARM.com def create_cpus(self): 2489447SAndreas.Sandberg@ARM.com cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) 2499447SAndreas.Sandberg@ARM.com for cclass in self.cpu_classes ] 2509447SAndreas.Sandberg@ARM.com cpus[0].switched_out = False 2519447SAndreas.Sandberg@ARM.com return cpus 252