base_config.py revision 9380
19380SAndreas.Sandberg@ARM.com# Copyright (c) 2012 ARM Limited 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59380SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69380SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79380SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89380SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99380SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109380SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119380SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129380SAndreas.Sandberg@ARM.com# 139380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239380SAndreas.Sandberg@ARM.com# 249380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359380SAndreas.Sandberg@ARM.com# 369380SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379380SAndreas.Sandberg@ARM.com 389380SAndreas.Sandberg@ARM.comfrom abc import ABCMeta, abstractmethod 399380SAndreas.Sandberg@ARM.comimport m5 409380SAndreas.Sandberg@ARM.comfrom m5.objects import * 419380SAndreas.Sandberg@ARM.comfrom m5.proxy import * 429380SAndreas.Sandberg@ARM.comm5.util.addToPath('../configs/common') 439380SAndreas.Sandberg@ARM.comimport FSConfig 449380SAndreas.Sandberg@ARM.comfrom Caches import * 459380SAndreas.Sandberg@ARM.com 469380SAndreas.Sandberg@ARM.comclass BaseSystem(object): 479380SAndreas.Sandberg@ARM.com """Base system builder. 489380SAndreas.Sandberg@ARM.com 499380SAndreas.Sandberg@ARM.com This class provides some basic functionality for creating an ARM 509380SAndreas.Sandberg@ARM.com system with the usual peripherals (caches, GIC, etc.). It allows 519380SAndreas.Sandberg@ARM.com customization by defining separate methods for different parts of 529380SAndreas.Sandberg@ARM.com the initialization process. 539380SAndreas.Sandberg@ARM.com """ 549380SAndreas.Sandberg@ARM.com 559380SAndreas.Sandberg@ARM.com __metaclass__ = ABCMeta 569380SAndreas.Sandberg@ARM.com 579380SAndreas.Sandberg@ARM.com def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, 589380SAndreas.Sandberg@ARM.com num_cpus=1, checker=False): 599380SAndreas.Sandberg@ARM.com """Initialize a simple ARM system. 609380SAndreas.Sandberg@ARM.com 619380SAndreas.Sandberg@ARM.com Keyword Arguments: 629380SAndreas.Sandberg@ARM.com mem_mode -- String describing the memory mode (timing or atomic) 639380SAndreas.Sandberg@ARM.com cpu_class -- CPU class to use 649380SAndreas.Sandberg@ARM.com num_cpus -- Number of CPUs to instantiate 659380SAndreas.Sandberg@ARM.com checker -- Set to True to add checker CPUs 669380SAndreas.Sandberg@ARM.com """ 679380SAndreas.Sandberg@ARM.com self.mem_mode = mem_mode 689380SAndreas.Sandberg@ARM.com self.cpu_class = cpu_class 699380SAndreas.Sandberg@ARM.com self.num_cpus = num_cpus 709380SAndreas.Sandberg@ARM.com self.checker = checker 719380SAndreas.Sandberg@ARM.com 729380SAndreas.Sandberg@ARM.com def create_cpus(self): 739380SAndreas.Sandberg@ARM.com """Return a list of CPU objects to add to a system.""" 749380SAndreas.Sandberg@ARM.com cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') 759380SAndreas.Sandberg@ARM.com for i in range(self.num_cpus) ] 769380SAndreas.Sandberg@ARM.com if self.checker: 779380SAndreas.Sandberg@ARM.com for c in cpus: 789380SAndreas.Sandberg@ARM.com c.addCheckerCpu() 799380SAndreas.Sandberg@ARM.com return cpus 809380SAndreas.Sandberg@ARM.com 819380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 829380SAndreas.Sandberg@ARM.com """Add private caches to a CPU. 839380SAndreas.Sandberg@ARM.com 849380SAndreas.Sandberg@ARM.com Arguments: 859380SAndreas.Sandberg@ARM.com cpu -- CPU instance to work on. 869380SAndreas.Sandberg@ARM.com """ 879380SAndreas.Sandberg@ARM.com cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 889380SAndreas.Sandberg@ARM.com L1Cache(size='32kB', assoc=4)) 899380SAndreas.Sandberg@ARM.com 909380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 919380SAndreas.Sandberg@ARM.com """Add shared caches to a system. 929380SAndreas.Sandberg@ARM.com 939380SAndreas.Sandberg@ARM.com Arguments: 949380SAndreas.Sandberg@ARM.com system -- System to work on. 959380SAndreas.Sandberg@ARM.com 969380SAndreas.Sandberg@ARM.com Returns: 979380SAndreas.Sandberg@ARM.com A bus that CPUs should use to connect to the shared cache. 989380SAndreas.Sandberg@ARM.com """ 999380SAndreas.Sandberg@ARM.com system.toL2Bus = CoherentBus(clock='2GHz') 1009380SAndreas.Sandberg@ARM.com system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) 1019380SAndreas.Sandberg@ARM.com system.l2c.cpu_side = system.toL2Bus.master 1029380SAndreas.Sandberg@ARM.com system.l2c.mem_side = system.membus.slave 1039380SAndreas.Sandberg@ARM.com return system.toL2Bus 1049380SAndreas.Sandberg@ARM.com 1059380SAndreas.Sandberg@ARM.com def init_cpu(self, system, cpu): 1069380SAndreas.Sandberg@ARM.com """Initialize a CPU. 1079380SAndreas.Sandberg@ARM.com 1089380SAndreas.Sandberg@ARM.com Arguments: 1099380SAndreas.Sandberg@ARM.com system -- System to work on. 1109380SAndreas.Sandberg@ARM.com cpu -- CPU to initialize. 1119380SAndreas.Sandberg@ARM.com """ 1129380SAndreas.Sandberg@ARM.com cpu.createInterruptController() 1139380SAndreas.Sandberg@ARM.com 1149380SAndreas.Sandberg@ARM.com def init_system(self, system): 1159380SAndreas.Sandberg@ARM.com """Initialize a system. 1169380SAndreas.Sandberg@ARM.com 1179380SAndreas.Sandberg@ARM.com Arguments: 1189380SAndreas.Sandberg@ARM.com system -- System to initialize. 1199380SAndreas.Sandberg@ARM.com """ 1209380SAndreas.Sandberg@ARM.com system.cpu = self.create_cpus() 1219380SAndreas.Sandberg@ARM.com 1229380SAndreas.Sandberg@ARM.com sha_bus = self.create_caches_shared(system) 1239380SAndreas.Sandberg@ARM.com for cpu in system.cpu: 1249380SAndreas.Sandberg@ARM.com self.create_caches_private(cpu) 1259380SAndreas.Sandberg@ARM.com self.init_cpu(system, cpu) 1269380SAndreas.Sandberg@ARM.com cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 1279380SAndreas.Sandberg@ARM.com system.membus) 1289380SAndreas.Sandberg@ARM.com 1299380SAndreas.Sandberg@ARM.com @abstractmethod 1309380SAndreas.Sandberg@ARM.com def create_system(self): 1319380SAndreas.Sandberg@ARM.com """Create an return an initialized system.""" 1329380SAndreas.Sandberg@ARM.com pass 1339380SAndreas.Sandberg@ARM.com 1349380SAndreas.Sandberg@ARM.com @abstractmethod 1359380SAndreas.Sandberg@ARM.com def create_root(self): 1369380SAndreas.Sandberg@ARM.com """Create and return a simulation root using the system 1379380SAndreas.Sandberg@ARM.com defined by this class.""" 1389380SAndreas.Sandberg@ARM.com pass 1399380SAndreas.Sandberg@ARM.com 1409380SAndreas.Sandberg@ARM.comclass BaseFSSystem(BaseSystem): 1419380SAndreas.Sandberg@ARM.com """Basic full system builder.""" 1429380SAndreas.Sandberg@ARM.com 1439380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 1449380SAndreas.Sandberg@ARM.com BaseSystem.__init__(self, **kwargs) 1459380SAndreas.Sandberg@ARM.com 1469380SAndreas.Sandberg@ARM.com def init_system(self, system): 1479380SAndreas.Sandberg@ARM.com BaseSystem.init_system(self, system) 1489380SAndreas.Sandberg@ARM.com 1499380SAndreas.Sandberg@ARM.com #create the iocache 1509380SAndreas.Sandberg@ARM.com system.iocache = IOCache(clock='1GHz', addr_ranges=[system.physmem.range]) 1519380SAndreas.Sandberg@ARM.com system.iocache.cpu_side = system.iobus.master 1529380SAndreas.Sandberg@ARM.com system.iocache.mem_side = system.membus.slave 1539380SAndreas.Sandberg@ARM.com 1549380SAndreas.Sandberg@ARM.com def create_root(self): 1559380SAndreas.Sandberg@ARM.com system = self.create_system() 1569380SAndreas.Sandberg@ARM.com m5.ticks.setGlobalFrequency('1THz') 1579380SAndreas.Sandberg@ARM.com return Root(full_system=True, system=system) 1589380SAndreas.Sandberg@ARM.com 1599380SAndreas.Sandberg@ARM.comclass BaseFSSystemUniprocessor(BaseFSSystem): 1609380SAndreas.Sandberg@ARM.com """Basic full system builder for uniprocessor systems. 1619380SAndreas.Sandberg@ARM.com 1629380SAndreas.Sandberg@ARM.com Note: This class is only really needed to provide backwards 1639380SAndreas.Sandberg@ARM.com compatibility in existing test cases. 1649380SAndreas.Sandberg@ARM.com """ 1659380SAndreas.Sandberg@ARM.com 1669380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 1679380SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 1689380SAndreas.Sandberg@ARM.com 1699380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 1709380SAndreas.Sandberg@ARM.com cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 1719380SAndreas.Sandberg@ARM.com L1Cache(size='32kB', assoc=4), 1729380SAndreas.Sandberg@ARM.com L2Cache(size='4MB', assoc=8)) 1739380SAndreas.Sandberg@ARM.com 1749380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 1759380SAndreas.Sandberg@ARM.com return None 176