base_config.py revision 13718
112726Snikos.nikoleris@arm.com# Copyright (c) 2012-2013, 2017-2018 ARM Limited 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59380SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69380SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79380SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89380SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99380SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109380SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119380SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129380SAndreas.Sandberg@ARM.com# 139380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239380SAndreas.Sandberg@ARM.com# 249380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359380SAndreas.Sandberg@ARM.com# 369380SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379792Sandreas.hansson@arm.com# Andreas Hansson 389380SAndreas.Sandberg@ARM.com 399380SAndreas.Sandberg@ARM.comfrom abc import ABCMeta, abstractmethod 4012070Snikos.nikoleris@arm.comimport optparse 419380SAndreas.Sandberg@ARM.comimport m5 429380SAndreas.Sandberg@ARM.comfrom m5.objects import * 439380SAndreas.Sandberg@ARM.comfrom m5.proxy import * 4411682Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 4511682Sandreas.hansson@arm.comfrom common import FSConfig 4612070Snikos.nikoleris@arm.comfrom common import Options 4711682Sandreas.hansson@arm.comfrom common.Caches import * 4812070Snikos.nikoleris@arm.comfrom ruby import Ruby 499380SAndreas.Sandberg@ARM.com 509654SAndreas.Sandberg@ARM.com_have_kvm_support = 'BaseKvmCPU' in globals() 519654SAndreas.Sandberg@ARM.com 529380SAndreas.Sandberg@ARM.comclass BaseSystem(object): 539380SAndreas.Sandberg@ARM.com """Base system builder. 549380SAndreas.Sandberg@ARM.com 559380SAndreas.Sandberg@ARM.com This class provides some basic functionality for creating an ARM 569380SAndreas.Sandberg@ARM.com system with the usual peripherals (caches, GIC, etc.). It allows 579380SAndreas.Sandberg@ARM.com customization by defining separate methods for different parts of 589380SAndreas.Sandberg@ARM.com the initialization process. 599380SAndreas.Sandberg@ARM.com """ 609380SAndreas.Sandberg@ARM.com 619380SAndreas.Sandberg@ARM.com __metaclass__ = ABCMeta 629380SAndreas.Sandberg@ARM.com 639792Sandreas.hansson@arm.com def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 6411156Sandreas.sandberg@arm.com cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1, 6512070Snikos.nikoleris@arm.com checker=False, mem_size=None, use_ruby=False): 669792Sandreas.hansson@arm.com """Initialize a simple base system. 679380SAndreas.Sandberg@ARM.com 689380SAndreas.Sandberg@ARM.com Keyword Arguments: 699380SAndreas.Sandberg@ARM.com mem_mode -- String describing the memory mode (timing or atomic) 709792Sandreas.hansson@arm.com mem_class -- Memory controller class to use 719380SAndreas.Sandberg@ARM.com cpu_class -- CPU class to use 729380SAndreas.Sandberg@ARM.com num_cpus -- Number of CPUs to instantiate 739380SAndreas.Sandberg@ARM.com checker -- Set to True to add checker CPUs 7410512SAli.Saidi@ARM.com mem_size -- Override the default memory size 7512070Snikos.nikoleris@arm.com use_ruby -- Set to True to use ruby memory 769380SAndreas.Sandberg@ARM.com """ 779380SAndreas.Sandberg@ARM.com self.mem_mode = mem_mode 789792Sandreas.hansson@arm.com self.mem_class = mem_class 799380SAndreas.Sandberg@ARM.com self.cpu_class = cpu_class 809380SAndreas.Sandberg@ARM.com self.num_cpus = num_cpus 8111156Sandreas.sandberg@arm.com self.num_threads = num_threads 829380SAndreas.Sandberg@ARM.com self.checker = checker 8312070Snikos.nikoleris@arm.com self.use_ruby = use_ruby 849380SAndreas.Sandberg@ARM.com 859793Sakash.bagdia@arm.com def create_cpus(self, cpu_clk_domain): 869380SAndreas.Sandberg@ARM.com """Return a list of CPU objects to add to a system.""" 8711156Sandreas.sandberg@arm.com cpus = [ self.cpu_class(clk_domain=cpu_clk_domain, 8811156Sandreas.sandberg@arm.com numThreads=self.num_threads, 899793Sakash.bagdia@arm.com cpu_id=i) 909380SAndreas.Sandberg@ARM.com for i in range(self.num_cpus) ] 919380SAndreas.Sandberg@ARM.com if self.checker: 929380SAndreas.Sandberg@ARM.com for c in cpus: 939380SAndreas.Sandberg@ARM.com c.addCheckerCpu() 949380SAndreas.Sandberg@ARM.com return cpus 959380SAndreas.Sandberg@ARM.com 969380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 979380SAndreas.Sandberg@ARM.com """Add private caches to a CPU. 989380SAndreas.Sandberg@ARM.com 999380SAndreas.Sandberg@ARM.com Arguments: 1009380SAndreas.Sandberg@ARM.com cpu -- CPU instance to work on. 1019380SAndreas.Sandberg@ARM.com """ 10210884Sandreas.hansson@arm.com cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1), 10310884Sandreas.hansson@arm.com L1_DCache(size='32kB', assoc=4)) 1049380SAndreas.Sandberg@ARM.com 1059380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 1069380SAndreas.Sandberg@ARM.com """Add shared caches to a system. 1079380SAndreas.Sandberg@ARM.com 1089380SAndreas.Sandberg@ARM.com Arguments: 1099380SAndreas.Sandberg@ARM.com system -- System to work on. 1109380SAndreas.Sandberg@ARM.com 1119380SAndreas.Sandberg@ARM.com Returns: 1129380SAndreas.Sandberg@ARM.com A bus that CPUs should use to connect to the shared cache. 1139380SAndreas.Sandberg@ARM.com """ 11410720Sandreas.hansson@arm.com system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) 1159793Sakash.bagdia@arm.com system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 1169793Sakash.bagdia@arm.com size='4MB', assoc=8) 1179380SAndreas.Sandberg@ARM.com system.l2c.cpu_side = system.toL2Bus.master 1189380SAndreas.Sandberg@ARM.com system.l2c.mem_side = system.membus.slave 1199380SAndreas.Sandberg@ARM.com return system.toL2Bus 1209380SAndreas.Sandberg@ARM.com 1219674Snilay@cs.wisc.edu def init_cpu(self, system, cpu, sha_bus): 1229380SAndreas.Sandberg@ARM.com """Initialize a CPU. 1239380SAndreas.Sandberg@ARM.com 1249380SAndreas.Sandberg@ARM.com Arguments: 1259380SAndreas.Sandberg@ARM.com system -- System to work on. 1269380SAndreas.Sandberg@ARM.com cpu -- CPU to initialize. 1279380SAndreas.Sandberg@ARM.com """ 1289674Snilay@cs.wisc.edu if not cpu.switched_out: 1299674Snilay@cs.wisc.edu self.create_caches_private(cpu) 1309674Snilay@cs.wisc.edu cpu.createInterruptController() 1319674Snilay@cs.wisc.edu cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 1329674Snilay@cs.wisc.edu system.membus) 1339380SAndreas.Sandberg@ARM.com 1349654SAndreas.Sandberg@ARM.com def init_kvm(self, system): 1359654SAndreas.Sandberg@ARM.com """Do KVM-specific system initialization. 1369654SAndreas.Sandberg@ARM.com 1379654SAndreas.Sandberg@ARM.com Arguments: 1389654SAndreas.Sandberg@ARM.com system -- System to work on. 1399654SAndreas.Sandberg@ARM.com """ 1409654SAndreas.Sandberg@ARM.com system.vm = KvmVM() 1419654SAndreas.Sandberg@ARM.com 1429380SAndreas.Sandberg@ARM.com def init_system(self, system): 1439380SAndreas.Sandberg@ARM.com """Initialize a system. 1449380SAndreas.Sandberg@ARM.com 1459380SAndreas.Sandberg@ARM.com Arguments: 1469380SAndreas.Sandberg@ARM.com system -- System to initialize. 1479380SAndreas.Sandberg@ARM.com """ 1489793Sakash.bagdia@arm.com self.create_clk_src(system) 1499793Sakash.bagdia@arm.com system.cpu = self.create_cpus(system.cpu_clk_domain) 1509380SAndreas.Sandberg@ARM.com 1519654SAndreas.Sandberg@ARM.com if _have_kvm_support and \ 1529654SAndreas.Sandberg@ARM.com any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 1539654SAndreas.Sandberg@ARM.com self.init_kvm(system) 1549654SAndreas.Sandberg@ARM.com 15512070Snikos.nikoleris@arm.com if self.use_ruby: 15612070Snikos.nikoleris@arm.com # Add the ruby specific and protocol specific options 15712070Snikos.nikoleris@arm.com parser = optparse.OptionParser() 15812070Snikos.nikoleris@arm.com Options.addCommonOptions(parser) 15912070Snikos.nikoleris@arm.com Ruby.define_options(parser) 16012070Snikos.nikoleris@arm.com (options, args) = parser.parse_args() 16111604Sandreas.hansson@arm.com 16212070Snikos.nikoleris@arm.com # Set the default cache size and associativity to be very 16312070Snikos.nikoleris@arm.com # small to encourage races between requests and writebacks. 16412070Snikos.nikoleris@arm.com options.l1d_size="32kB" 16512070Snikos.nikoleris@arm.com options.l1i_size="32kB" 16612070Snikos.nikoleris@arm.com options.l2_size="4MB" 16712070Snikos.nikoleris@arm.com options.l1d_assoc=4 16812070Snikos.nikoleris@arm.com options.l1i_assoc=2 16912070Snikos.nikoleris@arm.com options.l2_assoc=8 17012070Snikos.nikoleris@arm.com options.num_cpus = self.num_cpus 17112070Snikos.nikoleris@arm.com options.num_dirs = 2 17212070Snikos.nikoleris@arm.com 17312598Snikos.nikoleris@arm.com bootmem = getattr(system, 'bootmem', None) 17412070Snikos.nikoleris@arm.com Ruby.create_system(options, True, system, system.iobus, 17512598Snikos.nikoleris@arm.com system._dma_ports, bootmem) 17612070Snikos.nikoleris@arm.com 17712070Snikos.nikoleris@arm.com # Create a seperate clock domain for Ruby 17812070Snikos.nikoleris@arm.com system.ruby.clk_domain = SrcClockDomain( 17912070Snikos.nikoleris@arm.com clock = options.ruby_clock, 18012070Snikos.nikoleris@arm.com voltage_domain = system.voltage_domain) 18112070Snikos.nikoleris@arm.com for i, cpu in enumerate(system.cpu): 18212070Snikos.nikoleris@arm.com if not cpu.switched_out: 18312070Snikos.nikoleris@arm.com cpu.createInterruptController() 18412070Snikos.nikoleris@arm.com cpu.connectCachedPorts(system.ruby._cpu_ports[i]) 18512070Snikos.nikoleris@arm.com else: 18612070Snikos.nikoleris@arm.com sha_bus = self.create_caches_shared(system) 18712070Snikos.nikoleris@arm.com for cpu in system.cpu: 18812070Snikos.nikoleris@arm.com self.init_cpu(system, cpu, sha_bus) 18912070Snikos.nikoleris@arm.com 1909380SAndreas.Sandberg@ARM.com 1919793Sakash.bagdia@arm.com def create_clk_src(self,system): 1929793Sakash.bagdia@arm.com # Create system clock domain. This provides clock value to every 1939793Sakash.bagdia@arm.com # clocked object that lies beneath it unless explicitly overwritten 1949793Sakash.bagdia@arm.com # by a different clock domain. 1959827Sakash.bagdia@arm.com system.voltage_domain = VoltageDomain() 1969827Sakash.bagdia@arm.com system.clk_domain = SrcClockDomain(clock = '1GHz', 1979827Sakash.bagdia@arm.com voltage_domain = 1989827Sakash.bagdia@arm.com system.voltage_domain) 1999793Sakash.bagdia@arm.com 2009793Sakash.bagdia@arm.com # Create a seperate clock domain for components that should 2019793Sakash.bagdia@arm.com # run at CPUs frequency 2029827Sakash.bagdia@arm.com system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 2039827Sakash.bagdia@arm.com voltage_domain = 2049827Sakash.bagdia@arm.com system.voltage_domain) 2059793Sakash.bagdia@arm.com 2069380SAndreas.Sandberg@ARM.com @abstractmethod 2079380SAndreas.Sandberg@ARM.com def create_system(self): 2089380SAndreas.Sandberg@ARM.com """Create an return an initialized system.""" 2099380SAndreas.Sandberg@ARM.com pass 2109380SAndreas.Sandberg@ARM.com 2119380SAndreas.Sandberg@ARM.com @abstractmethod 2129380SAndreas.Sandberg@ARM.com def create_root(self): 2139380SAndreas.Sandberg@ARM.com """Create and return a simulation root using the system 2149380SAndreas.Sandberg@ARM.com defined by this class.""" 2159380SAndreas.Sandberg@ARM.com pass 2169380SAndreas.Sandberg@ARM.com 2179792Sandreas.hansson@arm.comclass BaseSESystem(BaseSystem): 2189792Sandreas.hansson@arm.com """Basic syscall-emulation builder.""" 2199792Sandreas.hansson@arm.com 2209792Sandreas.hansson@arm.com def __init__(self, **kwargs): 2219792Sandreas.hansson@arm.com BaseSystem.__init__(self, **kwargs) 2229792Sandreas.hansson@arm.com 2239792Sandreas.hansson@arm.com def init_system(self, system): 2249792Sandreas.hansson@arm.com BaseSystem.init_system(self, system) 2259792Sandreas.hansson@arm.com 2269792Sandreas.hansson@arm.com def create_system(self): 2279792Sandreas.hansson@arm.com system = System(physmem = self.mem_class(), 22810720Sandreas.hansson@arm.com membus = SystemXBar(), 22911156Sandreas.sandberg@arm.com mem_mode = self.mem_mode, 23011156Sandreas.sandberg@arm.com multi_thread = (self.num_threads > 1)) 23112070Snikos.nikoleris@arm.com if not self.use_ruby: 23212070Snikos.nikoleris@arm.com system.system_port = system.membus.slave 2339792Sandreas.hansson@arm.com system.physmem.port = system.membus.master 2349792Sandreas.hansson@arm.com self.init_system(system) 2359792Sandreas.hansson@arm.com return system 2369792Sandreas.hansson@arm.com 2379792Sandreas.hansson@arm.com def create_root(self): 2389792Sandreas.hansson@arm.com system = self.create_system() 2399792Sandreas.hansson@arm.com m5.ticks.setGlobalFrequency('1THz') 2409792Sandreas.hansson@arm.com return Root(full_system=False, system=system) 2419792Sandreas.hansson@arm.com 2429792Sandreas.hansson@arm.comclass BaseSESystemUniprocessor(BaseSESystem): 2439792Sandreas.hansson@arm.com """Basic syscall-emulation builder for uniprocessor systems. 2449792Sandreas.hansson@arm.com 2459792Sandreas.hansson@arm.com Note: This class is only really needed to provide backwards 2469792Sandreas.hansson@arm.com compatibility in existing test cases. 2479792Sandreas.hansson@arm.com """ 2489792Sandreas.hansson@arm.com 2499792Sandreas.hansson@arm.com def __init__(self, **kwargs): 2509792Sandreas.hansson@arm.com BaseSESystem.__init__(self, **kwargs) 2519792Sandreas.hansson@arm.com 2529792Sandreas.hansson@arm.com def create_caches_private(self, cpu): 2539792Sandreas.hansson@arm.com # The atomic SE configurations do not use caches 2549792Sandreas.hansson@arm.com if self.mem_mode == "timing": 2559792Sandreas.hansson@arm.com # @todo We might want to revisit these rather enthusiastic L1 sizes 25610884Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'), 25710884Sandreas.hansson@arm.com L1_DCache(size='256kB'), 2589792Sandreas.hansson@arm.com L2Cache(size='2MB')) 2599792Sandreas.hansson@arm.com 2609792Sandreas.hansson@arm.com def create_caches_shared(self, system): 2619792Sandreas.hansson@arm.com return None 2629792Sandreas.hansson@arm.com 2639380SAndreas.Sandberg@ARM.comclass BaseFSSystem(BaseSystem): 2649380SAndreas.Sandberg@ARM.com """Basic full system builder.""" 2659380SAndreas.Sandberg@ARM.com 2669380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 2679380SAndreas.Sandberg@ARM.com BaseSystem.__init__(self, **kwargs) 2689380SAndreas.Sandberg@ARM.com 2699380SAndreas.Sandberg@ARM.com def init_system(self, system): 2709380SAndreas.Sandberg@ARM.com BaseSystem.init_system(self, system) 2719380SAndreas.Sandberg@ARM.com 27212070Snikos.nikoleris@arm.com if self.use_ruby: 27312070Snikos.nikoleris@arm.com # Connect the ruby io port to the PIO bus, 27412070Snikos.nikoleris@arm.com # assuming that there is just one such port. 27512070Snikos.nikoleris@arm.com system.iobus.master = system.ruby._io_port.slave 27612070Snikos.nikoleris@arm.com else: 27712070Snikos.nikoleris@arm.com # create the memory controllers and connect them, stick with 27812070Snikos.nikoleris@arm.com # the physmem name to avoid bumping all the reference stats 27912070Snikos.nikoleris@arm.com system.physmem = [self.mem_class(range = r) 28012070Snikos.nikoleris@arm.com for r in system.mem_ranges] 28112726Snikos.nikoleris@arm.com system.llc = [NoncoherentCache(addr_ranges = [r], 28212726Snikos.nikoleris@arm.com size = '4kB', 28312726Snikos.nikoleris@arm.com assoc = 2, 28412726Snikos.nikoleris@arm.com mshrs = 128, 28512726Snikos.nikoleris@arm.com tag_latency = 10, 28612726Snikos.nikoleris@arm.com data_latency = 10, 28712726Snikos.nikoleris@arm.com sequential_access = True, 28812726Snikos.nikoleris@arm.com response_latency = 20, 28912726Snikos.nikoleris@arm.com tgts_per_mshr = 8) 29012726Snikos.nikoleris@arm.com for r in system.mem_ranges] 29113718Sandreas.sandberg@arm.com for i in range(len(system.physmem)): 29212726Snikos.nikoleris@arm.com system.physmem[i].port = system.llc[i].mem_side 29312726Snikos.nikoleris@arm.com system.llc[i].cpu_side = system.membus.master 2949826Sandreas.hansson@arm.com 29512070Snikos.nikoleris@arm.com # create the iocache, which by default runs at the system clock 29612070Snikos.nikoleris@arm.com system.iocache = IOCache(addr_ranges=system.mem_ranges) 29712070Snikos.nikoleris@arm.com system.iocache.cpu_side = system.iobus.master 29812070Snikos.nikoleris@arm.com system.iocache.mem_side = system.membus.slave 2999380SAndreas.Sandberg@ARM.com 3009380SAndreas.Sandberg@ARM.com def create_root(self): 3019380SAndreas.Sandberg@ARM.com system = self.create_system() 3029380SAndreas.Sandberg@ARM.com m5.ticks.setGlobalFrequency('1THz') 3039380SAndreas.Sandberg@ARM.com return Root(full_system=True, system=system) 3049380SAndreas.Sandberg@ARM.com 3059380SAndreas.Sandberg@ARM.comclass BaseFSSystemUniprocessor(BaseFSSystem): 3069380SAndreas.Sandberg@ARM.com """Basic full system builder for uniprocessor systems. 3079380SAndreas.Sandberg@ARM.com 3089380SAndreas.Sandberg@ARM.com Note: This class is only really needed to provide backwards 3099380SAndreas.Sandberg@ARM.com compatibility in existing test cases. 3109380SAndreas.Sandberg@ARM.com """ 3119380SAndreas.Sandberg@ARM.com 3129380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 3139380SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 3149380SAndreas.Sandberg@ARM.com 3159380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 31610884Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1), 31710884Sandreas.hansson@arm.com L1_DCache(size='32kB', assoc=4), 3189380SAndreas.Sandberg@ARM.com L2Cache(size='4MB', assoc=8)) 3199380SAndreas.Sandberg@ARM.com 3209380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 3219380SAndreas.Sandberg@ARM.com return None 3229447SAndreas.Sandberg@ARM.com 3239447SAndreas.Sandberg@ARM.comclass BaseFSSwitcheroo(BaseFSSystem): 3249447SAndreas.Sandberg@ARM.com """Uniprocessor system prepared for CPU switching""" 3259447SAndreas.Sandberg@ARM.com 3269447SAndreas.Sandberg@ARM.com def __init__(self, cpu_classes, **kwargs): 3279447SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 3289447SAndreas.Sandberg@ARM.com self.cpu_classes = tuple(cpu_classes) 3299447SAndreas.Sandberg@ARM.com 3309793Sakash.bagdia@arm.com def create_cpus(self, cpu_clk_domain): 3319793Sakash.bagdia@arm.com cpus = [ cclass(clk_domain = cpu_clk_domain, 3329793Sakash.bagdia@arm.com cpu_id=0, 3339793Sakash.bagdia@arm.com switched_out=True) 3349447SAndreas.Sandberg@ARM.com for cclass in self.cpu_classes ] 3359447SAndreas.Sandberg@ARM.com cpus[0].switched_out = False 3369447SAndreas.Sandberg@ARM.com return cpus 337