base_config.py revision 11156
19792Sandreas.hansson@arm.com# Copyright (c) 2012-2013 ARM Limited 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59380SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69380SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79380SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89380SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99380SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109380SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119380SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129380SAndreas.Sandberg@ARM.com# 139380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239380SAndreas.Sandberg@ARM.com# 249380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359380SAndreas.Sandberg@ARM.com# 369380SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379792Sandreas.hansson@arm.com# Andreas Hansson 389380SAndreas.Sandberg@ARM.com 399380SAndreas.Sandberg@ARM.comfrom abc import ABCMeta, abstractmethod 409380SAndreas.Sandberg@ARM.comimport m5 419380SAndreas.Sandberg@ARM.comfrom m5.objects import * 429380SAndreas.Sandberg@ARM.comfrom m5.proxy import * 439380SAndreas.Sandberg@ARM.comm5.util.addToPath('../configs/common') 449380SAndreas.Sandberg@ARM.comimport FSConfig 459380SAndreas.Sandberg@ARM.comfrom Caches import * 469380SAndreas.Sandberg@ARM.com 479654SAndreas.Sandberg@ARM.com_have_kvm_support = 'BaseKvmCPU' in globals() 489654SAndreas.Sandberg@ARM.com 499380SAndreas.Sandberg@ARM.comclass BaseSystem(object): 509380SAndreas.Sandberg@ARM.com """Base system builder. 519380SAndreas.Sandberg@ARM.com 529380SAndreas.Sandberg@ARM.com This class provides some basic functionality for creating an ARM 539380SAndreas.Sandberg@ARM.com system with the usual peripherals (caches, GIC, etc.). It allows 549380SAndreas.Sandberg@ARM.com customization by defining separate methods for different parts of 559380SAndreas.Sandberg@ARM.com the initialization process. 569380SAndreas.Sandberg@ARM.com """ 579380SAndreas.Sandberg@ARM.com 589380SAndreas.Sandberg@ARM.com __metaclass__ = ABCMeta 599380SAndreas.Sandberg@ARM.com 609792Sandreas.hansson@arm.com def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 6111156Sandreas.sandberg@arm.com cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1, 6211156Sandreas.sandberg@arm.com checker=False, 6310512SAli.Saidi@ARM.com mem_size=None): 649792Sandreas.hansson@arm.com """Initialize a simple base system. 659380SAndreas.Sandberg@ARM.com 669380SAndreas.Sandberg@ARM.com Keyword Arguments: 679380SAndreas.Sandberg@ARM.com mem_mode -- String describing the memory mode (timing or atomic) 689792Sandreas.hansson@arm.com mem_class -- Memory controller class to use 699380SAndreas.Sandberg@ARM.com cpu_class -- CPU class to use 709380SAndreas.Sandberg@ARM.com num_cpus -- Number of CPUs to instantiate 719380SAndreas.Sandberg@ARM.com checker -- Set to True to add checker CPUs 7210512SAli.Saidi@ARM.com mem_size -- Override the default memory size 739380SAndreas.Sandberg@ARM.com """ 749380SAndreas.Sandberg@ARM.com self.mem_mode = mem_mode 759792Sandreas.hansson@arm.com self.mem_class = mem_class 769380SAndreas.Sandberg@ARM.com self.cpu_class = cpu_class 779380SAndreas.Sandberg@ARM.com self.num_cpus = num_cpus 7811156Sandreas.sandberg@arm.com self.num_threads = num_threads 799380SAndreas.Sandberg@ARM.com self.checker = checker 809380SAndreas.Sandberg@ARM.com 819793Sakash.bagdia@arm.com def create_cpus(self, cpu_clk_domain): 829380SAndreas.Sandberg@ARM.com """Return a list of CPU objects to add to a system.""" 8311156Sandreas.sandberg@arm.com cpus = [ self.cpu_class(clk_domain=cpu_clk_domain, 8411156Sandreas.sandberg@arm.com numThreads=self.num_threads, 859793Sakash.bagdia@arm.com cpu_id=i) 869380SAndreas.Sandberg@ARM.com for i in range(self.num_cpus) ] 879380SAndreas.Sandberg@ARM.com if self.checker: 889380SAndreas.Sandberg@ARM.com for c in cpus: 899380SAndreas.Sandberg@ARM.com c.addCheckerCpu() 909380SAndreas.Sandberg@ARM.com return cpus 919380SAndreas.Sandberg@ARM.com 929380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 939380SAndreas.Sandberg@ARM.com """Add private caches to a CPU. 949380SAndreas.Sandberg@ARM.com 959380SAndreas.Sandberg@ARM.com Arguments: 969380SAndreas.Sandberg@ARM.com cpu -- CPU instance to work on. 979380SAndreas.Sandberg@ARM.com """ 9810884Sandreas.hansson@arm.com cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1), 9910884Sandreas.hansson@arm.com L1_DCache(size='32kB', assoc=4)) 1009380SAndreas.Sandberg@ARM.com 1019380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 1029380SAndreas.Sandberg@ARM.com """Add shared caches to a system. 1039380SAndreas.Sandberg@ARM.com 1049380SAndreas.Sandberg@ARM.com Arguments: 1059380SAndreas.Sandberg@ARM.com system -- System to work on. 1069380SAndreas.Sandberg@ARM.com 1079380SAndreas.Sandberg@ARM.com Returns: 1089380SAndreas.Sandberg@ARM.com A bus that CPUs should use to connect to the shared cache. 1099380SAndreas.Sandberg@ARM.com """ 11010720Sandreas.hansson@arm.com system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) 1119793Sakash.bagdia@arm.com system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 1129793Sakash.bagdia@arm.com size='4MB', assoc=8) 1139380SAndreas.Sandberg@ARM.com system.l2c.cpu_side = system.toL2Bus.master 1149380SAndreas.Sandberg@ARM.com system.l2c.mem_side = system.membus.slave 1159380SAndreas.Sandberg@ARM.com return system.toL2Bus 1169380SAndreas.Sandberg@ARM.com 1179674Snilay@cs.wisc.edu def init_cpu(self, system, cpu, sha_bus): 1189380SAndreas.Sandberg@ARM.com """Initialize a CPU. 1199380SAndreas.Sandberg@ARM.com 1209380SAndreas.Sandberg@ARM.com Arguments: 1219380SAndreas.Sandberg@ARM.com system -- System to work on. 1229380SAndreas.Sandberg@ARM.com cpu -- CPU to initialize. 1239380SAndreas.Sandberg@ARM.com """ 1249674Snilay@cs.wisc.edu if not cpu.switched_out: 1259674Snilay@cs.wisc.edu self.create_caches_private(cpu) 1269674Snilay@cs.wisc.edu cpu.createInterruptController() 1279674Snilay@cs.wisc.edu cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 1289674Snilay@cs.wisc.edu system.membus) 1299380SAndreas.Sandberg@ARM.com 1309654SAndreas.Sandberg@ARM.com def init_kvm(self, system): 1319654SAndreas.Sandberg@ARM.com """Do KVM-specific system initialization. 1329654SAndreas.Sandberg@ARM.com 1339654SAndreas.Sandberg@ARM.com Arguments: 1349654SAndreas.Sandberg@ARM.com system -- System to work on. 1359654SAndreas.Sandberg@ARM.com """ 1369654SAndreas.Sandberg@ARM.com system.vm = KvmVM() 1379654SAndreas.Sandberg@ARM.com 1389380SAndreas.Sandberg@ARM.com def init_system(self, system): 1399380SAndreas.Sandberg@ARM.com """Initialize a system. 1409380SAndreas.Sandberg@ARM.com 1419380SAndreas.Sandberg@ARM.com Arguments: 1429380SAndreas.Sandberg@ARM.com system -- System to initialize. 1439380SAndreas.Sandberg@ARM.com """ 1449793Sakash.bagdia@arm.com self.create_clk_src(system) 1459793Sakash.bagdia@arm.com system.cpu = self.create_cpus(system.cpu_clk_domain) 1469380SAndreas.Sandberg@ARM.com 1479654SAndreas.Sandberg@ARM.com if _have_kvm_support and \ 1489654SAndreas.Sandberg@ARM.com any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 1499654SAndreas.Sandberg@ARM.com self.init_kvm(system) 1509654SAndreas.Sandberg@ARM.com 1519380SAndreas.Sandberg@ARM.com sha_bus = self.create_caches_shared(system) 1529380SAndreas.Sandberg@ARM.com for cpu in system.cpu: 1539674Snilay@cs.wisc.edu self.init_cpu(system, cpu, sha_bus) 1549380SAndreas.Sandberg@ARM.com 1559793Sakash.bagdia@arm.com def create_clk_src(self,system): 1569793Sakash.bagdia@arm.com # Create system clock domain. This provides clock value to every 1579793Sakash.bagdia@arm.com # clocked object that lies beneath it unless explicitly overwritten 1589793Sakash.bagdia@arm.com # by a different clock domain. 1599827Sakash.bagdia@arm.com system.voltage_domain = VoltageDomain() 1609827Sakash.bagdia@arm.com system.clk_domain = SrcClockDomain(clock = '1GHz', 1619827Sakash.bagdia@arm.com voltage_domain = 1629827Sakash.bagdia@arm.com system.voltage_domain) 1639793Sakash.bagdia@arm.com 1649793Sakash.bagdia@arm.com # Create a seperate clock domain for components that should 1659793Sakash.bagdia@arm.com # run at CPUs frequency 1669827Sakash.bagdia@arm.com system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 1679827Sakash.bagdia@arm.com voltage_domain = 1689827Sakash.bagdia@arm.com system.voltage_domain) 1699793Sakash.bagdia@arm.com 1709380SAndreas.Sandberg@ARM.com @abstractmethod 1719380SAndreas.Sandberg@ARM.com def create_system(self): 1729380SAndreas.Sandberg@ARM.com """Create an return an initialized system.""" 1739380SAndreas.Sandberg@ARM.com pass 1749380SAndreas.Sandberg@ARM.com 1759380SAndreas.Sandberg@ARM.com @abstractmethod 1769380SAndreas.Sandberg@ARM.com def create_root(self): 1779380SAndreas.Sandberg@ARM.com """Create and return a simulation root using the system 1789380SAndreas.Sandberg@ARM.com defined by this class.""" 1799380SAndreas.Sandberg@ARM.com pass 1809380SAndreas.Sandberg@ARM.com 1819792Sandreas.hansson@arm.comclass BaseSESystem(BaseSystem): 1829792Sandreas.hansson@arm.com """Basic syscall-emulation builder.""" 1839792Sandreas.hansson@arm.com 1849792Sandreas.hansson@arm.com def __init__(self, **kwargs): 1859792Sandreas.hansson@arm.com BaseSystem.__init__(self, **kwargs) 1869792Sandreas.hansson@arm.com 1879792Sandreas.hansson@arm.com def init_system(self, system): 1889792Sandreas.hansson@arm.com BaseSystem.init_system(self, system) 1899792Sandreas.hansson@arm.com 1909792Sandreas.hansson@arm.com def create_system(self): 1919792Sandreas.hansson@arm.com system = System(physmem = self.mem_class(), 19210720Sandreas.hansson@arm.com membus = SystemXBar(), 19311156Sandreas.sandberg@arm.com mem_mode = self.mem_mode, 19411156Sandreas.sandberg@arm.com multi_thread = (self.num_threads > 1)) 1959792Sandreas.hansson@arm.com system.system_port = system.membus.slave 1969792Sandreas.hansson@arm.com system.physmem.port = system.membus.master 1979792Sandreas.hansson@arm.com self.init_system(system) 1989792Sandreas.hansson@arm.com return system 1999792Sandreas.hansson@arm.com 2009792Sandreas.hansson@arm.com def create_root(self): 2019792Sandreas.hansson@arm.com system = self.create_system() 2029792Sandreas.hansson@arm.com m5.ticks.setGlobalFrequency('1THz') 2039792Sandreas.hansson@arm.com return Root(full_system=False, system=system) 2049792Sandreas.hansson@arm.com 2059792Sandreas.hansson@arm.comclass BaseSESystemUniprocessor(BaseSESystem): 2069792Sandreas.hansson@arm.com """Basic syscall-emulation builder for uniprocessor systems. 2079792Sandreas.hansson@arm.com 2089792Sandreas.hansson@arm.com Note: This class is only really needed to provide backwards 2099792Sandreas.hansson@arm.com compatibility in existing test cases. 2109792Sandreas.hansson@arm.com """ 2119792Sandreas.hansson@arm.com 2129792Sandreas.hansson@arm.com def __init__(self, **kwargs): 2139792Sandreas.hansson@arm.com BaseSESystem.__init__(self, **kwargs) 2149792Sandreas.hansson@arm.com 2159792Sandreas.hansson@arm.com def create_caches_private(self, cpu): 2169792Sandreas.hansson@arm.com # The atomic SE configurations do not use caches 2179792Sandreas.hansson@arm.com if self.mem_mode == "timing": 2189792Sandreas.hansson@arm.com # @todo We might want to revisit these rather enthusiastic L1 sizes 21910884Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'), 22010884Sandreas.hansson@arm.com L1_DCache(size='256kB'), 2219792Sandreas.hansson@arm.com L2Cache(size='2MB')) 2229792Sandreas.hansson@arm.com 2239792Sandreas.hansson@arm.com def create_caches_shared(self, system): 2249792Sandreas.hansson@arm.com return None 2259792Sandreas.hansson@arm.com 2269380SAndreas.Sandberg@ARM.comclass BaseFSSystem(BaseSystem): 2279380SAndreas.Sandberg@ARM.com """Basic full system builder.""" 2289380SAndreas.Sandberg@ARM.com 2299380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 2309380SAndreas.Sandberg@ARM.com BaseSystem.__init__(self, **kwargs) 2319380SAndreas.Sandberg@ARM.com 2329380SAndreas.Sandberg@ARM.com def init_system(self, system): 2339380SAndreas.Sandberg@ARM.com BaseSystem.init_system(self, system) 2349380SAndreas.Sandberg@ARM.com 2359826Sandreas.hansson@arm.com # create the memory controllers and connect them, stick with 2369826Sandreas.hansson@arm.com # the physmem name to avoid bumping all the reference stats 2379835Sandreas.hansson@arm.com system.physmem = [self.mem_class(range = r) 2389826Sandreas.hansson@arm.com for r in system.mem_ranges] 2399826Sandreas.hansson@arm.com for i in xrange(len(system.physmem)): 2409826Sandreas.hansson@arm.com system.physmem[i].port = system.membus.master 2419826Sandreas.hansson@arm.com 2429788Sakash.bagdia@arm.com # create the iocache, which by default runs at the system clock 2439788Sakash.bagdia@arm.com system.iocache = IOCache(addr_ranges=system.mem_ranges) 2449380SAndreas.Sandberg@ARM.com system.iocache.cpu_side = system.iobus.master 2459380SAndreas.Sandberg@ARM.com system.iocache.mem_side = system.membus.slave 2469380SAndreas.Sandberg@ARM.com 2479380SAndreas.Sandberg@ARM.com def create_root(self): 2489380SAndreas.Sandberg@ARM.com system = self.create_system() 2499380SAndreas.Sandberg@ARM.com m5.ticks.setGlobalFrequency('1THz') 2509380SAndreas.Sandberg@ARM.com return Root(full_system=True, system=system) 2519380SAndreas.Sandberg@ARM.com 2529380SAndreas.Sandberg@ARM.comclass BaseFSSystemUniprocessor(BaseFSSystem): 2539380SAndreas.Sandberg@ARM.com """Basic full system builder for uniprocessor systems. 2549380SAndreas.Sandberg@ARM.com 2559380SAndreas.Sandberg@ARM.com Note: This class is only really needed to provide backwards 2569380SAndreas.Sandberg@ARM.com compatibility in existing test cases. 2579380SAndreas.Sandberg@ARM.com """ 2589380SAndreas.Sandberg@ARM.com 2599380SAndreas.Sandberg@ARM.com def __init__(self, **kwargs): 2609380SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 2619380SAndreas.Sandberg@ARM.com 2629380SAndreas.Sandberg@ARM.com def create_caches_private(self, cpu): 26310884Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1), 26410884Sandreas.hansson@arm.com L1_DCache(size='32kB', assoc=4), 2659380SAndreas.Sandberg@ARM.com L2Cache(size='4MB', assoc=8)) 2669380SAndreas.Sandberg@ARM.com 2679380SAndreas.Sandberg@ARM.com def create_caches_shared(self, system): 2689380SAndreas.Sandberg@ARM.com return None 2699447SAndreas.Sandberg@ARM.com 2709447SAndreas.Sandberg@ARM.comclass BaseFSSwitcheroo(BaseFSSystem): 2719447SAndreas.Sandberg@ARM.com """Uniprocessor system prepared for CPU switching""" 2729447SAndreas.Sandberg@ARM.com 2739447SAndreas.Sandberg@ARM.com def __init__(self, cpu_classes, **kwargs): 2749447SAndreas.Sandberg@ARM.com BaseFSSystem.__init__(self, **kwargs) 2759447SAndreas.Sandberg@ARM.com self.cpu_classes = tuple(cpu_classes) 2769447SAndreas.Sandberg@ARM.com 2779793Sakash.bagdia@arm.com def create_cpus(self, cpu_clk_domain): 2789793Sakash.bagdia@arm.com cpus = [ cclass(clk_domain = cpu_clk_domain, 2799793Sakash.bagdia@arm.com cpu_id=0, 2809793Sakash.bagdia@arm.com switched_out=True) 2819447SAndreas.Sandberg@ARM.com for cclass in self.cpu_classes ] 2829447SAndreas.Sandberg@ARM.com cpus[0].switched_out = False 2839447SAndreas.Sandberg@ARM.com return cpus 284