base_config.py revision 10720
111185Serfan.azarkhish@unibo.it# Copyright (c) 2012-2013 ARM Limited 211185Serfan.azarkhish@unibo.it# All rights reserved. 311185Serfan.azarkhish@unibo.it# 411185Serfan.azarkhish@unibo.it# The license below extends only to copyright in the software and shall 511185Serfan.azarkhish@unibo.it# not be construed as granting a license to any other intellectual 611185Serfan.azarkhish@unibo.it# property including but not limited to intellectual property relating 711185Serfan.azarkhish@unibo.it# to a hardware implementation of the functionality of the software 811185Serfan.azarkhish@unibo.it# licensed hereunder. You may use the software subject to the license 911185Serfan.azarkhish@unibo.it# terms below provided that you ensure that this notice is replicated 1011185Serfan.azarkhish@unibo.it# unmodified and in its entirety in all distributions of the software, 1111185Serfan.azarkhish@unibo.it# modified or unmodified, in source code or in binary form. 1211185Serfan.azarkhish@unibo.it# 1311185Serfan.azarkhish@unibo.it# Redistribution and use in source and binary forms, with or without 1411185Serfan.azarkhish@unibo.it# modification, are permitted provided that the following conditions are 1511185Serfan.azarkhish@unibo.it# met: redistributions of source code must retain the above copyright 1611185Serfan.azarkhish@unibo.it# notice, this list of conditions and the following disclaimer; 1711185Serfan.azarkhish@unibo.it# redistributions in binary form must reproduce the above copyright 1811185Serfan.azarkhish@unibo.it# notice, this list of conditions and the following disclaimer in the 1911185Serfan.azarkhish@unibo.it# documentation and/or other materials provided with the distribution; 2011185Serfan.azarkhish@unibo.it# neither the name of the copyright holders nor the names of its 2111185Serfan.azarkhish@unibo.it# contributors may be used to endorse or promote products derived from 2211185Serfan.azarkhish@unibo.it# this software without specific prior written permission. 2311185Serfan.azarkhish@unibo.it# 2411185Serfan.azarkhish@unibo.it# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511185Serfan.azarkhish@unibo.it# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611185Serfan.azarkhish@unibo.it# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711185Serfan.azarkhish@unibo.it# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811185Serfan.azarkhish@unibo.it# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911185Serfan.azarkhish@unibo.it# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011185Serfan.azarkhish@unibo.it# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111185Serfan.azarkhish@unibo.it# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211185Serfan.azarkhish@unibo.it# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311185Serfan.azarkhish@unibo.it# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411185Serfan.azarkhish@unibo.it# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511185Serfan.azarkhish@unibo.it# 3611185Serfan.azarkhish@unibo.it# Authors: Andreas Sandberg 3711185Serfan.azarkhish@unibo.it# Andreas Hansson 3811185Serfan.azarkhish@unibo.it 3911185Serfan.azarkhish@unibo.itfrom abc import ABCMeta, abstractmethod 4011185Serfan.azarkhish@unibo.itimport m5 4111185Serfan.azarkhish@unibo.itfrom m5.objects import * 4211185Serfan.azarkhish@unibo.itfrom m5.proxy import * 4311185Serfan.azarkhish@unibo.itm5.util.addToPath('../configs/common') 4411185Serfan.azarkhish@unibo.itimport FSConfig 4511185Serfan.azarkhish@unibo.itfrom Caches import * 4611185Serfan.azarkhish@unibo.it 4711185Serfan.azarkhish@unibo.it_have_kvm_support = 'BaseKvmCPU' in globals() 4811185Serfan.azarkhish@unibo.it 4911185Serfan.azarkhish@unibo.itclass BaseSystem(object): 5011185Serfan.azarkhish@unibo.it """Base system builder. 5111185Serfan.azarkhish@unibo.it 5211185Serfan.azarkhish@unibo.it This class provides some basic functionality for creating an ARM 5311185Serfan.azarkhish@unibo.it system with the usual peripherals (caches, GIC, etc.). It allows 5411185Serfan.azarkhish@unibo.it customization by defining separate methods for different parts of 5511185Serfan.azarkhish@unibo.it the initialization process. 5611185Serfan.azarkhish@unibo.it """ 5711185Serfan.azarkhish@unibo.it 5811185Serfan.azarkhish@unibo.it __metaclass__ = ABCMeta 5911185Serfan.azarkhish@unibo.it 6011185Serfan.azarkhish@unibo.it def __init__(self, mem_mode='timing', mem_class=SimpleMemory, 6111185Serfan.azarkhish@unibo.it cpu_class=TimingSimpleCPU, num_cpus=1, checker=False, 6211185Serfan.azarkhish@unibo.it mem_size=None): 6311185Serfan.azarkhish@unibo.it """Initialize a simple base system. 6411185Serfan.azarkhish@unibo.it 6511185Serfan.azarkhish@unibo.it Keyword Arguments: 6611185Serfan.azarkhish@unibo.it mem_mode -- String describing the memory mode (timing or atomic) 6711185Serfan.azarkhish@unibo.it mem_class -- Memory controller class to use 6811185Serfan.azarkhish@unibo.it cpu_class -- CPU class to use 6911185Serfan.azarkhish@unibo.it num_cpus -- Number of CPUs to instantiate 7011185Serfan.azarkhish@unibo.it checker -- Set to True to add checker CPUs 7111185Serfan.azarkhish@unibo.it mem_size -- Override the default memory size 7211185Serfan.azarkhish@unibo.it """ 7311185Serfan.azarkhish@unibo.it self.mem_mode = mem_mode 7411185Serfan.azarkhish@unibo.it self.mem_class = mem_class 7511185Serfan.azarkhish@unibo.it self.cpu_class = cpu_class 7611185Serfan.azarkhish@unibo.it self.num_cpus = num_cpus 7711185Serfan.azarkhish@unibo.it self.checker = checker 7811185Serfan.azarkhish@unibo.it 7911185Serfan.azarkhish@unibo.it def create_cpus(self, cpu_clk_domain): 8011185Serfan.azarkhish@unibo.it """Return a list of CPU objects to add to a system.""" 8111185Serfan.azarkhish@unibo.it cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, 8211185Serfan.azarkhish@unibo.it cpu_id=i) 8311185Serfan.azarkhish@unibo.it for i in range(self.num_cpus) ] 8411185Serfan.azarkhish@unibo.it if self.checker: 8511185Serfan.azarkhish@unibo.it for c in cpus: 8611185Serfan.azarkhish@unibo.it c.addCheckerCpu() 8711185Serfan.azarkhish@unibo.it return cpus 8811185Serfan.azarkhish@unibo.it 8911185Serfan.azarkhish@unibo.it def create_caches_private(self, cpu): 9011185Serfan.azarkhish@unibo.it """Add private caches to a CPU. 9111185Serfan.azarkhish@unibo.it 9211185Serfan.azarkhish@unibo.it Arguments: 9311185Serfan.azarkhish@unibo.it cpu -- CPU instance to work on. 9411185Serfan.azarkhish@unibo.it """ 9511185Serfan.azarkhish@unibo.it cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), 9611185Serfan.azarkhish@unibo.it L1Cache(size='32kB', assoc=4)) 9711185Serfan.azarkhish@unibo.it 9811185Serfan.azarkhish@unibo.it def create_caches_shared(self, system): 9911185Serfan.azarkhish@unibo.it """Add shared caches to a system. 10011185Serfan.azarkhish@unibo.it 10111185Serfan.azarkhish@unibo.it Arguments: 10211185Serfan.azarkhish@unibo.it system -- System to work on. 10311185Serfan.azarkhish@unibo.it 10411185Serfan.azarkhish@unibo.it Returns: 10511185Serfan.azarkhish@unibo.it A bus that CPUs should use to connect to the shared cache. 10611185Serfan.azarkhish@unibo.it """ 10711185Serfan.azarkhish@unibo.it system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) 10811185Serfan.azarkhish@unibo.it system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 10911185Serfan.azarkhish@unibo.it size='4MB', assoc=8) 11011185Serfan.azarkhish@unibo.it system.l2c.cpu_side = system.toL2Bus.master 11111185Serfan.azarkhish@unibo.it system.l2c.mem_side = system.membus.slave 11211185Serfan.azarkhish@unibo.it return system.toL2Bus 11311185Serfan.azarkhish@unibo.it 11411185Serfan.azarkhish@unibo.it def init_cpu(self, system, cpu, sha_bus): 11511185Serfan.azarkhish@unibo.it """Initialize a CPU. 11611185Serfan.azarkhish@unibo.it 11711185Serfan.azarkhish@unibo.it Arguments: 11811185Serfan.azarkhish@unibo.it system -- System to work on. 11911185Serfan.azarkhish@unibo.it cpu -- CPU to initialize. 12011185Serfan.azarkhish@unibo.it """ 12111185Serfan.azarkhish@unibo.it if not cpu.switched_out: 12211185Serfan.azarkhish@unibo.it self.create_caches_private(cpu) 12311185Serfan.azarkhish@unibo.it cpu.createInterruptController() 12411185Serfan.azarkhish@unibo.it cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, 12511185Serfan.azarkhish@unibo.it system.membus) 12611185Serfan.azarkhish@unibo.it 12711185Serfan.azarkhish@unibo.it def init_kvm(self, system): 12811185Serfan.azarkhish@unibo.it """Do KVM-specific system initialization. 12911185Serfan.azarkhish@unibo.it 13011185Serfan.azarkhish@unibo.it Arguments: 13111185Serfan.azarkhish@unibo.it system -- System to work on. 13211185Serfan.azarkhish@unibo.it """ 13311185Serfan.azarkhish@unibo.it system.vm = KvmVM() 13411185Serfan.azarkhish@unibo.it 13511185Serfan.azarkhish@unibo.it def init_system(self, system): 13611185Serfan.azarkhish@unibo.it """Initialize a system. 13711185Serfan.azarkhish@unibo.it 13811185Serfan.azarkhish@unibo.it Arguments: 13911185Serfan.azarkhish@unibo.it system -- System to initialize. 14011185Serfan.azarkhish@unibo.it """ 14111185Serfan.azarkhish@unibo.it self.create_clk_src(system) 14211185Serfan.azarkhish@unibo.it system.cpu = self.create_cpus(system.cpu_clk_domain) 14311185Serfan.azarkhish@unibo.it 14411185Serfan.azarkhish@unibo.it if _have_kvm_support and \ 14511185Serfan.azarkhish@unibo.it any([isinstance(c, BaseKvmCPU) for c in system.cpu]): 14611185Serfan.azarkhish@unibo.it self.init_kvm(system) 14711185Serfan.azarkhish@unibo.it 14811185Serfan.azarkhish@unibo.it sha_bus = self.create_caches_shared(system) 14911185Serfan.azarkhish@unibo.it for cpu in system.cpu: 15011185Serfan.azarkhish@unibo.it self.init_cpu(system, cpu, sha_bus) 15111185Serfan.azarkhish@unibo.it 15211185Serfan.azarkhish@unibo.it def create_clk_src(self,system): 15311185Serfan.azarkhish@unibo.it # Create system clock domain. This provides clock value to every 15411185Serfan.azarkhish@unibo.it # clocked object that lies beneath it unless explicitly overwritten 15511185Serfan.azarkhish@unibo.it # by a different clock domain. 15611185Serfan.azarkhish@unibo.it system.voltage_domain = VoltageDomain() 15711185Serfan.azarkhish@unibo.it system.clk_domain = SrcClockDomain(clock = '1GHz', 15811185Serfan.azarkhish@unibo.it voltage_domain = 15911185Serfan.azarkhish@unibo.it system.voltage_domain) 16011185Serfan.azarkhish@unibo.it 16111185Serfan.azarkhish@unibo.it # Create a seperate clock domain for components that should 16211185Serfan.azarkhish@unibo.it # run at CPUs frequency 16311185Serfan.azarkhish@unibo.it system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 16411185Serfan.azarkhish@unibo.it voltage_domain = 16511185Serfan.azarkhish@unibo.it system.voltage_domain) 16611185Serfan.azarkhish@unibo.it 16711185Serfan.azarkhish@unibo.it @abstractmethod 16811185Serfan.azarkhish@unibo.it def create_system(self): 16911185Serfan.azarkhish@unibo.it """Create an return an initialized system.""" 17011185Serfan.azarkhish@unibo.it pass 17111185Serfan.azarkhish@unibo.it 17211185Serfan.azarkhish@unibo.it @abstractmethod 17311185Serfan.azarkhish@unibo.it def create_root(self): 17411185Serfan.azarkhish@unibo.it """Create and return a simulation root using the system 17511185Serfan.azarkhish@unibo.it defined by this class.""" 17611185Serfan.azarkhish@unibo.it pass 17711185Serfan.azarkhish@unibo.it 17811185Serfan.azarkhish@unibo.itclass BaseSESystem(BaseSystem): 17911185Serfan.azarkhish@unibo.it """Basic syscall-emulation builder.""" 18011185Serfan.azarkhish@unibo.it 18111185Serfan.azarkhish@unibo.it def __init__(self, **kwargs): 18211185Serfan.azarkhish@unibo.it BaseSystem.__init__(self, **kwargs) 18311185Serfan.azarkhish@unibo.it 18411185Serfan.azarkhish@unibo.it def init_system(self, system): 18511185Serfan.azarkhish@unibo.it BaseSystem.init_system(self, system) 18611185Serfan.azarkhish@unibo.it 18711185Serfan.azarkhish@unibo.it def create_system(self): 18811284Sandreas.hansson@arm.com system = System(physmem = self.mem_class(), 18911185Serfan.azarkhish@unibo.it membus = SystemXBar(), 19011185Serfan.azarkhish@unibo.it mem_mode = self.mem_mode) 19111185Serfan.azarkhish@unibo.it system.system_port = system.membus.slave 19211185Serfan.azarkhish@unibo.it system.physmem.port = system.membus.master 19311185Serfan.azarkhish@unibo.it self.init_system(system) 19411185Serfan.azarkhish@unibo.it return system 19511185Serfan.azarkhish@unibo.it 19611185Serfan.azarkhish@unibo.it def create_root(self): 19711185Serfan.azarkhish@unibo.it system = self.create_system() 19811185Serfan.azarkhish@unibo.it m5.ticks.setGlobalFrequency('1THz') 19911185Serfan.azarkhish@unibo.it return Root(full_system=False, system=system) 20011185Serfan.azarkhish@unibo.it 20111185Serfan.azarkhish@unibo.itclass BaseSESystemUniprocessor(BaseSESystem): 20211185Serfan.azarkhish@unibo.it """Basic syscall-emulation builder for uniprocessor systems. 20311185Serfan.azarkhish@unibo.it 20411185Serfan.azarkhish@unibo.it Note: This class is only really needed to provide backwards 20511185Serfan.azarkhish@unibo.it compatibility in existing test cases. 20611185Serfan.azarkhish@unibo.it """ 20711185Serfan.azarkhish@unibo.it 20811185Serfan.azarkhish@unibo.it def __init__(self, **kwargs): 20911185Serfan.azarkhish@unibo.it BaseSESystem.__init__(self, **kwargs) 21011185Serfan.azarkhish@unibo.it 21111185Serfan.azarkhish@unibo.it def create_caches_private(self, cpu): 21211185Serfan.azarkhish@unibo.it # The atomic SE configurations do not use caches 21311185Serfan.azarkhish@unibo.it if self.mem_mode == "timing": 21411185Serfan.azarkhish@unibo.it # @todo We might want to revisit these rather enthusiastic L1 sizes 21511185Serfan.azarkhish@unibo.it cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), 21611185Serfan.azarkhish@unibo.it L1Cache(size='256kB'), 21711185Serfan.azarkhish@unibo.it L2Cache(size='2MB')) 21811185Serfan.azarkhish@unibo.it 21911185Serfan.azarkhish@unibo.it def create_caches_shared(self, system): 22011185Serfan.azarkhish@unibo.it return None 22111185Serfan.azarkhish@unibo.it 22211185Serfan.azarkhish@unibo.itclass BaseFSSystem(BaseSystem): 22311185Serfan.azarkhish@unibo.it """Basic full system builder.""" 22411185Serfan.azarkhish@unibo.it 22511185Serfan.azarkhish@unibo.it def __init__(self, **kwargs): 22611185Serfan.azarkhish@unibo.it BaseSystem.__init__(self, **kwargs) 22711185Serfan.azarkhish@unibo.it 22811185Serfan.azarkhish@unibo.it def init_system(self, system): 22911185Serfan.azarkhish@unibo.it BaseSystem.init_system(self, system) 23011185Serfan.azarkhish@unibo.it 23111185Serfan.azarkhish@unibo.it # create the memory controllers and connect them, stick with 23211185Serfan.azarkhish@unibo.it # the physmem name to avoid bumping all the reference stats 23311185Serfan.azarkhish@unibo.it system.physmem = [self.mem_class(range = r) 23411185Serfan.azarkhish@unibo.it for r in system.mem_ranges] 23511185Serfan.azarkhish@unibo.it for i in xrange(len(system.physmem)): 23611185Serfan.azarkhish@unibo.it system.physmem[i].port = system.membus.master 23711185Serfan.azarkhish@unibo.it 23811185Serfan.azarkhish@unibo.it # create the iocache, which by default runs at the system clock 23911185Serfan.azarkhish@unibo.it system.iocache = IOCache(addr_ranges=system.mem_ranges) 24011185Serfan.azarkhish@unibo.it system.iocache.cpu_side = system.iobus.master 24111185Serfan.azarkhish@unibo.it system.iocache.mem_side = system.membus.slave 24211185Serfan.azarkhish@unibo.it 24311185Serfan.azarkhish@unibo.it def create_root(self): 24411185Serfan.azarkhish@unibo.it system = self.create_system() 24511185Serfan.azarkhish@unibo.it m5.ticks.setGlobalFrequency('1THz') 24611185Serfan.azarkhish@unibo.it return Root(full_system=True, system=system) 24711185Serfan.azarkhish@unibo.it 24811185Serfan.azarkhish@unibo.itclass BaseFSSystemUniprocessor(BaseFSSystem): 24911185Serfan.azarkhish@unibo.it """Basic full system builder for uniprocessor systems. 25011185Serfan.azarkhish@unibo.it 25111185Serfan.azarkhish@unibo.it Note: This class is only really needed to provide backwards 25211185Serfan.azarkhish@unibo.it compatibility in existing test cases. 25311185Serfan.azarkhish@unibo.it """ 25411185Serfan.azarkhish@unibo.it 25511185Serfan.azarkhish@unibo.it def __init__(self, **kwargs): 25611185Serfan.azarkhish@unibo.it BaseFSSystem.__init__(self, **kwargs) 25711185Serfan.azarkhish@unibo.it 25811185Serfan.azarkhish@unibo.it def create_caches_private(self, cpu): 25911185Serfan.azarkhish@unibo.it cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), 26011185Serfan.azarkhish@unibo.it L1Cache(size='32kB', assoc=4), 26111185Serfan.azarkhish@unibo.it L2Cache(size='4MB', assoc=8)) 26211185Serfan.azarkhish@unibo.it 26311185Serfan.azarkhish@unibo.it def create_caches_shared(self, system): 26411185Serfan.azarkhish@unibo.it return None 26511185Serfan.azarkhish@unibo.it 26611185Serfan.azarkhish@unibo.itclass BaseFSSwitcheroo(BaseFSSystem): 26711185Serfan.azarkhish@unibo.it """Uniprocessor system prepared for CPU switching""" 26811185Serfan.azarkhish@unibo.it 26911185Serfan.azarkhish@unibo.it def __init__(self, cpu_classes, **kwargs): 27011185Serfan.azarkhish@unibo.it BaseFSSystem.__init__(self, **kwargs) 27111185Serfan.azarkhish@unibo.it self.cpu_classes = tuple(cpu_classes) 27211185Serfan.azarkhish@unibo.it 27311185Serfan.azarkhish@unibo.it def create_cpus(self, cpu_clk_domain): 27411185Serfan.azarkhish@unibo.it cpus = [ cclass(clk_domain = cpu_clk_domain, 27511185Serfan.azarkhish@unibo.it cpu_id=0, 27611185Serfan.azarkhish@unibo.it switched_out=True) 27711185Serfan.azarkhish@unibo.it for cclass in self.cpu_classes ] 27811185Serfan.azarkhish@unibo.it cpus[0].switched_out = False 27911185Serfan.azarkhish@unibo.it return cpus 28011185Serfan.azarkhish@unibo.it