arm_generic.py revision 12097:77a3d2890ba6
1# Copyright (c) 2012, 2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from abc import ABCMeta, abstractmethod 39import m5 40from m5.objects import * 41from m5.proxy import * 42m5.util.addToPath('../configs/') 43from common import FSConfig 44from common.Caches import * 45from base_config import * 46from common.cores.arm.O3_ARM_v7a import * 47from common.Benchmarks import SysConfig 48 49class ArmSESystemUniprocessor(BaseSESystemUniprocessor): 50 """Syscall-emulation builder for ARM uniprocessor systems. 51 52 A small tweak of the syscall-emulation builder to use more 53 representative cache configurations. 54 """ 55 56 def __init__(self, **kwargs): 57 BaseSESystem.__init__(self, **kwargs) 58 59 def create_caches_private(self, cpu): 60 # The atomic SE configurations do not use caches 61 if self.mem_mode == "timing": 62 # Use the more representative cache configuration 63 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 64 O3_ARM_v7a_DCache(), 65 O3_ARM_v7aL2()) 66 67class LinuxArmSystemBuilder(object): 68 """Mix-in that implements create_system. 69 70 This mix-in is intended as a convenient way of adding an 71 ARM-specific create_system method to a class deriving from one of 72 the generic base systems. 73 """ 74 def __init__(self, machine_type, **kwargs): 75 """ 76 Arguments: 77 machine_type -- String describing the platform to simulate 78 num_cpus -- integer number of CPUs in the system 79 use_ruby -- True if ruby is used instead of the classic memory system 80 """ 81 self.machine_type = machine_type 82 self.num_cpus = kwargs.get('num_cpus', 1) 83 self.mem_size = kwargs.get('mem_size', '256MB') 84 self.use_ruby = kwargs.get('use_ruby', False) 85 86 def create_system(self): 87 sc = SysConfig(None, self.mem_size, None) 88 system = FSConfig.makeArmSystem(self.mem_mode, 89 self.machine_type, self.num_cpus, 90 sc, False, ruby=self.use_ruby) 91 92 # We typically want the simulator to panic if the kernel 93 # panics or oopses. This prevents the simulator from running 94 # an obviously failed test case until the end of time. 95 system.panic_on_panic = True 96 system.panic_on_oops = True 97 98 self.init_system(system) 99 return system 100 101class LinuxArmFSSystem(LinuxArmSystemBuilder, 102 BaseFSSystem): 103 """Basic ARM full system builder.""" 104 105 def __init__(self, machine_type='VExpress_EMM', **kwargs): 106 """Initialize an ARM system that supports full system simulation. 107 108 Note: Keyword arguments that are not listed below will be 109 passed to the BaseFSSystem. 110 111 Keyword Arguments: 112 machine_type -- String describing the platform to simulate 113 """ 114 BaseSystem.__init__(self, **kwargs) 115 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 116 117 def create_caches_private(self, cpu): 118 # Use the more representative cache configuration 119 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 120 O3_ARM_v7a_DCache(), 121 O3_ARM_v7aL2()) 122 123class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, 124 BaseFSSystemUniprocessor): 125 """Basic ARM full system builder for uniprocessor systems. 126 127 Note: This class is a specialization of the ArmFSSystem and is 128 only really needed to provide backwards compatibility for existing 129 test cases. 130 """ 131 132 def __init__(self, machine_type='VExpress_EMM', **kwargs): 133 BaseFSSystemUniprocessor.__init__(self, **kwargs) 134 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 135 136class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): 137 """Uniprocessor ARM system prepared for CPU switching""" 138 139 def __init__(self, machine_type='VExpress_EMM', **kwargs): 140 BaseFSSwitcheroo.__init__(self, **kwargs) 141 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 142