arm_generic.py revision 10512
19380SAndreas.Sandberg@ARM.com# Copyright (c) 2012 ARM Limited 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59380SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69380SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79380SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89380SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99380SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109380SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119380SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129380SAndreas.Sandberg@ARM.com# 139380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239380SAndreas.Sandberg@ARM.com# 249380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359380SAndreas.Sandberg@ARM.com# 369380SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379380SAndreas.Sandberg@ARM.com 389380SAndreas.Sandberg@ARM.comfrom abc import ABCMeta, abstractmethod 399380SAndreas.Sandberg@ARM.comimport m5 409380SAndreas.Sandberg@ARM.comfrom m5.objects import * 419380SAndreas.Sandberg@ARM.comfrom m5.proxy import * 429380SAndreas.Sandberg@ARM.comm5.util.addToPath('../configs/common') 439380SAndreas.Sandberg@ARM.comimport FSConfig 449380SAndreas.Sandberg@ARM.comfrom Caches import * 459380SAndreas.Sandberg@ARM.comfrom base_config import * 4610406Sandreas.hansson@arm.comfrom O3_ARM_v7a import * 4710512SAli.Saidi@ARM.comfrom Benchmarks import SysConfig 4810406Sandreas.hansson@arm.com 4910406Sandreas.hansson@arm.comclass ArmSESystemUniprocessor(BaseSESystemUniprocessor): 5010406Sandreas.hansson@arm.com """Syscall-emulation builder for ARM uniprocessor systems. 5110406Sandreas.hansson@arm.com 5210406Sandreas.hansson@arm.com A small tweak of the syscall-emulation builder to use more 5310406Sandreas.hansson@arm.com representative cache configurations. 5410406Sandreas.hansson@arm.com """ 5510406Sandreas.hansson@arm.com 5610406Sandreas.hansson@arm.com def __init__(self, **kwargs): 5710406Sandreas.hansson@arm.com BaseSESystem.__init__(self, **kwargs) 5810406Sandreas.hansson@arm.com 5910406Sandreas.hansson@arm.com def create_caches_private(self, cpu): 6010406Sandreas.hansson@arm.com # The atomic SE configurations do not use caches 6110406Sandreas.hansson@arm.com if self.mem_mode == "timing": 6210406Sandreas.hansson@arm.com # Use the more representative cache configuration 6310406Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 6410406Sandreas.hansson@arm.com O3_ARM_v7a_DCache(), 6510406Sandreas.hansson@arm.com O3_ARM_v7aL2()) 669380SAndreas.Sandberg@ARM.com 679380SAndreas.Sandberg@ARM.comclass LinuxArmSystemBuilder(object): 689380SAndreas.Sandberg@ARM.com """Mix-in that implements create_system. 699380SAndreas.Sandberg@ARM.com 709380SAndreas.Sandberg@ARM.com This mix-in is intended as a convenient way of adding an 719380SAndreas.Sandberg@ARM.com ARM-specific create_system method to a class deriving from one of 729380SAndreas.Sandberg@ARM.com the generic base systems. 739380SAndreas.Sandberg@ARM.com """ 7410512SAli.Saidi@ARM.com def __init__(self, machine_type, **kwargs): 759380SAndreas.Sandberg@ARM.com """ 769380SAndreas.Sandberg@ARM.com Arguments: 779380SAndreas.Sandberg@ARM.com machine_type -- String describing the platform to simulate 7810512SAli.Saidi@ARM.com num_cpus -- integer number of CPUs in the system 799380SAndreas.Sandberg@ARM.com """ 809380SAndreas.Sandberg@ARM.com self.machine_type = machine_type 8110512SAli.Saidi@ARM.com self.num_cpus = kwargs.get('num_cpus', 1) 8210512SAli.Saidi@ARM.com self.mem_size = kwargs.get('mem_size', '256MB') 839380SAndreas.Sandberg@ARM.com 849380SAndreas.Sandberg@ARM.com def create_system(self): 8510512SAli.Saidi@ARM.com sc = SysConfig(None, self.mem_size, None) 869380SAndreas.Sandberg@ARM.com system = FSConfig.makeArmSystem(self.mem_mode, 8710512SAli.Saidi@ARM.com self.machine_type, self.num_cpus, 8810512SAli.Saidi@ARM.com sc, False) 899649SAndreas.Sandberg@ARM.com 909649SAndreas.Sandberg@ARM.com # We typically want the simulator to panic if the kernel 919649SAndreas.Sandberg@ARM.com # panics or oopses. This prevents the simulator from running 929649SAndreas.Sandberg@ARM.com # an obviously failed test case until the end of time. 939649SAndreas.Sandberg@ARM.com system.panic_on_panic = True 949649SAndreas.Sandberg@ARM.com system.panic_on_oops = True 959649SAndreas.Sandberg@ARM.com 969380SAndreas.Sandberg@ARM.com self.init_system(system) 979380SAndreas.Sandberg@ARM.com return system 989380SAndreas.Sandberg@ARM.com 999380SAndreas.Sandberg@ARM.comclass LinuxArmFSSystem(LinuxArmSystemBuilder, 1009380SAndreas.Sandberg@ARM.com BaseFSSystem): 1019380SAndreas.Sandberg@ARM.com """Basic ARM full system builder.""" 1029380SAndreas.Sandberg@ARM.com 10310512SAli.Saidi@ARM.com def __init__(self, machine_type='VExpress_EMM', **kwargs): 1049380SAndreas.Sandberg@ARM.com """Initialize an ARM system that supports full system simulation. 1059380SAndreas.Sandberg@ARM.com 1069380SAndreas.Sandberg@ARM.com Note: Keyword arguments that are not listed below will be 1079380SAndreas.Sandberg@ARM.com passed to the BaseFSSystem. 1089380SAndreas.Sandberg@ARM.com 1099380SAndreas.Sandberg@ARM.com Keyword Arguments: 1109380SAndreas.Sandberg@ARM.com machine_type -- String describing the platform to simulate 1119380SAndreas.Sandberg@ARM.com """ 1129380SAndreas.Sandberg@ARM.com BaseSystem.__init__(self, **kwargs) 11310512SAli.Saidi@ARM.com LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 1149380SAndreas.Sandberg@ARM.com 11510406Sandreas.hansson@arm.com def create_caches_private(self, cpu): 11610406Sandreas.hansson@arm.com # Use the more representative cache configuration 11710406Sandreas.hansson@arm.com cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 11810406Sandreas.hansson@arm.com O3_ARM_v7a_DCache(), 11910406Sandreas.hansson@arm.com O3_ARM_v7aL2()) 12010406Sandreas.hansson@arm.com 1219380SAndreas.Sandberg@ARM.comclass LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, 1229380SAndreas.Sandberg@ARM.com BaseFSSystemUniprocessor): 1239380SAndreas.Sandberg@ARM.com """Basic ARM full system builder for uniprocessor systems. 1249380SAndreas.Sandberg@ARM.com 1259380SAndreas.Sandberg@ARM.com Note: This class is a specialization of the ArmFSSystem and is 1269380SAndreas.Sandberg@ARM.com only really needed to provide backwards compatibility for existing 1279380SAndreas.Sandberg@ARM.com test cases. 1289380SAndreas.Sandberg@ARM.com """ 1299380SAndreas.Sandberg@ARM.com 13010512SAli.Saidi@ARM.com def __init__(self, machine_type='VExpress_EMM', **kwargs): 1319380SAndreas.Sandberg@ARM.com BaseFSSystemUniprocessor.__init__(self, **kwargs) 13210512SAli.Saidi@ARM.com LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 1339447SAndreas.Sandberg@ARM.com 1349447SAndreas.Sandberg@ARM.comclass LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): 1359447SAndreas.Sandberg@ARM.com """Uniprocessor ARM system prepared for CPU switching""" 1369447SAndreas.Sandberg@ARM.com 13710512SAli.Saidi@ARM.com def __init__(self, machine_type='VExpress_EMM', **kwargs): 1389447SAndreas.Sandberg@ARM.com BaseFSSwitcheroo.__init__(self, **kwargs) 13910512SAli.Saidi@ARM.com LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 140