vexpress_gem5_v2_base.dtsi revision 14114:ed18eaf9d344
1955SN/A/* 2955SN/A * Copyright (c) 2015-2017 ARM Limited 39812Sandreas.hansson@arm.com * All rights reserved 49812Sandreas.hansson@arm.com * 59812Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 69812Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 79812Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 89812Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 99812Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 109812Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 119812Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 129812Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 139812Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 149812Sandreas.hansson@arm.com * this software without specific prior written permission. 157816Ssteve.reinhardt@amd.com * 165871Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171762SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 28955SN/A * Authors: Andreas Sandberg 29955SN/A */ 30955SN/A 31955SN/A/ { 32955SN/A arm,hbi = <0x0>; 33955SN/A arm,vexpress,site = <0xf>; 34955SN/A interrupt-parent = <&gic>; 35955SN/A #address-cells = <2>; 36955SN/A #size-cells = <2>; 37955SN/A 38955SN/A gic: interrupt-controller@2c000000 { 39955SN/A compatible = "arm,gic-v3"; 40955SN/A #interrupt-cells = <0x3>; 41955SN/A #address-cells = <0x2>; 422665Ssaidi@eecs.umich.edu interrupt-controller; 432665Ssaidi@eecs.umich.edu redistributor-stride = <0x0 0x40000>; // 256kB stride 445863Snate@binkert.org reg = <0x0 0x2c000000 0x0 0x10000 45955SN/A 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...) 46955SN/A 0x0 0x0 0x0 0x0>; 47955SN/A interrupts = <1 9 0xf04>; 48955SN/A #size-cells = <0x2>; 49955SN/A linux,phandle = <0x1>; 508878Ssteve.reinhardt@amd.com phandle = <0x1>; 512632Sstever@eecs.umich.edu }; 528878Ssteve.reinhardt@amd.com 532632Sstever@eecs.umich.edu timer { 54955SN/A compatible = "arm,cortex-a15-timer", 558878Ssteve.reinhardt@amd.com "arm,armv7-timer"; 562632Sstever@eecs.umich.edu interrupts = <1 13 0xf08>, 572761Sstever@eecs.umich.edu <1 14 0xf08>, 582632Sstever@eecs.umich.edu <1 11 0xf08>, 592632Sstever@eecs.umich.edu <1 10 0xf08>; 602632Sstever@eecs.umich.edu clocks = <&osc_sys>; 612761Sstever@eecs.umich.edu clock-names="apb_pclk"; 622761Sstever@eecs.umich.edu }; 632761Sstever@eecs.umich.edu 648878Ssteve.reinhardt@amd.com pci { 658878Ssteve.reinhardt@amd.com compatible = "pci-host-ecam-generic"; 662761Sstever@eecs.umich.edu device_type = "pci"; 672761Sstever@eecs.umich.edu #address-cells = <0x3>; 682761Sstever@eecs.umich.edu #size-cells = <0x2>; 692761Sstever@eecs.umich.edu #interrupt-cells = <0x1>; 702761Sstever@eecs.umich.edu 718878Ssteve.reinhardt@amd.com reg = <0x0 0x30000000 0x0 0x10000000>; 728878Ssteve.reinhardt@amd.com 732632Sstever@eecs.umich.edu ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 742632Sstever@eecs.umich.edu <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 758878Ssteve.reinhardt@amd.com 768878Ssteve.reinhardt@amd.com /* 772632Sstever@eecs.umich.edu child unit address, #cells = #address-cells 78955SN/A child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4) 79955SN/A interrupt-parent, phandle 80955SN/A parent unit address, #cells = #address-cells@gic 815863Snate@binkert.org parent interrupt specifier, #cells = #interrupt-cells@gic 825863Snate@binkert.org */ 835863Snate@binkert.org interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1 845863Snate@binkert.org 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1 855863Snate@binkert.org 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1 865863Snate@binkert.org 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>; 875863Snate@binkert.org 885863Snate@binkert.org interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 895863Snate@binkert.org dma-coherent; 905863Snate@binkert.org }; 915863Snate@binkert.org 928878Ssteve.reinhardt@amd.com kmi@1c060000 { 935863Snate@binkert.org compatible = "arm,pl050", "arm,primecell"; 945863Snate@binkert.org reg = <0x0 0x1c060000 0x0 0x1000>; 955863Snate@binkert.org interrupts = <0 12 4>; 969812Sandreas.hansson@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 979812Sandreas.hansson@arm.com clock-names = "KMIREFCLK", "apb_pclk"; 985863Snate@binkert.org }; 999812Sandreas.hansson@arm.com 1005863Snate@binkert.org kmi@1c070000 { 1015863Snate@binkert.org compatible = "arm,pl050", "arm,primecell"; 1025863Snate@binkert.org reg = <0x0 0x1c070000 0x0 0x1000>; 1039812Sandreas.hansson@arm.com interrupts = <0 13 4>; 1049812Sandreas.hansson@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 1055863Snate@binkert.org clock-names = "KMIREFCLK", "apb_pclk"; 1065863Snate@binkert.org }; 1078878Ssteve.reinhardt@amd.com 1085863Snate@binkert.org uart0: uart@1c090000 { 1095863Snate@binkert.org compatible = "arm,pl011", "arm,primecell"; 1105863Snate@binkert.org reg = <0x0 0x1c090000 0x0 0x1000>; 1116654Snate@binkert.org interrupts = <0 5 4>; 112955SN/A clocks = <&osc_peripheral>, <&osc_smb>; 1135396Ssaidi@eecs.umich.edu clock-names = "uartclk", "apb_pclk"; 1145863Snate@binkert.org }; 1155863Snate@binkert.org 1164202Sbinkertn@umich.edu rtc@1c170000 { 1175863Snate@binkert.org compatible = "arm,pl031", "arm,primecell"; 1185863Snate@binkert.org reg = <0x0 0x1c170000 0x0 0x1000>; 1195863Snate@binkert.org interrupts = <0 4 4>; 1205863Snate@binkert.org clocks = <&osc_smb>; 121955SN/A clock-names = "apb_pclk"; 1226654Snate@binkert.org }; 1235273Sstever@gmail.com 1245871Snate@binkert.org v2m_clk24mhz: clk24mhz { 1255273Sstever@gmail.com compatible = "fixed-clock"; 1266655Snate@binkert.org #clock-cells = <0>; 1278878Ssteve.reinhardt@amd.com clock-frequency = <24000000>; 1286655Snate@binkert.org clock-output-names = "v2m:clk24mhz"; 1296655Snate@binkert.org }; 1309219Spower.jg@gmail.com 1316655Snate@binkert.org 1325871Snate@binkert.org v2m_sysreg: sysreg@1c010000 { 1336654Snate@binkert.org compatible = "arm,vexpress-sysreg"; 1348947Sandreas.hansson@arm.com reg = <0 0x1c010000 0x0 0x1000>; 1355396Ssaidi@eecs.umich.edu gpio-controller; 1368120Sgblack@eecs.umich.edu #gpio-cells = <2>; 1378120Sgblack@eecs.umich.edu }; 1388120Sgblack@eecs.umich.edu 1398120Sgblack@eecs.umich.edu vio@1c130000 { 1408120Sgblack@eecs.umich.edu compatible = "virtio,mmio"; 1418120Sgblack@eecs.umich.edu reg = <0 0x1c130000 0x0 0x1000>; 1428120Sgblack@eecs.umich.edu interrupts = <0 42 4>; 1438120Sgblack@eecs.umich.edu }; 1448879Ssteve.reinhardt@amd.com 1458879Ssteve.reinhardt@amd.com vio@1c140000 { 1468879Ssteve.reinhardt@amd.com compatible = "virtio,mmio"; 1478879Ssteve.reinhardt@amd.com reg = <0 0x1c140000 0x0 0x1000>; 1488879Ssteve.reinhardt@amd.com interrupts = <0 43 4>; 1498879Ssteve.reinhardt@amd.com }; 1508879Ssteve.reinhardt@amd.com 1518879Ssteve.reinhardt@amd.com dcc { 1528879Ssteve.reinhardt@amd.com compatible = "arm,vexpress,config-bus"; 1538879Ssteve.reinhardt@amd.com arm,vexpress,config-bridge = <&v2m_sysreg>; 1548879Ssteve.reinhardt@amd.com 1558879Ssteve.reinhardt@amd.com osc_pxl: osc@5 { 1568879Ssteve.reinhardt@amd.com compatible = "arm,vexpress-osc"; 1578120Sgblack@eecs.umich.edu arm,vexpress-sysreg,func = <1 5>; 1588120Sgblack@eecs.umich.edu freq-range = <23750000 1000000000>; 1598120Sgblack@eecs.umich.edu #clock-cells = <0>; 1608120Sgblack@eecs.umich.edu clock-output-names = "oscclk5"; 1618120Sgblack@eecs.umich.edu }; 1628120Sgblack@eecs.umich.edu 1638120Sgblack@eecs.umich.edu osc_smb: osc@6 { 1648120Sgblack@eecs.umich.edu compatible = "arm,vexpress-osc"; 1658120Sgblack@eecs.umich.edu arm,vexpress-sysreg,func = <1 6>; 1668120Sgblack@eecs.umich.edu freq-range = <20000000 50000000>; 1678120Sgblack@eecs.umich.edu #clock-cells = <0>; 1688120Sgblack@eecs.umich.edu clock-output-names = "oscclk6"; 1698120Sgblack@eecs.umich.edu }; 1708120Sgblack@eecs.umich.edu 1718879Ssteve.reinhardt@amd.com osc_sys: osc@7 { 1728879Ssteve.reinhardt@amd.com compatible = "arm,vexpress-osc"; 1738879Ssteve.reinhardt@amd.com arm,vexpress-sysreg,func = <1 7>; 1748879Ssteve.reinhardt@amd.com freq-range = <20000000 60000000>; 1758879Ssteve.reinhardt@amd.com #clock-cells = <0>; 1768879Ssteve.reinhardt@amd.com clock-output-names = "oscclk7"; 1778879Ssteve.reinhardt@amd.com }; 1788879Ssteve.reinhardt@amd.com }; 1799227Sandreas.hansson@arm.com 1809227Sandreas.hansson@arm.com 1818879Ssteve.reinhardt@amd.com mcc { 1828879Ssteve.reinhardt@amd.com compatible = "arm,vexpress,config-bus"; 1838879Ssteve.reinhardt@amd.com arm,vexpress,config-bridge = <&v2m_sysreg>; 1848879Ssteve.reinhardt@amd.com arm,vexpress,site = <0>; 1858120Sgblack@eecs.umich.edu 1868947Sandreas.hansson@arm.com osc_peripheral: osc@2 { 1877816Ssteve.reinhardt@amd.com compatible = "arm,vexpress-osc"; 1885871Snate@binkert.org arm,vexpress-sysreg,func = <1 2>; 1895871Snate@binkert.org freq-range = <24000000 24000000>; 1906121Snate@binkert.org #clock-cells = <0>; 1915871Snate@binkert.org clock-output-names = "v2m:oscclk2"; 1925871Snate@binkert.org }; 1939119Sandreas.hansson@arm.com }; 1949396Sandreas.hansson@arm.com}; 1959396Sandreas.hansson@arm.com