vexpress_gem5_v1.dtsi revision 12737:244581cf780b
1/* 2 * Copyright (c) 2015-2016 ARM Limited 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 */ 30 31/ { 32 arm,hbi = <0x0>; 33 arm,vexpress,site = <0xf>; 34 interrupt-parent = <&gic>; 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 gic: interrupt-controller@2c001000 { 39 compatible = "gem5,gic", "arm,gic-400"; 40 #interrupt-cells = <3>; 41 #address-cells = <0>; 42 interrupt-controller; 43 reg = <0 0x2c001000 0 0x1000>, 44 <0 0x2c002000 0 0x1000>, 45 <0 0x2c004000 0 0x2000>, 46 <0 0x2c006000 0 0x2000>; 47 interrupts = <1 9 0xf04>; 48 }; 49 50 51 timer { 52 compatible = "arm,cortex-a15-timer", 53 "arm,armv7-timer"; 54 interrupts = <1 13 0xf08>, 55 <1 14 0xf08>, 56 <1 11 0xf08>; 57 clocks = <&osc_sys>; 58 clock-names="apb_pclk"; 59 }; 60 61 pci { 62 compatible = "pci-host-ecam-generic"; 63 device_type = "pci"; 64 #address-cells = <0x3>; 65 #size-cells = <0x2>; 66 #interrupt-cells = <0x1>; 67 68 reg = <0x0 0x30000000 0x0 0x10000000>; 69 70 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 71 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 72 73 interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 74 <0x000800 0x0 0x0 0 &gic 0 69 1>, 75 <0x001000 0x0 0x0 0 &gic 0 70 1>, 76 <0x001800 0x0 0x0 0 &gic 0 71 1>; 77 78 interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 79 dma-coherent; 80 }; 81 82 /* Ths HDLCD controller driver hasn't reached mainline 83 * yet. Disable it by default in the platform until the DT 84 * bindings have stabilize. 85 */ 86 hdlcd0: hdlcd@2b000000 { 87 compatible = "arm,hdlcd"; 88 reg = <0x0 0x2b000000 0x0 0x1000>; 89 interrupts = <0 63 4>; 90 clocks = <&osc_pxl>; 91 clock-names = "pxlclk"; 92 93 status = "disabled"; 94 }; 95 96 kmi@1c060000 { 97 compatible = "arm,pl050", "arm,primecell"; 98 reg = <0x0 0x1c060000 0x0 0x1000>; 99 interrupts = <0 12 4>; 100 clocks = <&v2m_clk24mhz>, <&osc_smb>; 101 clock-names = "KMIREFCLK", "apb_pclk"; 102 }; 103 104 kmi@1c070000 { 105 compatible = "arm,pl050", "arm,primecell"; 106 reg = <0x0 0x1c070000 0x0 0x1000>; 107 interrupts = <0 13 4>; 108 clocks = <&v2m_clk24mhz>, <&osc_smb>; 109 clock-names = "KMIREFCLK", "apb_pclk"; 110 }; 111 112 uart0: uart@1c090000 { 113 compatible = "arm,pl011", "arm,primecell"; 114 reg = <0x0 0x1c090000 0x0 0x1000>; 115 interrupts = <0 5 4>; 116 clocks = <&osc_peripheral>, <&osc_smb>; 117 clock-names = "uartclk", "apb_pclk"; 118 }; 119 120 rtc@1c170000 { 121 compatible = "arm,pl031", "arm,primecell"; 122 reg = <0x0 0x1c170000 0x0 0x1000>; 123 interrupts = <0 4 4>; 124 clocks = <&osc_smb>; 125 clock-names = "apb_pclk"; 126 }; 127 128 v2m_clk24mhz: clk24mhz { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <24000000>; 132 clock-output-names = "v2m:clk24mhz"; 133 }; 134 135 136 v2m_sysreg: sysreg@1c010000 { 137 compatible = "arm,vexpress-sysreg"; 138 reg = <0 0x1c010000 0x0 0x1000>; 139 gpio-controller; 140 #gpio-cells = <2>; 141 }; 142 143 dcc { 144 compatible = "arm,vexpress,config-bus"; 145 arm,vexpress,config-bridge = <&v2m_sysreg>; 146 147 osc_pxl: osc@5 { 148 compatible = "arm,vexpress-osc"; 149 arm,vexpress-sysreg,func = <1 5>; 150 freq-range = <23750000 1000000000>; 151 #clock-cells = <0>; 152 clock-output-names = "oscclk5"; 153 }; 154 155 osc_smb: osc@6 { 156 compatible = "arm,vexpress-osc"; 157 arm,vexpress-sysreg,func = <1 6>; 158 freq-range = <20000000 50000000>; 159 #clock-cells = <0>; 160 clock-output-names = "oscclk6"; 161 }; 162 163 osc_sys: osc@7 { 164 compatible = "arm,vexpress-osc"; 165 arm,vexpress-sysreg,func = <1 7>; 166 freq-range = <20000000 60000000>; 167 #clock-cells = <0>; 168 clock-output-names = "oscclk7"; 169 }; 170 }; 171 172 173 mcc { 174 compatible = "arm,vexpress,config-bus"; 175 arm,vexpress,config-bridge = <&v2m_sysreg>; 176 arm,vexpress,site = <0>; 177 178 osc_peripheral: osc@2 { 179 compatible = "arm,vexpress-osc"; 180 arm,vexpress-sysreg,func = <1 2>; 181 freq-range = <24000000 24000000>; 182 #clock-cells = <0>; 183 clock-output-names = "v2m:oscclk2"; 184 }; 185 }; 186}; 187