armv8_big_little.dts revision 11569
1/* 2 * Copyright (c) 2015-2016 ARM Limited 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 * Gabor Dozsa 30 */ 31 32/dts-v1/; 33 34/memreserve/ 0x80000000 0x00010000; 35 36#include CONF_PLATFORM 37 38/* Assign a unique ID for pre-defined configurations. The selected 39 * configuration is picked up from CONF_CPUS 40*/ 41// 2 big and 2 little cpus 42#define _2_2 1 43// 2 big and 4 little cpus 44#define _2_4 2 45 46#define CPU(n,id) \ 47 CPU ## n: cpu@ ## id { \ 48 device_type = "cpu"; \ 49 compatible = "gem5,armv8", "arm,armv8"; \ 50 reg = < ## id >; \ 51 enable-method = "spin-table"; \ 52 cpu-release-addr = <0 0x8000fff8>; \ 53 }; 54 55 56/ { 57 model = "V2P-AARCH64"; 58 compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress"; 59 60 memory@80000000 { 61 device_type = "memory"; 62 reg = <0 0x80000000 0x4 0x00000000>; 63 }; 64 65 66 67 cpus { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 #if CONF_CPUS == _2_2 72 CPU(0,0x0) 73 CPU(1,0x1) 74 CPU(2,0x102) 75 CPU(3,0x103) 76 cpu-map { 77 cluster0 { 78 core0 { cpu = <&CPU0>; }; 79 core1 { cpu = <&CPU1>; }; 80 }; 81 cluster1 { 82 core0 { cpu = <&CPU2>; }; 83 core1 { cpu = <&CPU3>; }; 84 }; 85 }; 86 #elif CONF_CPUS == _2_4 87 CPU(0,0x0) 88 CPU(1,0x1) 89 CPU(2,0x102) 90 CPU(3,0x103) 91 CPU(4,0x104) 92 CPU(5,0x105) 93 cpu-map { 94 cluster0 { 95 core0 { cpu = <&CPU0>; }; 96 core1 { cpu = <&CPU1>; }; 97 }; 98 cluster1 { 99 core0 { cpu = <&CPU2>; }; 100 core1 { cpu = <&CPU3>; }; 101 core2 { cpu = <&CPU4>; }; 102 core3 { cpu = <&CPU5>; }; 103 }; 104 }; 105 #else 106 #error Missing configuration section 107 #endif 108 }; 109 110 virt-encoder { 111 compatible = "drm,virtual-encoder"; 112 port { 113 hdlcd0_virt_input: endpoint@0 { 114 remote-endpoint = <&hdlcd0_output>; 115 }; 116 }; 117 118 display-timings { 119 native-mode = <&timing0>; 120 121 timing0: timing_1080p60 { 122 /* 1920x1080-60 */ 123 clock-frequency = <148500000>; 124 hactive = <1920>; 125 vactive = <1080>; 126 hfront-porch = <148>; 127 hback-porch = <88>; 128 hsync-len = <44>; 129 vfront-porch = <36>; 130 vback-porch = <4>; 131 vsync-len = <5>; 132 }; 133 }; 134 }; 135}; 136 137&hdlcd0 { 138 status = "ok"; 139 140 port { 141 hdlcd0_output: endpoint@0 { 142 remote-endpoint = <&hdlcd0_virt_input>; 143 }; 144 }; 145}; 146 147 148