boot.S revision 13509
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2012 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com */ 387405SAli.Saidi@ARM.com 397405SAli.Saidi@ARM.com .text 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com .globl _start 4210461SAndreas.Sandberg@ARM.com_start: 439050Schander.sudanthi@arm.com /* 448887Sgeoffrey.blake@arm.com * EL3 initialisation 4510461SAndreas.Sandberg@ARM.com */ 468232Snate@binkert.org mrs x0, CurrentEL 478232Snate@binkert.org cmp x0, #0xc // EL3? 4810844Sandreas.sandberg@arm.com b.ne start_ns // skip EL3 initialisation 499384SAndreas.Sandberg@arm.com 507678Sgblack@eecs.umich.edu mov x0, #0x30 // RES1 518059SAli.Saidi@ARM.com orr x0, x0, #(1 << 0) // Non-secure EL1 528284SAli.Saidi@ARM.com orr x0, x0, #(1 << 8) // HVC enable 537405SAli.Saidi@ARM.com orr x0, x0, #(1 << 10) // 64-bit EL2 547405SAli.Saidi@ARM.com msr scr_el3, x0 557405SAli.Saidi@ARM.com 567405SAli.Saidi@ARM.com msr cptr_el3, xzr // Disable copro. traps to EL3 5710037SARM gem5 Developers 5810037SARM gem5 Developers ldr x0, =CNTFRQ 5911768SCurtis.Dunham@arm.com msr cntfrq_el0, x0 6010037SARM gem5 Developers 6110037SARM gem5 Developers /* 6210037SARM gem5 Developers * Check for the primary CPU to avoid a race on the distributor 6310037SARM gem5 Developers * registers. 6411768SCurtis.Dunham@arm.com */ 6510037SARM gem5 Developers mrs x0, mpidr_el1 6610037SARM gem5 Developers // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 6711768SCurtis.Dunham@arm.com // Test the the MPIDR_EL1 register against 0xff00ffffff to 6811768SCurtis.Dunham@arm.com // extract the primary CPU. 6911768SCurtis.Dunham@arm.com ldr x1, =0xff00ffffff 7011768SCurtis.Dunham@arm.com#ifdef GICV3 7111768SCurtis.Dunham@arm.com and x2, x0, #0xff // use Aff0 as cpuid for now... 7211768SCurtis.Dunham@arm.com tst x0, x1 // check for cpuid==zero 7311768SCurtis.Dunham@arm.com b.ne 1f // secondary CPU 7411768SCurtis.Dunham@arm.com 7511768SCurtis.Dunham@arm.com ldr x1, =GIC_DIST_BASE // GICD_CTLR 7611768SCurtis.Dunham@arm.com mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S 7711768SCurtis.Dunham@arm.com str w0, [x1] 7811768SCurtis.Dunham@arm.com 7910037SARM gem5 Developers 8010037SARM gem5 Developers1: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0 8110037SARM gem5 Developers // 128K for each redistributor, 256K strided... 8211768SCurtis.Dunham@arm.com mov x3, #1 << 18 // GICv4 8311768SCurtis.Dunham@arm.com mul x3, x3, x2 8411768SCurtis.Dunham@arm.com add x1, x1, x3 8511768SCurtis.Dunham@arm.com mov w0, #~0 // Grp1 interrupts 8611768SCurtis.Dunham@arm.com str w0, [x1], #4 8711768SCurtis.Dunham@arm.com b.ne 2f // Only local interrupts for secondary CPUs 8811768SCurtis.Dunham@arm.com ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR 8911768SCurtis.Dunham@arm.com str w0, [x1], #4 9010037SARM gem5 Developers str w0, [x1], #4 9111768SCurtis.Dunham@arm.com str w0, [x1], #4 9211768SCurtis.Dunham@arm.com 9311768SCurtis.Dunham@arm.com 9411768SCurtis.Dunham@arm.com2: mov x0, #1 9510037SARM gem5 Developers msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable 9611768SCurtis.Dunham@arm.com msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable 9711768SCurtis.Dunham@arm.com#else 9811768SCurtis.Dunham@arm.com tst x0, x1 // check for cpuid==zero 9911768SCurtis.Dunham@arm.com b.ne 1f // secondary CPU 10011768SCurtis.Dunham@arm.com 10111768SCurtis.Dunham@arm.com ldr x1, =GIC_DIST_BASE // GICD_CTLR 10211768SCurtis.Dunham@arm.com mov w0, #3 // EnableGrp0 | EnableGrp1 10311768SCurtis.Dunham@arm.com str w0, [x1] 10411768SCurtis.Dunham@arm.com 10511768SCurtis.Dunham@arm.com1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR 10611768SCurtis.Dunham@arm.com mov w0, #~0 // Grp1 interrupts 10711768SCurtis.Dunham@arm.com str w0, [x1], #4 10811768SCurtis.Dunham@arm.com b.ne 2f // Only local interrupts for secondary CPUs 10911768SCurtis.Dunham@arm.com str w0, [x1], #4 11011768SCurtis.Dunham@arm.com str w0, [x1], #4 11111768SCurtis.Dunham@arm.com 11211768SCurtis.Dunham@arm.com2: ldr x1, =GIC_CPU_BASE // GICC_CTLR 11311768SCurtis.Dunham@arm.com ldr w0, [x1] 11410037SARM gem5 Developers mov w0, #3 // EnableGrp0 | EnableGrp1 11511768SCurtis.Dunham@arm.com str w0, [x1] 11611768SCurtis.Dunham@arm.com 11711768SCurtis.Dunham@arm.com mov w0, #1 << 7 // allow NS access to GICC_PMR 11811768SCurtis.Dunham@arm.com str w0, [x1, #4] // GICC_PMR 11910037SARM gem5 Developers#endif 12011768SCurtis.Dunham@arm.com 12111768SCurtis.Dunham@arm.com msr sctlr_el2, xzr 12211768SCurtis.Dunham@arm.com 12311768SCurtis.Dunham@arm.com /* 12411768SCurtis.Dunham@arm.com * Prepare the switch to the EL2_SP1 mode from EL3 12511768SCurtis.Dunham@arm.com */ 12610037SARM gem5 Developers ldr x0, =start_ns // Return after mode switch 12711768SCurtis.Dunham@arm.com mov x1, #0x3c9 // EL2_SP1 | D | A | I | F 12811768SCurtis.Dunham@arm.com msr elr_el3, x0 12911768SCurtis.Dunham@arm.com msr spsr_el3, x1 13011768SCurtis.Dunham@arm.com eret 13111768SCurtis.Dunham@arm.com 13211768SCurtis.Dunham@arm.comstart_ns: 13311768SCurtis.Dunham@arm.com /* 13411768SCurtis.Dunham@arm.com * Kernel parameters 13511768SCurtis.Dunham@arm.com */ 13611768SCurtis.Dunham@arm.com mov x0, xzr 13711768SCurtis.Dunham@arm.com mov x1, xzr 13811768SCurtis.Dunham@arm.com mov x2, xzr 13911768SCurtis.Dunham@arm.com mov x3, xzr 14011768SCurtis.Dunham@arm.com 14111768SCurtis.Dunham@arm.com mrs x4, mpidr_el1 14211768SCurtis.Dunham@arm.com // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 14311768SCurtis.Dunham@arm.com // Test the the MPIDR_EL1 register against 0xff00ffffff to 14411768SCurtis.Dunham@arm.com // extract the primary CPU. 14511768SCurtis.Dunham@arm.com ldr x1, =0xff00ffffff 14611768SCurtis.Dunham@arm.com tst x4, x1 // check for cpuid==zero 14711768SCurtis.Dunham@arm.com mov x1, xzr // load previous 'xzr' value back to x1 14811768SCurtis.Dunham@arm.com b.eq 2f // secondary CPU 14911768SCurtis.Dunham@arm.com 15011768SCurtis.Dunham@arm.com /* 15111768SCurtis.Dunham@arm.com * Secondary CPUs 15211768SCurtis.Dunham@arm.com */ 15311768SCurtis.Dunham@arm.com1: wfe 15411768SCurtis.Dunham@arm.com ldr x4, =PHYS_OFFSET + 0xfff8 15511768SCurtis.Dunham@arm.com ldr x4, [x4] 15611768SCurtis.Dunham@arm.com cbz x4, 1b 15711768SCurtis.Dunham@arm.com br x4 // branch to the given address 15811768SCurtis.Dunham@arm.com 15911768SCurtis.Dunham@arm.com2: 16011768SCurtis.Dunham@arm.com /* 16111768SCurtis.Dunham@arm.com * UART initialisation (38400 8N1) 16211768SCurtis.Dunham@arm.com */ 16311768SCurtis.Dunham@arm.com ldr x4, =UART_BASE // UART base 16411768SCurtis.Dunham@arm.com mov w5, #0x10 // ibrd 16511768SCurtis.Dunham@arm.com str w5, [x4, #0x24] 16611768SCurtis.Dunham@arm.com mov w5, #0xc300 16711768SCurtis.Dunham@arm.com orr w5, w5, #0x0001 // cr 16811768SCurtis.Dunham@arm.com str w5, [x4, #0x30] 16911768SCurtis.Dunham@arm.com 17011768SCurtis.Dunham@arm.com /* 17111768SCurtis.Dunham@arm.com * CLCD output site MB 17211768SCurtis.Dunham@arm.com */ 17311768SCurtis.Dunham@arm.com ldr x4, =SYSREGS_BASE 17411768SCurtis.Dunham@arm.com ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB 17511768SCurtis.Dunham@arm.com str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA 17611768SCurtis.Dunham@arm.com str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL 17711768SCurtis.Dunham@arm.com 17811768SCurtis.Dunham@arm.com // set up the arch timer frequency 17911768SCurtis.Dunham@arm.com //ldr x0, =CNTFRQ 18011768SCurtis.Dunham@arm.com //msr cntfrq_el0, x0 18111768SCurtis.Dunham@arm.com 18211768SCurtis.Dunham@arm.com /* 18311768SCurtis.Dunham@arm.com * Primary CPU 18411768SCurtis.Dunham@arm.com */ 18511768SCurtis.Dunham@arm.com ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob 18611768SCurtis.Dunham@arm.com ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address 18711768SCurtis.Dunham@arm.com br x6 18811768SCurtis.Dunham@arm.com 18911768SCurtis.Dunham@arm.com .ltorg 19011768SCurtis.Dunham@arm.com 19111768SCurtis.Dunham@arm.com .org 0x200 19211768SCurtis.Dunham@arm.com