platform.S revision 8017
18013Sbinkertn@umich.edu/* 28013Sbinkertn@umich.edu * Copyright (c) 2003, 2004, 2005 38013Sbinkertn@umich.edu * The Regents of The University of Michigan 48013Sbinkertn@umich.edu * All Rights Reserved 58013Sbinkertn@umich.edu * 68013Sbinkertn@umich.edu * This code is part of the M5 simulator, developed by Nathan Binkert, 78013Sbinkertn@umich.edu * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 88013Sbinkertn@umich.edu * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew 98013Sbinkertn@umich.edu * Schultz. 108013Sbinkertn@umich.edu * 118013Sbinkertn@umich.edu * Permission is granted to use, copy, create derivative works and 128013Sbinkertn@umich.edu * redistribute this software and such derivative works for any 138013Sbinkertn@umich.edu * purpose, so long as the copyright notice above, this grant of 148013Sbinkertn@umich.edu * permission, and the disclaimer below appear in all copies made; and 158013Sbinkertn@umich.edu * so long as the name of The University of Michigan is not used in 168013Sbinkertn@umich.edu * any advertising or publicity pertaining to the use or distribution 178013Sbinkertn@umich.edu * of this software without specific, written prior authorization. 188013Sbinkertn@umich.edu * 198013Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 208013Sbinkertn@umich.edu * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 218013Sbinkertn@umich.edu * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 228013Sbinkertn@umich.edu * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 238013Sbinkertn@umich.edu * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 248013Sbinkertn@umich.edu * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 258013Sbinkertn@umich.edu * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 268013Sbinkertn@umich.edu * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 278013Sbinkertn@umich.edu * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 288013Sbinkertn@umich.edu * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 298013Sbinkertn@umich.edu * DAMAGES. 308013Sbinkertn@umich.edu */ 318013Sbinkertn@umich.edu 328013Sbinkertn@umich.edu/* 338013Sbinkertn@umich.edu * Copyright 1993 Hewlett-Packard Development Company, L.P. 348013Sbinkertn@umich.edu * 358013Sbinkertn@umich.edu * Permission is hereby granted, free of charge, to any person 368013Sbinkertn@umich.edu * obtaining a copy of this software and associated documentation 378013Sbinkertn@umich.edu * files (the "Software"), to deal in the Software without 388013Sbinkertn@umich.edu * restriction, including without limitation the rights to use, copy, 398013Sbinkertn@umich.edu * modify, merge, publish, distribute, sublicense, and/or sell copies 408013Sbinkertn@umich.edu * of the Software, and to permit persons to whom the Software is 418013Sbinkertn@umich.edu * furnished to do so, subject to the following conditions: 428013Sbinkertn@umich.edu * 438013Sbinkertn@umich.edu * The above copyright notice and this permission notice shall be 448013Sbinkertn@umich.edu * included in all copies or substantial portions of the Software. 458013Sbinkertn@umich.edu * 468013Sbinkertn@umich.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 478013Sbinkertn@umich.edu * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 488013Sbinkertn@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 498013Sbinkertn@umich.edu * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 508013Sbinkertn@umich.edu * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 518013Sbinkertn@umich.edu * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 528013Sbinkertn@umich.edu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 538013Sbinkertn@umich.edu * SOFTWARE. 548013Sbinkertn@umich.edu */ 558013Sbinkertn@umich.edu 568013Sbinkertn@umich.edu#define max_cpuid 1 578013Sbinkertn@umich.edu#define hw_rei_spe hw_rei 588013Sbinkertn@umich.edu 598013Sbinkertn@umich.edu#include "ev5_defs.h" 608013Sbinkertn@umich.edu#include "ev5_impure.h" 618013Sbinkertn@umich.edu#include "ev5_alpha_defs.h" 628013Sbinkertn@umich.edu#include "ev5_paldef.h" 638013Sbinkertn@umich.edu#include "ev5_osfalpha_defs.h" 648013Sbinkertn@umich.edu#include "fromHudsonMacros.h" 658013Sbinkertn@umich.edu#include "fromHudsonOsf.h" 668013Sbinkertn@umich.edu#include "dc21164FromGasSources.h" 678013Sbinkertn@umich.edu#include "cserve.h" 688013Sbinkertn@umich.edu#include "tlaser.h" 698013Sbinkertn@umich.edu 708013Sbinkertn@umich.edu#define pt_entInt pt_entint 718013Sbinkertn@umich.edu#define pt_entArith pt_entarith 728013Sbinkertn@umich.edu#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8) 738013Sbinkertn@umich.edu#define mchk_flag CNS_Q_FLAG 748013Sbinkertn@umich.edu#define mchk_sys_base 56 758013Sbinkertn@umich.edu#define mchk_cpu_base (CNS_Q_LD_LOCK + 8) 768013Sbinkertn@umich.edu#define mchk_offsets CNS_Q_EXC_ADDR 778013Sbinkertn@umich.edu#define mchk_mchk_code 8 788013Sbinkertn@umich.edu#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT 798013Sbinkertn@umich.edu#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT 808013Sbinkertn@umich.edu#define mchk_sc_addr CNS_Q_SC_ADDR 818013Sbinkertn@umich.edu#define mchk_sc_stat CNS_Q_SC_STAT 828013Sbinkertn@umich.edu#define mchk_ei_addr CNS_Q_EI_ADDR 838013Sbinkertn@umich.edu#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR 848013Sbinkertn@umich.edu#define mchk_fill_syn CNS_Q_FILL_SYN 858013Sbinkertn@umich.edu#define mchk_ei_stat CNS_Q_EI_STAT 868013Sbinkertn@umich.edu#define mchk_exc_addr CNS_Q_EXC_ADDR 878013Sbinkertn@umich.edu#define mchk_ld_lock CNS_Q_LD_LOCK 888013Sbinkertn@umich.edu#define osfpcb_q_Ksp pcb_q_ksp 898013Sbinkertn@umich.edu#define pal_impure_common_size ((0x200 + 7) & 0xfff8) 908013Sbinkertn@umich.edu 918013Sbinkertn@umich.edu#if defined(BIG_TSUNAMI) 928013Sbinkertn@umich.edu#define MAXPROC 0x3f 938013Sbinkertn@umich.edu#define IPIQ_addr 0x800 948013Sbinkertn@umich.edu#define IPIQ_shift 0 958013Sbinkertn@umich.edu#define IPIR_addr 0x840 968013Sbinkertn@umich.edu#define IPIR_shift 0 978013Sbinkertn@umich.edu#define RTC_addr 0x880 988013Sbinkertn@umich.edu#define RTC_shift 0 998013Sbinkertn@umich.edu#define DIR_addr 0xa2 1008013Sbinkertn@umich.edu#elif defined(TSUNAMI) 1018013Sbinkertn@umich.edu#define MAXPROC 0x3 1028013Sbinkertn@umich.edu#define IPIQ_addr 0x080 1038013Sbinkertn@umich.edu#define IPIQ_shift 12 1048013Sbinkertn@umich.edu#define IPIR_addr 0x080 1058013Sbinkertn@umich.edu#define IPIR_shift 8 1068013Sbinkertn@umich.edu#define RTC_addr 0x080 1078013Sbinkertn@umich.edu#define RTC_shift 4 1088013Sbinkertn@umich.edu#define DIR_addr 0xa0 1098013Sbinkertn@umich.edu#elif defined(TLASER) 1108013Sbinkertn@umich.edu#define MAXPROC 0xf 1118013Sbinkertn@umich.edu#else 1128013Sbinkertn@umich.edu#error Must define BIG_TSUNAMI, TSUNAMI, or TLASER 1138013Sbinkertn@umich.edu#endif 1148013Sbinkertn@umich.edu 1158013Sbinkertn@umich.edu#define ALIGN_BLOCK \ 1168013Sbinkertn@umich.edu .align 5 1178013Sbinkertn@umich.edu 1188013Sbinkertn@umich.edu#define ALIGN_BRANCH \ 1198013Sbinkertn@umich.edu .align 3 1208013Sbinkertn@umich.edu 1218013Sbinkertn@umich.edu#define EXPORT(_x) \ 1228013Sbinkertn@umich.edu .align 5; \ 1238013Sbinkertn@umich.edu .globl _x; \ 1248013Sbinkertn@umich.edu_x: 1258013Sbinkertn@umich.edu 1268013Sbinkertn@umich.edu// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 1278013Sbinkertn@umich.edu// XXX the following is 'made up' 1288013Sbinkertn@umich.edu// XXX bugnion 1298013Sbinkertn@umich.edu 1308013Sbinkertn@umich.edu// XXX bugnion not sure how to align 'quad' 1318013Sbinkertn@umich.edu#define ALIGN_QUAD \ 1328013Sbinkertn@umich.edu .align 3 1338013Sbinkertn@umich.edu 1348013Sbinkertn@umich.edu#define ALIGN_128 \ 1358013Sbinkertn@umich.edu .align 7 1368013Sbinkertn@umich.edu 1378013Sbinkertn@umich.edu 1388013Sbinkertn@umich.edu#define GET_IMPURE(_r) mfpr _r,pt_impure 1398013Sbinkertn@umich.edu#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2) 1408013Sbinkertn@umich.edu 1418013Sbinkertn@umich.edu 1428013Sbinkertn@umich.edu#define BIT(_x) (1<<(_x)) 1438013Sbinkertn@umich.edu 1448013Sbinkertn@umich.edu 1458013Sbinkertn@umich.edu// System specific code - beh model version 1468013Sbinkertn@umich.edu// 1478013Sbinkertn@umich.edu// 1488013Sbinkertn@umich.edu// Entry points 1498013Sbinkertn@umich.edu// SYS_CFLUSH - Cache flush 1508013Sbinkertn@umich.edu// SYS_CSERVE - Console service 1518013Sbinkertn@umich.edu// SYS_WRIPIR - interprocessor interrupts 1528013Sbinkertn@umich.edu// SYS_HALT_INTERRUPT - Halt interrupt 1538013Sbinkertn@umich.edu// SYS_PASSIVE_RELEASE - Interrupt, passive release 1548013Sbinkertn@umich.edu// SYS_INTERRUPT - Interrupt 1558013Sbinkertn@umich.edu// SYS_RESET - Reset 1568013Sbinkertn@umich.edu// SYS_ENTER_CONSOLE 1578013Sbinkertn@umich.edu// 1588013Sbinkertn@umich.edu// 1598013Sbinkertn@umich.edu// Macro to read TLINTRSUMx 1608013Sbinkertn@umich.edu// 1618013Sbinkertn@umich.edu// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register 1628013Sbinkertn@umich.edu// 1638013Sbinkertn@umich.edu// Assumed register usage: 1648013Sbinkertn@umich.edu// rsum TLINTRSUMx contents 1658013Sbinkertn@umich.edu// raddr node space address 1668013Sbinkertn@umich.edu// scratch scratch register 1678013Sbinkertn@umich.edu// 1688013Sbinkertn@umich.edu#define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \ 1698013Sbinkertn@umich.edu nop; \ 1708013Sbinkertn@umich.edu mfpr _scratch, pt_whami; /* Get our whami (VID) */ \ 1718013Sbinkertn@umich.edu extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \ 1728013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ 1738013Sbinkertn@umich.edu sll _raddr, 24, _raddr; /* Shift up to proper position */ \ 1748013Sbinkertn@umich.edu srl _scratch, 1, _rsum; /* Shift off the cpu number */ \ 1758013Sbinkertn@umich.edu sll _rsum, 22, _rsum; /* Get our node offset */ \ 1768013Sbinkertn@umich.edu addq _raddr, _rsum, _raddr; /* Get our base node space address */ \ 1778013Sbinkertn@umich.edu blbs _scratch, 1f; \ 1788013Sbinkertn@umich.edu lda _raddr, 0x1180(_raddr); \ 1798013Sbinkertn@umich.edu br r31, 2f; \ 1808013Sbinkertn@umich.edu1: lda _raddr, 0x11c0(_raddr); \ 1818013Sbinkertn@umich.edu2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */ 1828013Sbinkertn@umich.edu 1838013Sbinkertn@umich.edu// 1848013Sbinkertn@umich.edu// Macro to write TLINTRSUMx 1858013Sbinkertn@umich.edu// 1868013Sbinkertn@umich.edu// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register 1878013Sbinkertn@umich.edu// 1888013Sbinkertn@umich.edu// Assumed register usage: 1898013Sbinkertn@umich.edu// rsum TLINTRSUMx write data 1908013Sbinkertn@umich.edu// raddr node space address 1918013Sbinkertn@umich.edu// scratch scratch register 1928013Sbinkertn@umich.edu// 1938013Sbinkertn@umich.edu#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \ 1948013Sbinkertn@umich.edu nop; \ 1958013Sbinkertn@umich.edu mfpr _whami, pt_whami; /* Get our whami (VID) */ \ 1968013Sbinkertn@umich.edu extbl _whami, 1, _whami; /* shift down to bit 0 */ \ 1978013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ 1988013Sbinkertn@umich.edu sll _raddr, 24, _raddr; /* Shift up to proper position */ \ 1998013Sbinkertn@umich.edu blbs _whami, 1f; \ 2008013Sbinkertn@umich.edu lda _raddr, 0x1180(_raddr); \ 2018013Sbinkertn@umich.edu br zero, 2f; \ 2028013Sbinkertn@umich.edu1: lda _raddr, 0x11c0(_raddr); \ 2038013Sbinkertn@umich.edu2: srl _whami, 1, _whami; /* Get our node offset */ \ 2048013Sbinkertn@umich.edu addq _raddr, _whami, _raddr; /* Get our base node space address */ \ 2058013Sbinkertn@umich.edu mb; \ 2068013Sbinkertn@umich.edu stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \ 2078013Sbinkertn@umich.edu ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \ 2088013Sbinkertn@umich.edu bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */ 2098013Sbinkertn@umich.edu 2108013Sbinkertn@umich.edu 2118013Sbinkertn@umich.edu// 2128013Sbinkertn@umich.edu// Macro to determine highest priority TIOP Node ID from interrupt pending mask 2138013Sbinkertn@umich.edu// 2148013Sbinkertn@umich.edu// Assumed register usage: 2158013Sbinkertn@umich.edu// rmask - TLINTRSUMx contents, shifted to isolate IOx bits 2168013Sbinkertn@umich.edu// rid - TLSB Node ID of highest TIOP 2178013Sbinkertn@umich.edu// 2188013Sbinkertn@umich.edu#define Intr_Find_TIOP(_rmask,_rid) \ 2198013Sbinkertn@umich.edu srl _rmask,3,_rid; /* check IOP8 */ \ 2208013Sbinkertn@umich.edu blbc _rid,1f; /* not IOP8 */ \ 2218013Sbinkertn@umich.edu lda _rid,8(zero); /* IOP8 */ \ 2228013Sbinkertn@umich.edu br zero,6f; \ 2238013Sbinkertn@umich.edu1: srl _rmask,3,_rid; /* check IOP7 */ \ 2248013Sbinkertn@umich.edu blbc _rid, 2f; /* not IOP7 */ \ 2258013Sbinkertn@umich.edu lda _rid, 7(r31); /* IOP7 */ \ 2268013Sbinkertn@umich.edu br r31, 6f; \ 2278013Sbinkertn@umich.edu2: srl _rmask, 2, _rid; /* check IOP6 */ \ 2288013Sbinkertn@umich.edu blbc _rid, 3f; /* not IOP6 */ \ 2298013Sbinkertn@umich.edu lda _rid, 6(r31); /* IOP6 */ \ 2308013Sbinkertn@umich.edu br r31, 6f; \ 2318013Sbinkertn@umich.edu3: srl _rmask, 1, _rid; /* check IOP5 */ \ 2328013Sbinkertn@umich.edu blbc _rid, 4f; /* not IOP5 */ \ 2338013Sbinkertn@umich.edu lda _rid, 5(r31); /* IOP5 */ \ 2348013Sbinkertn@umich.edu br r31, 6f; \ 2358013Sbinkertn@umich.edu4: srl _rmask, 0, _rid; /* check IOP4 */ \ 2368013Sbinkertn@umich.edu blbc _rid, 5f; /* not IOP4 */ \ 2378013Sbinkertn@umich.edu lda r14, 4(r31); /* IOP4 */ \ 2388013Sbinkertn@umich.edu br r31, 6f; \ 2398013Sbinkertn@umich.edu5: lda r14, 0(r31); /* passive release */ \ 2408013Sbinkertn@umich.edu6: 2418013Sbinkertn@umich.edu 2428013Sbinkertn@umich.edu// 2438013Sbinkertn@umich.edu// Macro to calculate base node space address for given node id 2448013Sbinkertn@umich.edu// 2458013Sbinkertn@umich.edu// Assumed register usage: 2468013Sbinkertn@umich.edu// rid - TLSB node id 2478013Sbinkertn@umich.edu// raddr - base node space address 2488013Sbinkertn@umich.edu#define Get_TLSB_Node_Address(_rid,_raddr) \ 2498013Sbinkertn@umich.edu sll _rid, 22, _rid; \ 2508013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); \ 2518013Sbinkertn@umich.edu sll _raddr, 24, _raddr; \ 2528013Sbinkertn@umich.edu addq _raddr, _rid, _raddr 2538013Sbinkertn@umich.edu 2548013Sbinkertn@umich.edu 2558013Sbinkertn@umich.edu#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2568013Sbinkertn@umich.edu lda _rs1, tlep_##_tlepreg(zero); \ 2578013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2588013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2598013Sbinkertn@umich.edu stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */ 2608013Sbinkertn@umich.edu 2618013Sbinkertn@umich.edu#define OSFmchk_TLEPstore(_tlepreg) \ 2628013Sbinkertn@umich.edu OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg) 2638013Sbinkertn@umich.edu 2648013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2658013Sbinkertn@umich.edu lda _rs1, tlep_##_tlepreg(zero); \ 2668013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2678013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2688013Sbinkertn@umich.edu stl_p _rs, mchk_crd_##_tlepreg(_rlog) 2698013Sbinkertn@umich.edu 2708013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2718013Sbinkertn@umich.edu lda _rs1, tlsb_##_tlepreg(zero); \ 2728013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2738013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2748013Sbinkertn@umich.edu stl_p _rs,mchk_crd_##_tlepreg(_rlog) 2758013Sbinkertn@umich.edu 2768013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2778013Sbinkertn@umich.edu lda _rs1,tlsb_##_tlepreg(zero); \ 2788013Sbinkertn@umich.edu or _rs1, _nodebase,_rs1; \ 2798013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2808013Sbinkertn@umich.edu stl_p _rs, mchk_crd_##_tlepreg(_rlog); \ 2818013Sbinkertn@umich.edu stl_p _rs, 0(_rs1) 2828013Sbinkertn@umich.edu 2838013Sbinkertn@umich.edu#define OSFcrd_TLEPstore(_tlepreg) \ 2848013Sbinkertn@umich.edu OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg) 2858013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb(_tlepreg) \ 2868013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg) 2878013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \ 2888013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg) 2898013Sbinkertn@umich.edu 2908013Sbinkertn@umich.edu 2918013Sbinkertn@umich.edu#define save_pcia_intr(_irq) \ 2928013Sbinkertn@umich.edu and r13, 0xf, r25; /* isolate low 4 bits */ \ 2938013Sbinkertn@umich.edu addq r14, 4, r14; /* format the TIOP Node id field */ \ 2948013Sbinkertn@umich.edu sll r14, 4, r14; /* shift the TIOP Node id */ \ 2958013Sbinkertn@umich.edu or r14, r25, r10; /* merge Node id/hose/HPC */ \ 2968013Sbinkertn@umich.edu mfpr r14, pt14; /* get saved value */ \ 2978013Sbinkertn@umich.edu extbl r14, _irq, r25; /* confirm none outstanding */ \ 2988013Sbinkertn@umich.edu bne r25, sys_machine_check_while_in_pal; \ 2998013Sbinkertn@umich.edu insbl r10, _irq, r10; /* align new info */ \ 3008013Sbinkertn@umich.edu or r14, r10, r14; /* merge info */ \ 3018013Sbinkertn@umich.edu mtpr r14, pt14; /* save it */ \ 3028013Sbinkertn@umich.edu bic r13, 0xf, r13 /* clear low 4 bits of vector */ 3038013Sbinkertn@umich.edu 3048013Sbinkertn@umich.edu 3058013Sbinkertn@umich.edu// wripir - PALcode for wripir instruction 3068013Sbinkertn@umich.edu// R16 has the processor number. 3078013Sbinkertn@umich.edu// 3088013Sbinkertn@umich.edu ALIGN_BLOCK 3098013Sbinkertn@umich.eduEXPORT(sys_wripir) 3108013Sbinkertn@umich.edu // 3118013Sbinkertn@umich.edu // Convert the processor number to a CPU mask 3128013Sbinkertn@umich.edu // 3138013Sbinkertn@umich.edu and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported 3148013Sbinkertn@umich.edu bis r31, 0x1, r16 // get a one 3158013Sbinkertn@umich.edu sll r16, r14, r14 // shift the bit to the right place 3168017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 3178017Sbinkertn@umich.edu sll r14,IPIQ_shift,r14 3188017Sbinkertn@umich.edu#endif 3198017Sbinkertn@umich.edu 3208013Sbinkertn@umich.edu 3218013Sbinkertn@umich.edu // 3228013Sbinkertn@umich.edu // Build the Broadcast Space base address 3238013Sbinkertn@umich.edu // 3248017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 3258017Sbinkertn@umich.edu lda r16,0xf01(r31) 3268017Sbinkertn@umich.edu sll r16,32,r16 3278017Sbinkertn@umich.edu ldah r13,0xa0(r31) 3288017Sbinkertn@umich.edu sll r13,8,r13 3298017Sbinkertn@umich.edu bis r16,r13,r16 3308017Sbinkertn@umich.edu lda r16,IPIQ_addr(r16) 3318017Sbinkertn@umich.edu#elif defined(TLASER) 3328013Sbinkertn@umich.edu lda r13, 0xff8e(r31) // Load the upper address bits 3338013Sbinkertn@umich.edu sll r13, 24, r13 // shift them to the top 3348017Sbinkertn@umich.edu#endif 3358013Sbinkertn@umich.edu 3368013Sbinkertn@umich.edu // 3378013Sbinkertn@umich.edu // Send out the IP Intr 3388013Sbinkertn@umich.edu // 3398017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 3408017Sbinkertn@umich.edu stq_p r14, 0(r16) // Tsunami MISC Register 3418017Sbinkertn@umich.edu#elif defined(TLASER) 3428013Sbinkertn@umich.edu stq_p r14, 0x40(r13) // Write to TLIPINTR reg 3438017Sbinkertn@umich.edu#endif 3448013Sbinkertn@umich.edu wmb // Push out the store 3458013Sbinkertn@umich.edu hw_rei 3468013Sbinkertn@umich.edu 3478013Sbinkertn@umich.edu 3488013Sbinkertn@umich.edu// cflush - PALcode for CFLUSH instruction 3498013Sbinkertn@umich.edu// 3508013Sbinkertn@umich.edu// SYS_CFLUSH 3518013Sbinkertn@umich.edu// Entry: 3528013Sbinkertn@umich.edu// R16 - contains the PFN of the page to be flushed 3538013Sbinkertn@umich.edu// 3548013Sbinkertn@umich.edu// Function: 3558013Sbinkertn@umich.edu// Flush all Dstream caches of 1 entire page 3568013Sbinkertn@umich.edu// 3578013Sbinkertn@umich.edu// 3588013Sbinkertn@umich.edu ALIGN_BLOCK 3598013Sbinkertn@umich.eduEXPORT(sys_cflush) 3608013Sbinkertn@umich.edu 3618013Sbinkertn@umich.edu// #convert pfn to addr, and clean off <63:20> 3628013Sbinkertn@umich.edu// #sll r16, <page_offset_size_bits>+<63-20>>, r12 3638013Sbinkertn@umich.edu sll r16, page_offset_size_bits+(63-20),r12 3648013Sbinkertn@umich.edu 3658013Sbinkertn@umich.edu// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16> 3668013Sbinkertn@umich.edu// # stolen from srcmax code. XXX bugnion 3678013Sbinkertn@umich.edu lda r13, 0x10(r31) // assume 16Mbytes of cache 3688013Sbinkertn@umich.edu sll r13, 20, r13 // convert to bytes 3698013Sbinkertn@umich.edu 3708013Sbinkertn@umich.edu 3718013Sbinkertn@umich.edu srl r12, 63-20, r12 // shift back to normal position 3728013Sbinkertn@umich.edu xor r12, r13, r12 // xor addr<18> 3738013Sbinkertn@umich.edu 3748013Sbinkertn@umich.edu or r31, 8192/(32*8), r13 // get count of loads 3758013Sbinkertn@umich.edu nop 3768013Sbinkertn@umich.edu 3778013Sbinkertn@umich.educflush_loop: 3788013Sbinkertn@umich.edu subq r13, 1, r13 // decr counter 3798013Sbinkertn@umich.edu mfpr r25, ev5__intid // Fetch level of interruptor 3808013Sbinkertn@umich.edu 3818013Sbinkertn@umich.edu ldq_p r31, 32*0(r12) // do a load 3828013Sbinkertn@umich.edu ldq_p r31, 32*1(r12) // do next load 3838013Sbinkertn@umich.edu 3848013Sbinkertn@umich.edu ldq_p r31, 32*2(r12) // do next load 3858013Sbinkertn@umich.edu ldq_p r31, 32*3(r12) // do next load 3868013Sbinkertn@umich.edu 3878013Sbinkertn@umich.edu ldq_p r31, 32*4(r12) // do next load 3888013Sbinkertn@umich.edu ldq_p r31, 32*5(r12) // do next load 3898013Sbinkertn@umich.edu 3908013Sbinkertn@umich.edu ldq_p r31, 32*6(r12) // do next load 3918013Sbinkertn@umich.edu ldq_p r31, 32*7(r12) // do next load 3928013Sbinkertn@umich.edu 3938013Sbinkertn@umich.edu mfpr r14, ev5__ipl // Fetch current level 3948013Sbinkertn@umich.edu lda r12, (32*8)(r12) // skip to next cache block addr 3958013Sbinkertn@umich.edu 3968013Sbinkertn@umich.edu cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl 3978013Sbinkertn@umich.edu beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt??? 3988013Sbinkertn@umich.edu 3998013Sbinkertn@umich.edu bne r13, cflush_loop // loop till done 4008013Sbinkertn@umich.edu hw_rei // back to user 4018013Sbinkertn@umich.edu 4028013Sbinkertn@umich.edu ALIGN_BRANCH 4038013Sbinkertn@umich.edu1: // Here if interrupted 4048013Sbinkertn@umich.edu mfpr r12, exc_addr 4058013Sbinkertn@umich.edu subq r12, 4, r12 // Backup PC to point to CFLUSH 4068013Sbinkertn@umich.edu 4078013Sbinkertn@umich.edu mtpr r12, exc_addr 4088013Sbinkertn@umich.edu nop 4098013Sbinkertn@umich.edu 4108013Sbinkertn@umich.edu mfpr r31, pt0 // Pad exc_addr write 4118013Sbinkertn@umich.edu hw_rei 4128013Sbinkertn@umich.edu 4138013Sbinkertn@umich.edu 4148013Sbinkertn@umich.edu ALIGN_BLOCK 4158013Sbinkertn@umich.edu// 4168013Sbinkertn@umich.edu// sys_cserve - PALcode for CSERVE instruction 4178013Sbinkertn@umich.edu// 4188013Sbinkertn@umich.edu// Function: 4198013Sbinkertn@umich.edu// Various functions for private use of console software 4208013Sbinkertn@umich.edu// 4218013Sbinkertn@umich.edu// option selector in r0 4228013Sbinkertn@umich.edu// arguments in r16.... 4238013Sbinkertn@umich.edu// 4248013Sbinkertn@umich.edu// 4258013Sbinkertn@umich.edu// r0 = 0 unknown 4268013Sbinkertn@umich.edu// 4278013Sbinkertn@umich.edu// r0 = 1 ldq_p 4288013Sbinkertn@umich.edu// r0 = 2 stq_p 4298013Sbinkertn@umich.edu// args, are as for normal STQ_P/LDQ_P in VMS PAL 4308013Sbinkertn@umich.edu// 4318013Sbinkertn@umich.edu// r0 = 3 dump_tb's 4328013Sbinkertn@umich.edu// r16 = detination PA to dump tb's to. 4338013Sbinkertn@umich.edu// 4348013Sbinkertn@umich.edu// r0<0> = 1, success 4358013Sbinkertn@umich.edu// r0<0> = 0, failure, or option not supported 4368013Sbinkertn@umich.edu// r0<63:1> = (generally 0, but may be function dependent) 4378013Sbinkertn@umich.edu// r0 - load data on ldq_p 4388013Sbinkertn@umich.edu// 4398013Sbinkertn@umich.edu// 4408013Sbinkertn@umich.eduEXPORT(sys_cserve) 4418013Sbinkertn@umich.edu 4428013Sbinkertn@umich.edu /* taken from scrmax */ 4438013Sbinkertn@umich.edu cmpeq r18, CSERVE_K_RD_IMPURE, r0 4448013Sbinkertn@umich.edu bne r0, Sys_Cserve_Rd_Impure 4458013Sbinkertn@umich.edu 4468013Sbinkertn@umich.edu cmpeq r18, CSERVE_K_JTOPAL, r0 4478013Sbinkertn@umich.edu bne r0, Sys_Cserve_Jtopal 4488013Sbinkertn@umich.edu call_pal 0 4498013Sbinkertn@umich.edu 4508013Sbinkertn@umich.edu or r31, r31, r0 4518013Sbinkertn@umich.edu hw_rei // and back we go 4528013Sbinkertn@umich.edu 4538013Sbinkertn@umich.eduSys_Cserve_Rd_Impure: 4548013Sbinkertn@umich.edu mfpr r0, pt_impure // Get base of impure scratch area. 4558013Sbinkertn@umich.edu hw_rei 4568013Sbinkertn@umich.edu 4578013Sbinkertn@umich.edu ALIGN_BRANCH 4588013Sbinkertn@umich.edu 4598013Sbinkertn@umich.eduSys_Cserve_Jtopal: 4608013Sbinkertn@umich.edu bic a0, 3, t8 // Clear out low 2 bits of address 4618013Sbinkertn@umich.edu bis t8, 1, t8 // Or in PAL mode bit 4628013Sbinkertn@umich.edu mtpr t8,exc_addr 4638013Sbinkertn@umich.edu hw_rei 4648013Sbinkertn@umich.edu 4658013Sbinkertn@umich.edu // ldq_p 4668013Sbinkertn@umich.edu ALIGN_QUAD 4678013Sbinkertn@umich.edu1: 4688013Sbinkertn@umich.edu ldq_p r0,0(r17) // get the data 4698013Sbinkertn@umich.edu nop // pad palshadow write 4708013Sbinkertn@umich.edu 4718013Sbinkertn@umich.edu hw_rei // and back we go 4728013Sbinkertn@umich.edu 4738013Sbinkertn@umich.edu 4748013Sbinkertn@umich.edu // stq_p 4758013Sbinkertn@umich.edu ALIGN_QUAD 4768013Sbinkertn@umich.edu2: 4778013Sbinkertn@umich.edu stq_p r18, 0(r17) // store the data 4788013Sbinkertn@umich.edu lda r0,17(r31) // bogus 4798013Sbinkertn@umich.edu hw_rei // and back we go 4808013Sbinkertn@umich.edu 4818013Sbinkertn@umich.edu 4828013Sbinkertn@umich.edu ALIGN_QUAD 4838013Sbinkertn@umich.educsrv_callback: 4848013Sbinkertn@umich.edu ldq r16, 0(r17) // restore r16 4858013Sbinkertn@umich.edu ldq r17, 8(r17) // restore r17 4868013Sbinkertn@umich.edu lda r0, hlt_c_callback(r31) 4878013Sbinkertn@umich.edu br r31, sys_enter_console 4888013Sbinkertn@umich.edu 4898013Sbinkertn@umich.edu 4908013Sbinkertn@umich.educsrv_identify: 4918013Sbinkertn@umich.edu mfpr r0, pal_base 4928013Sbinkertn@umich.edu ldq_p r0, 8(r0) 4938013Sbinkertn@umich.edu hw_rei 4948013Sbinkertn@umich.edu 4958013Sbinkertn@umich.edu 4968013Sbinkertn@umich.edu// dump tb's 4978013Sbinkertn@umich.edu ALIGN_QUAD 4988013Sbinkertn@umich.edu0: 4998013Sbinkertn@umich.edu // DTB PTEs - 64 entries 5008013Sbinkertn@umich.edu addq r31, 64, r0 // initialize loop counter 5018013Sbinkertn@umich.edu nop 5028013Sbinkertn@umich.edu 5038013Sbinkertn@umich.edu1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp 5048013Sbinkertn@umich.edu mfpr r12, ev5__dtb_pte // read out next pte to reg file 5058013Sbinkertn@umich.edu 5068013Sbinkertn@umich.edu subq r0, 1, r0 // decrement loop counter 5078013Sbinkertn@umich.edu nop // Pad - no Mbox instr in cycle after mfpr 5088013Sbinkertn@umich.edu 5098013Sbinkertn@umich.edu stq_p r12, 0(r16) // store out PTE 5108013Sbinkertn@umich.edu addq r16, 8 ,r16 // increment pointer 5118013Sbinkertn@umich.edu 5128013Sbinkertn@umich.edu bne r0, 1b 5138013Sbinkertn@umich.edu 5148013Sbinkertn@umich.edu ALIGN_BRANCH 5158013Sbinkertn@umich.edu // ITB PTEs - 48 entries 5168013Sbinkertn@umich.edu addq r31, 48, r0 // initialize loop counter 5178013Sbinkertn@umich.edu nop 5188013Sbinkertn@umich.edu 5198013Sbinkertn@umich.edu2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp 5208013Sbinkertn@umich.edu mfpr r12, ev5__itb_pte // read out next pte to reg file 5218013Sbinkertn@umich.edu 5228013Sbinkertn@umich.edu subq r0, 1, r0 // decrement loop counter 5238013Sbinkertn@umich.edu nop // 5248013Sbinkertn@umich.edu 5258013Sbinkertn@umich.edu stq_p r12, 0(r16) // store out PTE 5268013Sbinkertn@umich.edu addq r16, 8 ,r16 // increment pointer 5278013Sbinkertn@umich.edu 5288013Sbinkertn@umich.edu bne r0, 2b 5298013Sbinkertn@umich.edu or r31, 1, r0 // set success 5308013Sbinkertn@umich.edu 5318013Sbinkertn@umich.edu hw_rei // and back we go 5328013Sbinkertn@umich.edu 5338013Sbinkertn@umich.edu 5348013Sbinkertn@umich.edu// 5358013Sbinkertn@umich.edu// SYS_INTERRUPT - Interrupt processing code 5368013Sbinkertn@umich.edu// 5378013Sbinkertn@umich.edu// Current state: 5388013Sbinkertn@umich.edu// Stack is pushed 5398013Sbinkertn@umich.edu// ps, sp and gp are updated 5408013Sbinkertn@umich.edu// r12, r14 - available 5418013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 5428013Sbinkertn@umich.edu// r25 - ISR 5438013Sbinkertn@umich.edu// r16, r17, r18 - available 5448013Sbinkertn@umich.edu// 5458013Sbinkertn@umich.edu// 5468013Sbinkertn@umich.eduEXPORT(sys_interrupt) 5478013Sbinkertn@umich.edu cmpeq r13, 31, r12 // Check for level 31 interrupt 5488013Sbinkertn@umich.edu bne r12, sys_int_mchk_or_crd // machine check or crd 5498013Sbinkertn@umich.edu 5508013Sbinkertn@umich.edu cmpeq r13, 30, r12 // Check for level 30 interrupt 5518013Sbinkertn@umich.edu bne r12, sys_int_powerfail // powerfail 5528013Sbinkertn@umich.edu 5538013Sbinkertn@umich.edu cmpeq r13, 29, r12 // Check for level 29 interrupt 5548013Sbinkertn@umich.edu bne r12, sys_int_perf_cnt // performance counters 5558013Sbinkertn@umich.edu 5568013Sbinkertn@umich.edu cmpeq r13, 23, r12 // Check for level 23 interrupt 5578013Sbinkertn@umich.edu bne r12, sys_int_23 // IPI in Tsunami 5588013Sbinkertn@umich.edu 5598013Sbinkertn@umich.edu cmpeq r13, 22, r12 // Check for level 22 interrupt 5608013Sbinkertn@umich.edu bne r12, sys_int_22 // timer interrupt 5618013Sbinkertn@umich.edu 5628013Sbinkertn@umich.edu cmpeq r13, 21, r12 // Check for level 21 interrupt 5638013Sbinkertn@umich.edu bne r12, sys_int_21 // I/O 5648013Sbinkertn@umich.edu 5658013Sbinkertn@umich.edu cmpeq r13, 20, r12 // Check for level 20 interrupt 5668013Sbinkertn@umich.edu bne r12, sys_int_20 // system error interrupt 5678013Sbinkertn@umich.edu // (might be corrected) 5688013Sbinkertn@umich.edu 5698013Sbinkertn@umich.edu mfpr r14, exc_addr // ooops, something is wrong 5708013Sbinkertn@umich.edu br r31, pal_pal_bug_check_from_int 5718013Sbinkertn@umich.edu 5728013Sbinkertn@umich.edu 5738013Sbinkertn@umich.edu// 5748013Sbinkertn@umich.edu//sys_int_2* 5758013Sbinkertn@umich.edu// Routines to handle device interrupts at IPL 23-20. 5768013Sbinkertn@umich.edu// System specific method to ack/clear the interrupt, detect passive 5778013Sbinkertn@umich.edu// release, detect interprocessor (22), interval clock (22), corrected 5788013Sbinkertn@umich.edu// system error (20) 5798013Sbinkertn@umich.edu// 5808013Sbinkertn@umich.edu// Current state: 5818013Sbinkertn@umich.edu// Stack is pushed 5828013Sbinkertn@umich.edu// ps, sp and gp are updated 5838013Sbinkertn@umich.edu// r12, r14 - available 5848013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 5858013Sbinkertn@umich.edu// r25 - ISR 5868013Sbinkertn@umich.edu// 5878013Sbinkertn@umich.edu// On exit: 5888013Sbinkertn@umich.edu// Interrupt has been ack'd/cleared 5898013Sbinkertn@umich.edu// a0/r16 - signals IO device interrupt 5908013Sbinkertn@umich.edu// a1/r17 - contains interrupt vector 5918013Sbinkertn@umich.edu// exit to ent_int address 5928013Sbinkertn@umich.edu// 5938013Sbinkertn@umich.edu// 5948013Sbinkertn@umich.edu 5958013Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 5968013Sbinkertn@umich.edu ALIGN_BRANCH 5978013Sbinkertn@umich.edusys_int_23: 5988013Sbinkertn@umich.edu or r31,0,r16 // IPI interrupt A0 = 0 5998013Sbinkertn@umich.edu lda r12,0xf01(r31) // build up an address for the MISC register 6008013Sbinkertn@umich.edu sll r12,16,r12 6018013Sbinkertn@umich.edu lda r12,0xa000(r12) 6028013Sbinkertn@umich.edu sll r12,16,r12 6038013Sbinkertn@umich.edu lda r12,IPIR_addr(r12) 6048013Sbinkertn@umich.edu 6058013Sbinkertn@umich.edu mfpr r10, pt_whami // get CPU ID 6068013Sbinkertn@umich.edu extbl r10, 1, r10 // Isolate just whami bits 6078013Sbinkertn@umich.edu or r31,0x1,r14 // load r14 with bit to clear 6088013Sbinkertn@umich.edu sll r14,r10,r14 // left shift by CPU ID 6098013Sbinkertn@umich.edu sll r14,IPIR_shift,r14 6108013Sbinkertn@umich.edu stq_p r14, 0(r12) // clear the ipi interrupt 6118013Sbinkertn@umich.edu 6128013Sbinkertn@umich.edu br r31, pal_post_interrupt // Notify the OS 6138013Sbinkertn@umich.edu 6148013Sbinkertn@umich.edu 6158013Sbinkertn@umich.edu ALIGN_BRANCH 6168013Sbinkertn@umich.edusys_int_22: 6178013Sbinkertn@umich.edu or r31,1,r16 // a0 means it is a clock interrupt 6188013Sbinkertn@umich.edu lda r12,0xf01(r31) // build up an address for the MISC register 6198013Sbinkertn@umich.edu sll r12,16,r12 6208013Sbinkertn@umich.edu lda r12,0xa000(r12) 6218013Sbinkertn@umich.edu sll r12,16,r12 6228013Sbinkertn@umich.edu lda r12,RTC_addr(r12) 6238013Sbinkertn@umich.edu 6248013Sbinkertn@umich.edu mfpr r10, pt_whami // get CPU ID 6258013Sbinkertn@umich.edu extbl r10, 1, r10 // Isolate just whami bits 6268013Sbinkertn@umich.edu or r31,0x1,r14 // load r14 with bit to clear 6278013Sbinkertn@umich.edu sll r14,r10,r14 // left shift by CPU ID 6288013Sbinkertn@umich.edu sll r14,RTC_shift,r14 // put the bits in the right position 6298013Sbinkertn@umich.edu stq_p r14, 0(r12) // clear the rtc interrupt 6308013Sbinkertn@umich.edu 6318013Sbinkertn@umich.edu br r31, pal_post_interrupt // Tell the OS 6328013Sbinkertn@umich.edu 6338013Sbinkertn@umich.edu 6348013Sbinkertn@umich.edu ALIGN_BRANCH 6358013Sbinkertn@umich.edusys_int_20: 6368013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 6378013Sbinkertn@umich.edu srl r13, 12, r13 // shift down to examine IPL15 6388013Sbinkertn@umich.edu 6398013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 6408013Sbinkertn@umich.edu beq r14, 1f 6418013Sbinkertn@umich.edu 6428013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 6438013Sbinkertn@umich.edu lda r10, 0xa40(r10) // Get base TLILID address 6448013Sbinkertn@umich.edu 6458013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 6468013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 6478013Sbinkertn@umich.edu beq r13, 1f 6488013Sbinkertn@umich.edu 6498013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 6508013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 6518013Sbinkertn@umich.edu save_pcia_intr(1) 6528013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 6538013Sbinkertn@umich.edu 6548013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 6558013Sbinkertn@umich.edu br r31, pal_post_interrupt // 6568013Sbinkertn@umich.edu 6578013Sbinkertn@umich.edu 6588013Sbinkertn@umich.edu ALIGN_BRANCH 6598013Sbinkertn@umich.edusys_int_21: 6608013Sbinkertn@umich.edu 6618013Sbinkertn@umich.edu lda r12,0xf01(r31) // calculate DIRn address 6628013Sbinkertn@umich.edu sll r12,32,r12 6638013Sbinkertn@umich.edu ldah r13,DIR_addr(r31) 6648013Sbinkertn@umich.edu sll r13,8,r13 6658013Sbinkertn@umich.edu bis r12,r13,r12 6668013Sbinkertn@umich.edu 6678013Sbinkertn@umich.edu mfpr r13, pt_whami // get CPU ID 6688013Sbinkertn@umich.edu extbl r13, 1, r13 // Isolate just whami bits 6698013Sbinkertn@umich.edu 6708013Sbinkertn@umich.edu#ifdef BIG_TSUNAMI 6718013Sbinkertn@umich.edu sll r13,4,r13 6728013Sbinkertn@umich.edu or r12,r13,r12 6738013Sbinkertn@umich.edu#else 6748013Sbinkertn@umich.edu lda r12,0x0080(r12) 6758013Sbinkertn@umich.edu and r13,0x1,r14 // grab LSB and shift left 6 6768013Sbinkertn@umich.edu sll r14,6,r14 6778013Sbinkertn@umich.edu and r13,0x2,r10 // grabl LSB+1 and shift left 9 6788013Sbinkertn@umich.edu sll r10,9,r10 6798013Sbinkertn@umich.edu 6808013Sbinkertn@umich.edu mskbl r12,0,r12 // calculate DIRn address 6818013Sbinkertn@umich.edu lda r13,0x280(r31) 6828013Sbinkertn@umich.edu bis r12,r13,r12 6838013Sbinkertn@umich.edu or r12,r14,r12 6848013Sbinkertn@umich.edu or r12,r10,r12 6858013Sbinkertn@umich.edu#endif 6868013Sbinkertn@umich.edu 6878013Sbinkertn@umich.edu ldq_p r13, 0(r12) // read DIRn 6888013Sbinkertn@umich.edu 6898013Sbinkertn@umich.edu or r31,1,r14 // set bit 55 (ISA Interrupt) 6908013Sbinkertn@umich.edu sll r14,55,r14 6918013Sbinkertn@umich.edu 6928013Sbinkertn@umich.edu and r13, r14, r14 // check if bit 55 is set 6938013Sbinkertn@umich.edu lda r16,0x900(r31) // load offset for normal into r13 6948013Sbinkertn@umich.edu beq r14, normal_int // if not compute the vector normally 6958013Sbinkertn@umich.edu 6968013Sbinkertn@umich.edu lda r16,0x800(r31) // replace with offset for pic 6978013Sbinkertn@umich.edu lda r12,0xf01(r31) // build an addr to access PIC 6988013Sbinkertn@umich.edu sll r12,32,r12 // at f01fc000000 6998013Sbinkertn@umich.edu ldah r13,0xfc(r31) 7008013Sbinkertn@umich.edu sll r13,8,r13 7018013Sbinkertn@umich.edu bis r12,r13,r12 7028013Sbinkertn@umich.edu ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev 7038013Sbinkertn@umich.edu 7048013Sbinkertn@umich.edunormal_int: 7058013Sbinkertn@umich.edu //ctlz r13,r14 // count the number of leading zeros 7068013Sbinkertn@umich.edu // EV5 doesn't have ctlz, but we do, so lets use it 7078013Sbinkertn@umich.edu .byte 0x4e 7088013Sbinkertn@umich.edu .byte 0x06 7098013Sbinkertn@umich.edu .byte 0xed 7108013Sbinkertn@umich.edu .byte 0x73 7118013Sbinkertn@umich.edu lda r10,63(r31) 7128013Sbinkertn@umich.edu subq r10,r14,r17 // subtract from 7138013Sbinkertn@umich.edu 7148013Sbinkertn@umich.edu lda r13,0x10(r31) 7158013Sbinkertn@umich.edu mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit) 7168013Sbinkertn@umich.edu addq r17,r16,r17 7178013Sbinkertn@umich.edu 7188013Sbinkertn@umich.edu or r31,3,r16 // a0 means it is a I/O interrupt 7198013Sbinkertn@umich.edu 7208013Sbinkertn@umich.edu br r31, pal_post_interrupt 7218013Sbinkertn@umich.edu 7228013Sbinkertn@umich.edu#elif defined(TLASER) 7238013Sbinkertn@umich.edu ALIGN_BRANCH 7248013Sbinkertn@umich.edusys_int_23: 7258013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7268013Sbinkertn@umich.edu srl r13, 22, r13 // shift down to examine IPL17 7278013Sbinkertn@umich.edu 7288013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7298013Sbinkertn@umich.edu beq r14, 1f 7308013Sbinkertn@umich.edu 7318013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7328013Sbinkertn@umich.edu lda r10, 0xac0(r10) // Get base TLILID address 7338013Sbinkertn@umich.edu 7348013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7358013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7368013Sbinkertn@umich.edu 7378013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7388013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7398013Sbinkertn@umich.edu 7408013Sbinkertn@umich.edu 7418013Sbinkertn@umich.edu ALIGN_BRANCH 7428013Sbinkertn@umich.edusys_int_22: 7438013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7448013Sbinkertn@umich.edu srl r13, 6, r14 // check the Intim bit 7458013Sbinkertn@umich.edu 7468013Sbinkertn@umich.edu blbs r14, tlep_intim // go service Intim 7478013Sbinkertn@umich.edu srl r13, 5, r14 // check the IP Int bit 7488013Sbinkertn@umich.edu 7498013Sbinkertn@umich.edu blbs r14, tlep_ipint // go service IP Int 7508013Sbinkertn@umich.edu srl r13, 17, r13 // shift down to examine IPL16 7518013Sbinkertn@umich.edu 7528013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7538013Sbinkertn@umich.edu beq r14, 1f 7548013Sbinkertn@umich.edu 7558013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7568013Sbinkertn@umich.edu lda r10, 0xa80(r10) // Get base TLILID address 7578013Sbinkertn@umich.edu 7588013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7598013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7608013Sbinkertn@umich.edu beq r13, 1f 7618013Sbinkertn@umich.edu 7628013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 7638013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 7648013Sbinkertn@umich.edu save_pcia_intr(2) 7658013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 7668013Sbinkertn@umich.edu 7678013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7688013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7698013Sbinkertn@umich.edu 7708013Sbinkertn@umich.edu 7718013Sbinkertn@umich.edu ALIGN_BRANCH 7728013Sbinkertn@umich.edusys_int_21: 7738013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7748013Sbinkertn@umich.edu srl r13, 12, r13 // shift down to examine IPL15 7758013Sbinkertn@umich.edu 7768013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7778013Sbinkertn@umich.edu beq r14, 1f 7788013Sbinkertn@umich.edu 7798013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7808013Sbinkertn@umich.edu lda r10, 0xa40(r10) // Get base TLILID address 7818013Sbinkertn@umich.edu 7828013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7838013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7848013Sbinkertn@umich.edu beq r13, 1f 7858013Sbinkertn@umich.edu 7868013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 7878013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 7888013Sbinkertn@umich.edu save_pcia_intr(1) 7898013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 7908013Sbinkertn@umich.edu 7918013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7928013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7938013Sbinkertn@umich.edu 7948013Sbinkertn@umich.edu 7958013Sbinkertn@umich.edu ALIGN_BRANCH 7968013Sbinkertn@umich.edusys_int_20: 7978013Sbinkertn@umich.edu lda r13, 1(r31) // Duart0 bit 7988013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit 7998013Sbinkertn@umich.edu 8008013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 8018013Sbinkertn@umich.edu blbs r13, tlep_uart0 // go service UART int 8028013Sbinkertn@umich.edu 8038013Sbinkertn@umich.edu srl r13, 7, r13 // shift down to examine IPL14 8048013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 8058013Sbinkertn@umich.edu 8068013Sbinkertn@umich.edu beq r14, tlep_ecc // Branch if not IPL14 8078013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 8088013Sbinkertn@umich.edu 8098013Sbinkertn@umich.edu lda r10, 0xa00(r10) // Get base TLILID0 address 8108013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 8118013Sbinkertn@umich.edu 8128013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 8138013Sbinkertn@umich.edu beq r13, 1f 8148013Sbinkertn@umich.edu 8158013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 8168013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 8178013Sbinkertn@umich.edu save_pcia_intr(0) 8188013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 8198013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 8208013Sbinkertn@umich.edu br r31, pal_post_interrupt // 8218013Sbinkertn@umich.edu 8228013Sbinkertn@umich.edu 8238013Sbinkertn@umich.edu ALIGN_BRANCH 8248013Sbinkertn@umich.edutlep_intim: 8258013Sbinkertn@umich.edu lda r13, 0xffb(r31) // get upper GBUS address bits 8268013Sbinkertn@umich.edu sll r13, 28, r13 // shift up to top 8278013Sbinkertn@umich.edu 8288013Sbinkertn@umich.edu lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset) 8298013Sbinkertn@umich.edu ldq_p r13, 0(r13) // read CSRC 8308013Sbinkertn@umich.edu 8318013Sbinkertn@umich.edu lda r13, 0x40(r31) // load Intim bit 8328013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit 8338013Sbinkertn@umich.edu 8348013Sbinkertn@umich.edu lda r16, osfint_c_clk(r31) // passive release 8358013Sbinkertn@umich.edu br r31, pal_post_interrupt // Build the stack frame 8368013Sbinkertn@umich.edu 8378013Sbinkertn@umich.edu 8388013Sbinkertn@umich.edu ALIGN_BRANCH 8398013Sbinkertn@umich.edutlep_ipint: 8408013Sbinkertn@umich.edu lda r13, 0x20(r31) // load IP Int bit 8418013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit 8428013Sbinkertn@umich.edu 8438013Sbinkertn@umich.edu lda r16, osfint_c_ip(r31) // passive release 8448013Sbinkertn@umich.edu br r31, pal_post_interrupt // Build the stack frame 8458013Sbinkertn@umich.edu 8468013Sbinkertn@umich.edu 8478013Sbinkertn@umich.edu ALIGN_BRANCH 8488013Sbinkertn@umich.edutlep_uart0: 8498013Sbinkertn@umich.edu lda r13, 0xffa(r31) // get upper GBUS address bits 8508013Sbinkertn@umich.edu sll r13, 28, r13 // shift up to top 8518013Sbinkertn@umich.edu 8528013Sbinkertn@umich.edu ldl_p r14, 0x80(r13) // zero pointer register 8538013Sbinkertn@umich.edu lda r14, 3(r31) // index to RR3 8548013Sbinkertn@umich.edu 8558013Sbinkertn@umich.edu stl_p r14, 0x80(r13) // write pointer register 8568013Sbinkertn@umich.edu mb 8578013Sbinkertn@umich.edu 8588013Sbinkertn@umich.edu mb 8598013Sbinkertn@umich.edu ldl_p r14, 0x80(r13) // read RR3 8608013Sbinkertn@umich.edu 8618013Sbinkertn@umich.edu srl r14, 5, r10 // is it Channel A RX? 8628013Sbinkertn@umich.edu blbs r10, uart0_rx 8638013Sbinkertn@umich.edu 8648013Sbinkertn@umich.edu srl r14, 4, r10 // is it Channel A TX? 8658013Sbinkertn@umich.edu blbs r10, uart0_tx 8668013Sbinkertn@umich.edu 8678013Sbinkertn@umich.edu srl r14, 2, r10 // is it Channel B RX? 8688013Sbinkertn@umich.edu blbs r10, uart1_rx 8698013Sbinkertn@umich.edu 8708013Sbinkertn@umich.edu srl r14, 1, r10 // is it Channel B TX? 8718013Sbinkertn@umich.edu blbs r10, uart1_tx 8728013Sbinkertn@umich.edu 8738013Sbinkertn@umich.edu lda r8, 0(r31) // passive release 8748013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8758013Sbinkertn@umich.edu 8768013Sbinkertn@umich.edu 8778013Sbinkertn@umich.edu ALIGN_BRANCH 8788013Sbinkertn@umich.eduuart0_rx: 8798013Sbinkertn@umich.edu lda r8, 0x680(r31) // UART0 RX vector 8808013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8818013Sbinkertn@umich.edu 8828013Sbinkertn@umich.edu 8838013Sbinkertn@umich.edu ALIGN_BRANCH 8848013Sbinkertn@umich.eduuart0_tx: 8858013Sbinkertn@umich.edu lda r14, 0x28(r31) // Reset TX Int Pending code 8868013Sbinkertn@umich.edu mb 8878013Sbinkertn@umich.edu stl_p r14, 0x80(r13) // write Channel A WR0 8888013Sbinkertn@umich.edu mb 8898013Sbinkertn@umich.edu 8908013Sbinkertn@umich.edu lda r8, 0x6c0(r31) // UART0 TX vector 8918013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8928013Sbinkertn@umich.edu 8938013Sbinkertn@umich.edu 8948013Sbinkertn@umich.edu ALIGN_BRANCH 8958013Sbinkertn@umich.eduuart1_rx: 8968013Sbinkertn@umich.edu lda r8, 0x690(r31) // UART1 RX vector 8978013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8988013Sbinkertn@umich.edu 8998013Sbinkertn@umich.edu 9008013Sbinkertn@umich.edu ALIGN_BRANCH 9018013Sbinkertn@umich.eduuart1_tx: 9028013Sbinkertn@umich.edu lda r14, 0x28(r31) // Reset TX Int Pending code 9038013Sbinkertn@umich.edu stl_p r14, 0(r13) // write Channel B WR0 9048013Sbinkertn@umich.edu 9058013Sbinkertn@umich.edu lda r8, 0x6d0(r31) // UART1 TX vector 9068013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 9078013Sbinkertn@umich.edu 9088013Sbinkertn@umich.edu 9098013Sbinkertn@umich.edu ALIGN_BRANCH 9108013Sbinkertn@umich.educlear_duart0_int: 9118013Sbinkertn@umich.edu lda r13, 1(r31) // load duart0 bit 9128013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit 9138013Sbinkertn@umich.edu 9148013Sbinkertn@umich.edu beq r8, 1f 9158013Sbinkertn@umich.edu or r8, r31, r13 // move vector to r13 9168013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // Build the stack frame 9178013Sbinkertn@umich.edu1: nop 9188013Sbinkertn@umich.edu nop 9198013Sbinkertn@umich.edu hw_rei 9208013Sbinkertn@umich.edu// lda r16, osfint_c_passrel(r31) // passive release 9218013Sbinkertn@umich.edu// br r31, pal_post_interrupt // 9228013Sbinkertn@umich.edu 9238013Sbinkertn@umich.edu 9248013Sbinkertn@umich.edu ALIGN_BRANCH 9258013Sbinkertn@umich.edutlep_ecc: 9268013Sbinkertn@umich.edu mfpr r14, pt_whami // get our node id 9278013Sbinkertn@umich.edu extbl r14, 1, r14 // shift to bit 0 9288013Sbinkertn@umich.edu 9298013Sbinkertn@umich.edu srl r14, 1, r14 // shift off cpu number 9308013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) // compute our nodespace address 9318013Sbinkertn@umich.edu 9328013Sbinkertn@umich.edu ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset 9338013Sbinkertn@umich.edu srl r13, 17, r13 // shift down the CWDE/CRDE bits 9348013Sbinkertn@umich.edu 9358013Sbinkertn@umich.edu and r13, 3, r13 // mask the CWDE/CRDE bits 9368013Sbinkertn@umich.edu beq r13, 1f 9378013Sbinkertn@umich.edu 9388013Sbinkertn@umich.edu ornot r31, r31, r12 // set flag 9398013Sbinkertn@umich.edu lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code 9408013Sbinkertn@umich.edu br r31, sys_merge_sys_corr // jump to CRD logout frame code 9418013Sbinkertn@umich.edu 9428013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 9438013Sbinkertn@umich.edu 9448013Sbinkertn@umich.edu#endif // if TSUNAMI || BIG_TSUNAMI elif TLASER 9458013Sbinkertn@umich.edu 9468013Sbinkertn@umich.edu ALIGN_BRANCH 9478013Sbinkertn@umich.edupal_post_dev_interrupt: 9488013Sbinkertn@umich.edu or r13, r31, r17 // move vector to a1 9498013Sbinkertn@umich.edu or r31, osfint_c_dev, r16 // a0 signals IO device interrupt 9508013Sbinkertn@umich.edu 9518013Sbinkertn@umich.edupal_post_interrupt: 9528013Sbinkertn@umich.edu mfpr r12, pt_entint 9538013Sbinkertn@umich.edu 9548013Sbinkertn@umich.edu mtpr r12, exc_addr 9558013Sbinkertn@umich.edu 9568013Sbinkertn@umich.edu nop 9578013Sbinkertn@umich.edu nop 9588013Sbinkertn@umich.edu 9598013Sbinkertn@umich.edu hw_rei_spe 9608013Sbinkertn@umich.edu 9618013Sbinkertn@umich.edu 9628013Sbinkertn@umich.edu// 9638013Sbinkertn@umich.edu// sys_passive_release 9648013Sbinkertn@umich.edu// Just pretend the interrupt never occurred. 9658013Sbinkertn@umich.edu// 9668013Sbinkertn@umich.edu 9678013Sbinkertn@umich.eduEXPORT(sys_passive_release) 9688013Sbinkertn@umich.edu mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps 9698013Sbinkertn@umich.edu nop 9708013Sbinkertn@umich.edu 9718013Sbinkertn@umich.edu mfpr r31, pt0 // Pad write to dtb_cm 9728013Sbinkertn@umich.edu hw_rei 9738013Sbinkertn@umich.edu 9748013Sbinkertn@umich.edu// 9758013Sbinkertn@umich.edu// sys_int_powerfail 9768013Sbinkertn@umich.edu// A powerfail interrupt has been detected. The stack has been pushed. 9778013Sbinkertn@umich.edu// IPL and PS are updated as well. 9788013Sbinkertn@umich.edu// 9798013Sbinkertn@umich.edu// I'm not sure what to do here, I'm treating it as an IO device interrupt 9808013Sbinkertn@umich.edu// 9818013Sbinkertn@umich.edu// 9828013Sbinkertn@umich.edu 9838013Sbinkertn@umich.edu ALIGN_BLOCK 9848013Sbinkertn@umich.edusys_int_powerfail: 9858013Sbinkertn@umich.edu lda r12, 0xffc4(r31) // get GBUS_MISCR address bits 9868013Sbinkertn@umich.edu sll r12, 24, r12 // shift to proper position 9878013Sbinkertn@umich.edu ldq_p r12, 0(r12) // read GBUS_MISCR 9888013Sbinkertn@umich.edu srl r12, 5, r12 // isolate bit <5> 9898013Sbinkertn@umich.edu blbc r12, 1f // if clear, no missed mchk 9908013Sbinkertn@umich.edu 9918013Sbinkertn@umich.edu // Missed a CFAIL mchk 9928013Sbinkertn@umich.edu lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits 9938013Sbinkertn@umich.edu sll r13, 24, r13 // shift to proper position 9948013Sbinkertn@umich.edu lda r14, 0x40(r31) // get bit <6> mask 9958013Sbinkertn@umich.edu ldq_p r12, 0(r13) // read GBUS$SERNUM 9968013Sbinkertn@umich.edu or r12, r14, r14 // set bit <6> 9978013Sbinkertn@umich.edu stq_p r14, 0(r13) // clear GBUS$SERNUM<6> 9988013Sbinkertn@umich.edu mb 9998013Sbinkertn@umich.edu mb 10008013Sbinkertn@umich.edu 10018013Sbinkertn@umich.edu1: br r31, sys_int_mchk // do a machine check 10028013Sbinkertn@umich.edu 10038013Sbinkertn@umich.edu lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector 10048013Sbinkertn@umich.edu mfpr r25, pt_entint 10058013Sbinkertn@umich.edu 10068013Sbinkertn@umich.edu lda r16, osfint_c_dev(r31) // a0 to device code 10078013Sbinkertn@umich.edu mtpr r25, exc_addr 10088013Sbinkertn@umich.edu 10098013Sbinkertn@umich.edu nop // pad exc_addr write 10108013Sbinkertn@umich.edu nop 10118013Sbinkertn@umich.edu 10128013Sbinkertn@umich.edu hw_rei_spe 10138013Sbinkertn@umich.edu 10148013Sbinkertn@umich.edu// 10158013Sbinkertn@umich.edu// sys_halt_interrupt 10168013Sbinkertn@umich.edu// A halt interrupt has been detected. Pass control to the console. 10178013Sbinkertn@umich.edu// 10188013Sbinkertn@umich.edu// 10198013Sbinkertn@umich.edu// 10208013Sbinkertn@umich.edu EXPORT(sys_halt_interrupt) 10218013Sbinkertn@umich.edu 10228013Sbinkertn@umich.edu ldah r13, 0x1800(r31) // load Halt/^PHalt bits 10238013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits 10248013Sbinkertn@umich.edu 10258013Sbinkertn@umich.edu mtpr r11, dtb_cm // Restore Mbox current mode 10268013Sbinkertn@umich.edu nop 10278013Sbinkertn@umich.edu nop 10288013Sbinkertn@umich.edu mtpr r0, pt0 10298013Sbinkertn@umich.edu lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt 10308013Sbinkertn@umich.edu br r31, sys_enter_console // enter the console 10318013Sbinkertn@umich.edu 10328013Sbinkertn@umich.edu 10338013Sbinkertn@umich.edu 10348013Sbinkertn@umich.edu// 10358013Sbinkertn@umich.edu// sys_int_mchk_or_crd 10368013Sbinkertn@umich.edu// 10378013Sbinkertn@umich.edu// Current state: 10388013Sbinkertn@umich.edu// Stack is pushed 10398013Sbinkertn@umich.edu// ps, sp and gp are updated 10408013Sbinkertn@umich.edu// r12 10418013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 10428013Sbinkertn@umich.edu// r14 - exc_addr 10438013Sbinkertn@umich.edu// r25 - ISR 10448013Sbinkertn@umich.edu// r16, r17, r18 - available 10458013Sbinkertn@umich.edu// 10468013Sbinkertn@umich.edu// 10478013Sbinkertn@umich.edu ALIGN_BLOCK 10488013Sbinkertn@umich.edusys_int_mchk_or_crd: 10498013Sbinkertn@umich.edu srl r25, isr_v_mck, r12 10508013Sbinkertn@umich.edu blbs r12, sys_int_mchk 10518013Sbinkertn@umich.edu // 10528013Sbinkertn@umich.edu // Not a Machine check interrupt, so must be an Internal CRD interrupt 10538013Sbinkertn@umich.edu // 10548013Sbinkertn@umich.edu 10558013Sbinkertn@umich.edu mb //Clear out Cbox prior to reading IPRs 10568013Sbinkertn@umich.edu srl r25, isr_v_crd, r13 //Check for CRD 10578013Sbinkertn@umich.edu blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!! 10588013Sbinkertn@umich.edu 10598013Sbinkertn@umich.edu lda r9, 1(r31) 10608013Sbinkertn@umich.edu sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd 10618013Sbinkertn@umich.edu mtpr r9, ev5__hwint_clr // ack the crd interrupt 10628013Sbinkertn@umich.edu 10638013Sbinkertn@umich.edu or r31, r31, r12 // clear flag 10648013Sbinkertn@umich.edu lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code 10658013Sbinkertn@umich.edu 10668013Sbinkertn@umich.edusys_merge_sys_corr: 10678013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 10688013Sbinkertn@umich.edu mtpr r0, pt0 // save r0 for scratch 10698013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 10708013Sbinkertn@umich.edu mtpr r1, pt1 // save r0 for scratch 10718013Sbinkertn@umich.edu 10728013Sbinkertn@umich.edu ldq_p r0, ei_addr(r14) // EI_ADDR IPR 10738013Sbinkertn@umich.edu ldq_p r10, fill_syn(r14) // FILL_SYN IPR 10748013Sbinkertn@umich.edu bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub 10758013Sbinkertn@umich.edu 10768013Sbinkertn@umich.edu blbs r12, 1f // no scrubbing for IRQ0 case 10778013Sbinkertn@umich.edu// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1 10788013Sbinkertn@umich.edu bsr r13, sys_crd_scrub_mem // and go scrub 10798013Sbinkertn@umich.edu 10808013Sbinkertn@umich.edu // ld/st pair in scrub routine will have finished due 10818013Sbinkertn@umich.edu // to ibox stall of stx_c. Don't need another mb. 10828013Sbinkertn@umich.edu ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 10838013Sbinkertn@umich.edu or r8, r31, r12 // Must only be executed once in this flow, and must 10848013Sbinkertn@umich.edu br r31, 2f // be after the scrub routine. 10858013Sbinkertn@umich.edu 10868013Sbinkertn@umich.edu1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 10878013Sbinkertn@umich.edu // For IRQ0 CRD case only - meaningless data. 10888013Sbinkertn@umich.edu 10898013Sbinkertn@umich.edu2: mfpr r13, pt_mces // Get MCES 10908013Sbinkertn@umich.edu srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES 10918013Sbinkertn@umich.edu blbc r14, 6f // branch if 630 10928013Sbinkertn@umich.edu srl r13, mces_v_dsc, r14 // check if 620 reporting disabled 10938013Sbinkertn@umich.edu blbc r14, 5f // branch if enabled 10948013Sbinkertn@umich.edu or r13, r31, r14 // don't set SCE if disabled 10958013Sbinkertn@umich.edu br r31, 8f // continue 10968013Sbinkertn@umich.edu5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit 10978013Sbinkertn@umich.edu br r31, 8f 10988013Sbinkertn@umich.edu 10998013Sbinkertn@umich.edu6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled 11008013Sbinkertn@umich.edu blbc r14, 7f // branch if enabled 11018013Sbinkertn@umich.edu or r13, r31, r14 // don't set PCE if disabled 11028013Sbinkertn@umich.edu br r31, 8f // continue 11038013Sbinkertn@umich.edu7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit 11048013Sbinkertn@umich.edu 11058013Sbinkertn@umich.edu // Setup SCB if dpc is not set 11068013Sbinkertn@umich.edu8: mtpr r14, pt_mces // Store updated MCES 11078013Sbinkertn@umich.edu srl r13, mces_v_sce, r1 // Get SCE 11088013Sbinkertn@umich.edu srl r13, mces_v_pce, r14 // Get PCE 11098013Sbinkertn@umich.edu or r1, r14, r1 // SCE OR PCE, since they share 11108013Sbinkertn@umich.edu // the CRD logout frame 11118013Sbinkertn@umich.edu // Get base of the logout area. 11128013Sbinkertn@umich.edu GET_IMPURE(r14) // addr of per-cpu impure area 11138013Sbinkertn@umich.edu GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14) 11148013Sbinkertn@umich.edu 11158013Sbinkertn@umich.edu blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame 11168013Sbinkertn@umich.edu 11178013Sbinkertn@umich.edu // Set the 2nd error flag in the logout area: 11188013Sbinkertn@umich.edu 11198013Sbinkertn@umich.edu lda r1, 3(r31) // Set retry and 2nd error flags 11208013Sbinkertn@umich.edu sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword 11218013Sbinkertn@umich.edu stl_p r1, mchk_crd_flag+4(r14) // store flag longword 11228013Sbinkertn@umich.edu br sys_crd_ack 11238013Sbinkertn@umich.edu 11248013Sbinkertn@umich.edusys_crd_write_logout_frame: 11258013Sbinkertn@umich.edu // should only be here if neither the pce or sce bits are set 11268013Sbinkertn@umich.edu 11278013Sbinkertn@umich.edu // 11288013Sbinkertn@umich.edu // Write the mchk code to the logout area 11298013Sbinkertn@umich.edu // 11308013Sbinkertn@umich.edu stq_p r9, mchk_crd_mchk_code(r14) 11318013Sbinkertn@umich.edu 11328013Sbinkertn@umich.edu 11338013Sbinkertn@umich.edu // 11348013Sbinkertn@umich.edu // Write the first 2 quadwords of the logout area: 11358013Sbinkertn@umich.edu // 11368013Sbinkertn@umich.edu lda r1, 1(r31) // Set retry flag 11378013Sbinkertn@umich.edu sll r1, 63, r9 // Move retry flag to bit 63 11388013Sbinkertn@umich.edu lda r1, mchk_crd_size(r9) // Combine retry flag and frame size 11398013Sbinkertn@umich.edu stq_p r1, mchk_crd_flag(r14) // store flag/frame size 11408013Sbinkertn@umich.edu 11418013Sbinkertn@umich.edu // 11428013Sbinkertn@umich.edu // Write error IPRs already fetched to the logout area 11438013Sbinkertn@umich.edu // 11448013Sbinkertn@umich.edu stq_p r0, mchk_crd_ei_addr(r14) 11458013Sbinkertn@umich.edu stq_p r10, mchk_crd_fill_syn(r14) 11468013Sbinkertn@umich.edu stq_p r8, mchk_crd_ei_stat(r14) 11478013Sbinkertn@umich.edu stq_p r25, mchk_crd_isr(r14) 11488013Sbinkertn@umich.edu // 11498013Sbinkertn@umich.edu // Log system specific info here 11508013Sbinkertn@umich.edu // 11518013Sbinkertn@umich.educrd_storeTLEP_: 11528013Sbinkertn@umich.edu lda r1, 0xffc4(r31) // Get GBUS$MISCR address 11538013Sbinkertn@umich.edu sll r1, 24, r1 11548013Sbinkertn@umich.edu ldq_p r1, 0(r1) // Read GBUS$MISCR 11558013Sbinkertn@umich.edu sll r1, 16, r1 // shift up to proper field 11568013Sbinkertn@umich.edu mfpr r10, pt_whami // get our node id 11578013Sbinkertn@umich.edu extbl r10, 1, r10 // shift to bit 0 11588013Sbinkertn@umich.edu or r1, r10, r1 // merge MISCR and WHAMI 11598013Sbinkertn@umich.edu stl_p r1, mchk_crd_whami(r14) // write to crd logout area 11608013Sbinkertn@umich.edu srl r10, 1, r10 // shift off cpu number 11618013Sbinkertn@umich.edu 11628013Sbinkertn@umich.edu Get_TLSB_Node_Address(r10,r0) // compute our nodespace address 11638013Sbinkertn@umich.edu 11648013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb(tldev) 11658013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlber) 11668013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr0) 11678013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr1) 11688013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr2) 11698013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr3) 11708013Sbinkertn@umich.edu 11718013Sbinkertn@umich.edusys_crd_ack: 11728013Sbinkertn@umich.edu mfpr r0, pt0 // restore r0 11738013Sbinkertn@umich.edu mfpr r1, pt1 // restore r1 11748013Sbinkertn@umich.edu 11758013Sbinkertn@umich.edu srl r12, ei_stat_v_ei_es, r12 11768013Sbinkertn@umich.edu blbc r12, 5f 11778013Sbinkertn@umich.edu srl r13, mces_v_dsc, r10 // logging enabled? 11788013Sbinkertn@umich.edu br r31, 6f 11798013Sbinkertn@umich.edu5: srl r13, mces_v_dpc, r10 // logging enabled? 11808013Sbinkertn@umich.edu6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it 11818013Sbinkertn@umich.edu 11828013Sbinkertn@umich.edu // logging not enabled 11838013Sbinkertn@umich.edu // Get base of the logout area. 11848013Sbinkertn@umich.edu GET_IMPURE(r13) // addr of per-cpu impure area 11858013Sbinkertn@umich.edu GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13) 11868013Sbinkertn@umich.edu ldl_p r10, mchk_crd_rsvd(r13) // bump counter 11878013Sbinkertn@umich.edu addl r10, 1, r10 11888013Sbinkertn@umich.edu stl_p r10, mchk_crd_rsvd(r13) 11898013Sbinkertn@umich.edu mb 11908013Sbinkertn@umich.edu br r31, sys_crd_dismiss_interrupt // just return 11918013Sbinkertn@umich.edu 11928013Sbinkertn@umich.edu // 11938013Sbinkertn@umich.edu // The stack is pushed. Load up a0,a1,a2 and vector via entInt 11948013Sbinkertn@umich.edu // 11958013Sbinkertn@umich.edu // 11968013Sbinkertn@umich.edu 11978013Sbinkertn@umich.edu ALIGN_BRANCH 11988013Sbinkertn@umich.edusys_crd_post_interrupt: 11998013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 12008013Sbinkertn@umich.edu lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector 12018013Sbinkertn@umich.edu 12028013Sbinkertn@umich.edu blbc r12, 1f 12038013Sbinkertn@umich.edu lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector 12048013Sbinkertn@umich.edu 12058013Sbinkertn@umich.edu1: subq r31, 1, r18 // get a -1 12068013Sbinkertn@umich.edu mfpr r25, pt_entInt 12078013Sbinkertn@umich.edu 12088013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 12098013Sbinkertn@umich.edu mtpr r25, exc_addr // load interrupt vector 12108013Sbinkertn@umich.edu 12118013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 12128013Sbinkertn@umich.edu or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 12138013Sbinkertn@umich.edu 12148013Sbinkertn@umich.edu hw_rei_spe // done 12158013Sbinkertn@umich.edu 12168013Sbinkertn@umich.edu 12178013Sbinkertn@umich.edu // 12188013Sbinkertn@umich.edu // The stack is pushed. Need to back out of it all. 12198013Sbinkertn@umich.edu // 12208013Sbinkertn@umich.edu 12218013Sbinkertn@umich.edusys_crd_dismiss_interrupt: 12228013Sbinkertn@umich.edu br r31, Call_Pal_Rti 12238013Sbinkertn@umich.edu 12248013Sbinkertn@umich.edu 12258013Sbinkertn@umich.edu// sys_crd_scrub_mem 12268013Sbinkertn@umich.edu// 12278013Sbinkertn@umich.edu// r0 = addr of cache block 12288013Sbinkertn@umich.edu// 12298013Sbinkertn@umich.edu ALIGN_BLOCK // align for branch target 12308013Sbinkertn@umich.edusys_crd_scrub_mem: 12318013Sbinkertn@umich.edu // now find error in memory, and attempt to scrub that cache block 12328013Sbinkertn@umich.edu // This routine just scrubs the failing octaword 12338013Sbinkertn@umich.edu // Only need to "touch" one quadword per octaword to accomplish the scrub 12348013Sbinkertn@umich.edu srl r0, 39, r8 // get high bit of bad pa 12358013Sbinkertn@umich.edu blbs r8, 1f // don't attempt fixup on IO space addrs 12368013Sbinkertn@umich.edu nop // needed to align the ldq_pl to octaword boundary 12378013Sbinkertn@umich.edu nop // " 12388013Sbinkertn@umich.edu 12398013Sbinkertn@umich.edu ldq_p r8, 0(r0) // attempt to read the bad memory 12408013Sbinkertn@umich.edu // location 12418013Sbinkertn@umich.edu // (Note bits 63:40,3:0 of ei_addr 12428013Sbinkertn@umich.edu // are set to 1, but as long as 12438013Sbinkertn@umich.edu // we are doing a phys ref, should 12448013Sbinkertn@umich.edu // be ok) 12458013Sbinkertn@umich.edu nop // Needed to keep the Ibox from swapping the ldq_p into E1 12468013Sbinkertn@umich.edu 12478013Sbinkertn@umich.edu stq_p r8, 0(r0) // Store it back if it is still there. 12488013Sbinkertn@umich.edu // If store fails, location already 12498013Sbinkertn@umich.edu // scrubbed by someone else 12508013Sbinkertn@umich.edu 12518013Sbinkertn@umich.edu nop // needed to align the ldq_p to octaword boundary 12528013Sbinkertn@umich.edu 12538013Sbinkertn@umich.edu lda r8, 0x20(r31) // flip bit 5 to touch next hexaword 12548013Sbinkertn@umich.edu xor r8, r0, r0 12558013Sbinkertn@umich.edu nop // needed to align the ldq_p to octaword boundary 12568013Sbinkertn@umich.edu nop // " 12578013Sbinkertn@umich.edu 12588013Sbinkertn@umich.edu ldq_p r8, 0(r0) // attempt to read the bad memory 12598013Sbinkertn@umich.edu // location 12608013Sbinkertn@umich.edu // (Note bits 63:40,3:0 of ei_addr 12618013Sbinkertn@umich.edu // are set to 1, but as long as 12628013Sbinkertn@umich.edu // we are doing a phys ref, should 12638013Sbinkertn@umich.edu // be ok) 12648013Sbinkertn@umich.edu nop // Needed to keep the Ibox from swapping the ldq_p into E1 12658013Sbinkertn@umich.edu 12668013Sbinkertn@umich.edu stq_p r8, 0(r0) // Store it back if it is still there. 12678013Sbinkertn@umich.edu // If store fails, location already 12688013Sbinkertn@umich.edu // scrubbed by someone else 12698013Sbinkertn@umich.edu 12708013Sbinkertn@umich.edu lda r8, 0x20(r31) // restore r0 to original address 12718013Sbinkertn@umich.edu xor r8, r0, r0 12728013Sbinkertn@umich.edu 12738013Sbinkertn@umich.edu //at this point, ei_stat could be locked due to a new corr error on the ld, 12748013Sbinkertn@umich.edu //so read ei_stat to unlock AFTER this routine. 12758013Sbinkertn@umich.edu 12768013Sbinkertn@umich.edu// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1 12778013Sbinkertn@umich.edu1: ret r31, (r13) // and back we go 12788013Sbinkertn@umich.edu 12798013Sbinkertn@umich.edu 12808013Sbinkertn@umich.edu// 12818013Sbinkertn@umich.edu// sys_int_mchk - MCHK Interrupt code 12828013Sbinkertn@umich.edu// 12838013Sbinkertn@umich.edu// Machine check interrupt from the system. Setup and join the 12848013Sbinkertn@umich.edu// regular machine check flow. 12858013Sbinkertn@umich.edu// On exit: 12868013Sbinkertn@umich.edu// pt0 - saved r0 12878013Sbinkertn@umich.edu// pt1 - saved r1 12888013Sbinkertn@umich.edu// pt4 - saved r4 12898013Sbinkertn@umich.edu// pt5 - saved r5 12908013Sbinkertn@umich.edu// pt6 - saved r6 12918013Sbinkertn@umich.edu// pt10 - saved exc_addr 12928013Sbinkertn@umich.edu// pt_misc<47:32> - mchk code 12938013Sbinkertn@umich.edu// pt_misc<31:16> - scb vector 12948013Sbinkertn@umich.edu// r14 - base of Cbox IPRs in IO space 12958013Sbinkertn@umich.edu// MCES<mchk> is set 12968013Sbinkertn@umich.edu// 12978013Sbinkertn@umich.edu ALIGN_BLOCK 12988013Sbinkertn@umich.edusys_int_mchk: 12998013Sbinkertn@umich.edu lda r14, mchk_c_sys_hrd_error(r31) 13008013Sbinkertn@umich.edu mfpr r12, exc_addr 13018013Sbinkertn@umich.edu 13028013Sbinkertn@umich.edu addq r14, 1, r14 // Flag as interrupt 13038013Sbinkertn@umich.edu nop 13048013Sbinkertn@umich.edu 13058013Sbinkertn@umich.edu sll r14, 32, r14 // Move mchk code to position 13068013Sbinkertn@umich.edu mtpr r12, pt10 // Stash exc_addr 13078013Sbinkertn@umich.edu 13088013Sbinkertn@umich.edu mfpr r12, pt_misc // Get MCES and scratch 13098013Sbinkertn@umich.edu mtpr r0, pt0 // Stash for scratch 13108013Sbinkertn@umich.edu 13118013Sbinkertn@umich.edu zap r12, 0x3c, r12 // Clear scratch 13128013Sbinkertn@umich.edu blbs r12, sys_double_machine_check // MCHK halt if double machine check 13138013Sbinkertn@umich.edu 13148013Sbinkertn@umich.edu or r12, r14, r12 // Combine mchk code 13158013Sbinkertn@umich.edu lda r14, scb_v_sysmchk(r31) // Get SCB vector 13168013Sbinkertn@umich.edu 13178013Sbinkertn@umich.edu sll r14, 16, r14 // Move SCBv to position 13188013Sbinkertn@umich.edu or r12, r14, r14 // Combine SCBv 13198013Sbinkertn@umich.edu 13208013Sbinkertn@umich.edu bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit 13218013Sbinkertn@umich.edu mtpr r14, pt_misc // Save mchk code!scbv!whami!mces 13228013Sbinkertn@umich.edu 13238013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 13248013Sbinkertn@umich.edu mtpr r1, pt1 // Stash for scratch 13258013Sbinkertn@umich.edu 13268013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 13278013Sbinkertn@umich.edu mtpr r4, pt4 13288013Sbinkertn@umich.edu 13298013Sbinkertn@umich.edu mtpr r5, pt5 13308013Sbinkertn@umich.edu 13318013Sbinkertn@umich.edu mtpr r6, pt6 13328013Sbinkertn@umich.edu br r31, sys_mchk_collect_iprs // Join common machine check flow 13338013Sbinkertn@umich.edu 13348013Sbinkertn@umich.edu 13358013Sbinkertn@umich.edu// 13368013Sbinkertn@umich.edu// sys_int_perf_cnt - Performance counter interrupt code 13378013Sbinkertn@umich.edu// 13388013Sbinkertn@umich.edu// A performance counter interrupt has been detected. The stack 13398013Sbinkertn@umich.edu// has been pushed. IPL and PS are updated as well. 13408013Sbinkertn@umich.edu// 13418013Sbinkertn@umich.edu// on exit to interrupt entry point ENTINT:: 13428013Sbinkertn@umich.edu// a0 = osfint$c_perf 13438013Sbinkertn@umich.edu// a1 = scb$v_perfmon (650) 13448013Sbinkertn@umich.edu// a2 = 0 if performance counter 0 fired 13458013Sbinkertn@umich.edu// a2 = 1 if performance counter 1 fired 13468013Sbinkertn@umich.edu// a2 = 2 if performance counter 2 fired 13478013Sbinkertn@umich.edu// (if more than one counter overflowed, an interrupt will be 13488013Sbinkertn@umich.edu// generated for each counter that overflows) 13498013Sbinkertn@umich.edu// 13508013Sbinkertn@umich.edu// 13518013Sbinkertn@umich.edu// 13528013Sbinkertn@umich.edu ALIGN_BLOCK 13538013Sbinkertn@umich.edusys_int_perf_cnt: // Performance counter interrupt 13548013Sbinkertn@umich.edu lda r17, scb_v_perfmon(r31) // a1 to interrupt vector 13558013Sbinkertn@umich.edu mfpr r25, pt_entint 13568013Sbinkertn@umich.edu 13578013Sbinkertn@umich.edu lda r16, osfint_c_perf(r31) // a0 to perf counter code 13588013Sbinkertn@umich.edu mtpr r25, exc_addr 13598013Sbinkertn@umich.edu 13608013Sbinkertn@umich.edu //isolate which perf ctr fired, load code in a2, and ack 13618013Sbinkertn@umich.edu mfpr r25, isr 13628013Sbinkertn@umich.edu or r31, r31, r18 // assume interrupt was pc0 13638013Sbinkertn@umich.edu 13648013Sbinkertn@umich.edu srl r25, isr_v_pc1, r25 // isolate 13658013Sbinkertn@umich.edu cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14 13668013Sbinkertn@umich.edu 13678013Sbinkertn@umich.edu srl r25, 1, r25 // get pc2 13688013Sbinkertn@umich.edu cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14 13698013Sbinkertn@umich.edu 13708013Sbinkertn@umich.edu lda r25, 1(r31) // get a one 13718013Sbinkertn@umich.edu sll r25, r18, r25 13728013Sbinkertn@umich.edu 13738013Sbinkertn@umich.edu sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt 13748013Sbinkertn@umich.edu mtpr r25, hwint_clr 13758013Sbinkertn@umich.edu 13768013Sbinkertn@umich.edu hw_rei_spe 13778013Sbinkertn@umich.edu 13788013Sbinkertn@umich.edu 13798013Sbinkertn@umich.edu 13808013Sbinkertn@umich.edu// 13818013Sbinkertn@umich.edu// sys_reset - System specific RESET code 13828013Sbinkertn@umich.edu// On entry: 13838013Sbinkertn@umich.edu// r1 = pal_base +8 13848013Sbinkertn@umich.edu// 13858013Sbinkertn@umich.edu// Entry state on trap: 13868013Sbinkertn@umich.edu// r0 = whami 13878013Sbinkertn@umich.edu// r2 = base of scratch area 13888013Sbinkertn@umich.edu// r3 = halt code 13898013Sbinkertn@umich.edu// and the following 3 if init_cbox is enabled: 13908013Sbinkertn@umich.edu// r5 = sc_ctl 13918013Sbinkertn@umich.edu// r6 = bc_ctl 13928013Sbinkertn@umich.edu// r7 = bc_cnfg 13938013Sbinkertn@umich.edu// 13948013Sbinkertn@umich.edu// Entry state on switch: 13958013Sbinkertn@umich.edu// r17 - new PC 13968013Sbinkertn@umich.edu// r18 - new PCBB 13978013Sbinkertn@umich.edu// r19 - new VPTB 13988013Sbinkertn@umich.edu// 13998013Sbinkertn@umich.edu 14008013Sbinkertn@umich.edu ALIGN_BLOCK 14018013Sbinkertn@umich.edu .globl sys_reset 14028013Sbinkertn@umich.edusys_reset: 14038013Sbinkertn@umich.edu// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load 14048013Sbinkertn@umich.edu mtpr r31, itb_ia // clear the ITB 14058013Sbinkertn@umich.edu mtpr r31, dtb_ia // clear the DTB 14068013Sbinkertn@umich.edu 14078013Sbinkertn@umich.edu lda r1, -8(r1) // point to start of code 14088013Sbinkertn@umich.edu mtpr r1, pal_base // initialize PAL_BASE 14098013Sbinkertn@umich.edu 14108013Sbinkertn@umich.edu // Interrupts 14118013Sbinkertn@umich.edu mtpr r31, astrr // stop ASTs 14128013Sbinkertn@umich.edu mtpr r31, aster // stop ASTs 14138013Sbinkertn@umich.edu mtpr r31, sirr // clear software interrupts 14148013Sbinkertn@umich.edu 14158013Sbinkertn@umich.edu mtpr r0, pt1 // r0 is whami (unless we entered via swp) 14168013Sbinkertn@umich.edu 14178013Sbinkertn@umich.edu ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero) 14188013Sbinkertn@umich.edu 14198013Sbinkertn@umich.edu bis r31, 1, r0 14208013Sbinkertn@umich.edu sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable> 14218013Sbinkertn@umich.edu or r0, r1, r1 // Set the bit 14228013Sbinkertn@umich.edu 14238013Sbinkertn@umich.edu mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable, 14248013Sbinkertn@umich.edu // super page enabled, correct read per assembly option 14258013Sbinkertn@umich.edu 14268013Sbinkertn@umich.edu // Mbox/Dcache init 14278013Sbinkertn@umich.edu lda r1,BIT(mcsr_v_sp1)(zero) 14288013Sbinkertn@umich.edu 14298013Sbinkertn@umich.edu mtpr r1, mcsr // MCSR - Super page enabled 14308013Sbinkertn@umich.edu lda r1, BIT(dc_mode_v_dc_ena)(r31) 14318013Sbinkertn@umich.edu ALIGN_BRANCH 14328013Sbinkertn@umich.edu// mtpr r1, dc_mode // turn Dcache on 14338013Sbinkertn@umich.edu nop 14348013Sbinkertn@umich.edu 14358013Sbinkertn@umich.edu mfpr r31, pt0 // No Mbox instr in 1,2,3,4 14368013Sbinkertn@umich.edu mfpr r31, pt0 14378013Sbinkertn@umich.edu mfpr r31, pt0 14388013Sbinkertn@umich.edu mfpr r31, pt0 14398013Sbinkertn@umich.edu mtpr r31, dc_flush // flush Dcache 14408013Sbinkertn@umich.edu 14418013Sbinkertn@umich.edu // build PS (IPL=7,CM=K,VMM=0,SW=0) 14428013Sbinkertn@umich.edu lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7 14438013Sbinkertn@umich.edu lda r1, 0x1F(r31) 14448013Sbinkertn@umich.edu mtpr r1, ipl // set internal <ipl>=1F 14458013Sbinkertn@umich.edu mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy 14468013Sbinkertn@umich.edu mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy 14478013Sbinkertn@umich.edu 14488013Sbinkertn@umich.edu // Create the PALtemp pt_intmask 14498013Sbinkertn@umich.edu // MAP: 14508013Sbinkertn@umich.edu // OSF IPL EV5 internal IPL(hex) note 14518013Sbinkertn@umich.edu // 0 0 14528013Sbinkertn@umich.edu // 1 1 14538013Sbinkertn@umich.edu // 2 2 14548013Sbinkertn@umich.edu // 3 14 device 14558013Sbinkertn@umich.edu // 4 15 device 14568013Sbinkertn@umich.edu // 5 16 device 14578013Sbinkertn@umich.edu // 6 1E device,performance counter, powerfail 14588013Sbinkertn@umich.edu // 7 1F 14598013Sbinkertn@umich.edu // 14608013Sbinkertn@umich.edu 14618013Sbinkertn@umich.edu ldah r1, 0x1f1E(r31) // Create upper lw of int_mask 14628013Sbinkertn@umich.edu lda r1, 0x1615(r1) 14638013Sbinkertn@umich.edu 14648013Sbinkertn@umich.edu sll r1, 32, r1 14658013Sbinkertn@umich.edu ldah r1, 0x1402(r1) // Create lower lw of int_mask 14668013Sbinkertn@umich.edu 14678013Sbinkertn@umich.edu lda r1, 0x0100(r1) 14688013Sbinkertn@umich.edu mtpr r1, pt_intmask // Stash in PALtemp 14698013Sbinkertn@umich.edu 14708013Sbinkertn@umich.edu // Unlock a bunch of chip internal IPRs 14718013Sbinkertn@umich.edu mtpr r31, exc_sum // clear out exeception summary and exc_mask 14728013Sbinkertn@umich.edu mfpr r31, va // unlock va, mmstat 14738013Sbinkertn@umich.edu lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero) 14748013Sbinkertn@umich.edu 14758013Sbinkertn@umich.edu mtpr r8, icperr_stat // Clear Icache parity error & timeout status 14768013Sbinkertn@umich.edu lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) 14778013Sbinkertn@umich.edu 14788013Sbinkertn@umich.edu mtpr r8, dcperr_stat // Clear Dcache parity error status 14798013Sbinkertn@umich.edu 14808013Sbinkertn@umich.edu rc r0 // clear intr_flag 14818013Sbinkertn@umich.edu mtpr r31, pt_trap 14828013Sbinkertn@umich.edu 14838013Sbinkertn@umich.edu mfpr r0, pt_misc 14848013Sbinkertn@umich.edu srl r0, pt_misc_v_switch, r1 14858013Sbinkertn@umich.edu blbs r1, sys_reset_switch // see if we got here from swppal 14868013Sbinkertn@umich.edu 14878013Sbinkertn@umich.edu // Rest of the "real" reset flow 14888013Sbinkertn@umich.edu // ASN 14898013Sbinkertn@umich.edu mtpr r31, dtb_asn 14908013Sbinkertn@umich.edu mtpr r31, itb_asn 14918013Sbinkertn@umich.edu 14928013Sbinkertn@umich.edu lda r1, 0x67(r31) 14938013Sbinkertn@umich.edu sll r1, hwint_clr_v_pc0c, r1 14948013Sbinkertn@umich.edu mtpr r1, hwint_clr // Clear hardware interrupt requests 14958013Sbinkertn@umich.edu 14968013Sbinkertn@umich.edu lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error 14978013Sbinkertn@umich.edu mfpr r0, pt1 // get whami 14988013Sbinkertn@umich.edu insbl r0, 1, r0 // isolate whami in correct pt_misc position 14998013Sbinkertn@umich.edu or r0, r1, r1 // combine whami and mces 15008013Sbinkertn@umich.edu mtpr r1, pt_misc // store whami and mces, swap bit clear 15018013Sbinkertn@umich.edu 15028013Sbinkertn@umich.edu zapnot r3, 1, r0 // isolate halt code 15038013Sbinkertn@umich.edu mtpr r0, pt0 // save entry type 15048013Sbinkertn@umich.edu 15058013Sbinkertn@umich.edu // Cycle counter 15068013Sbinkertn@umich.edu or r31, 1, r9 // get a one 15078013Sbinkertn@umich.edu sll r9, 32, r9 // shift to <32> 15088013Sbinkertn@umich.edu mtpr r31, cc // clear Cycle Counter 15098013Sbinkertn@umich.edu mtpr r9, cc_ctl // clear and enable the Cycle Counter 15108013Sbinkertn@umich.edu mtpr r31, pt_scc // clear System Cycle Counter 15118013Sbinkertn@umich.edu 15128013Sbinkertn@umich.edu 15138013Sbinkertn@umich.edu // Misc PALtemps 15148013Sbinkertn@umich.edu mtpr r31, maf_mode // no mbox instructions for 3 cycles 15158013Sbinkertn@umich.edu or r31, 1, r1 // get bogus scbb value 15168013Sbinkertn@umich.edu mtpr r1, pt_scbb // load scbb 15178013Sbinkertn@umich.edu mtpr r31, pt_prbr // clear out prbr 15188013Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 15198013Sbinkertn@umich.edu // yes, this is ugly, but you figure out a better 15208013Sbinkertn@umich.edu // way to get the address of the kludge_initial_pcbb 15218013Sbinkertn@umich.edu // in r1 with an uncooperative assembler --ali 15228013Sbinkertn@umich.edu br r1, kludge_getpcb_addr 15238013Sbinkertn@umich.edu br r31, kludge_initial_pcbb 15248013Sbinkertn@umich.edukludge_getpcb_addr: 15258013Sbinkertn@umich.edu ldq_p r19, 0(r1) 15268013Sbinkertn@umich.edu sll r19, 44, r19 15278013Sbinkertn@umich.edu srl r19, 44, r19 15288013Sbinkertn@umich.edu mulq r19,4,r19 15298013Sbinkertn@umich.edu addq r19, r1, r1 15308013Sbinkertn@umich.edu addq r1,4,r1 15318013Sbinkertn@umich.edu#elif defined(TLASER) 15328013Sbinkertn@umich.edu // or zero,kludge_initial_pcbb,r1 15338013Sbinkertn@umich.edu GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1) 15348013Sbinkertn@umich.edu#endif 15358013Sbinkertn@umich.edu mtpr r1, pt_pcbb // load pcbb 15368013Sbinkertn@umich.edu lda r1, 2(r31) // get a two 15378013Sbinkertn@umich.edu sll r1, 32, r1 // gen up upper bits 15388013Sbinkertn@umich.edu mtpr r1, mvptbr 15398013Sbinkertn@umich.edu mtpr r1, ivptbr 15408013Sbinkertn@umich.edu mtpr r31, pt_ptbr 15418013Sbinkertn@umich.edu // Performance counters 15428013Sbinkertn@umich.edu mtpr r31, pmctr 15438013Sbinkertn@umich.edu 15448013Sbinkertn@umich.edu // Clear pmctr_ctl in impure area 15458013Sbinkertn@umich.edu 15468013Sbinkertn@umich.edu 15478013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 15488013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 15498013Sbinkertn@umich.edu GET_IMPURE(r13) 15508013Sbinkertn@umich.edu stq_p r31, 0(r13) // Clear lock_flag 15518013Sbinkertn@umich.edu 15528013Sbinkertn@umich.edu mfpr r0, pt0 // get entry type 15538013Sbinkertn@umich.edu br r31, sys_enter_console // enter the cosole 15548013Sbinkertn@umich.edu 15558013Sbinkertn@umich.edu 15568013Sbinkertn@umich.edu // swppal entry 15578013Sbinkertn@umich.edu // r0 - pt_misc 15588013Sbinkertn@umich.edu // r17 - new PC 15598013Sbinkertn@umich.edu // r18 - new PCBB 15608013Sbinkertn@umich.edu // r19 - new VPTB 15618013Sbinkertn@umich.edusys_reset_switch: 15628013Sbinkertn@umich.edu or r31, 1, r9 15638013Sbinkertn@umich.edu sll r9, pt_misc_v_switch, r9 15648013Sbinkertn@umich.edu bic r0, r9, r0 // clear switch bit 15658013Sbinkertn@umich.edu mtpr r0, pt_misc 15668013Sbinkertn@umich.edu 15678013Sbinkertn@umich.edu rpcc r1 // get cyccounter 15688013Sbinkertn@umich.edu 15698013Sbinkertn@umich.edu ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme 15708013Sbinkertn@umich.edu ldl_p r23, osfpcb_l_cc(r18) // get cycle counter 15718013Sbinkertn@umich.edu ldl_p r24, osfpcb_l_asn(r18) // get new asn 15728013Sbinkertn@umich.edu 15738013Sbinkertn@umich.edu 15748013Sbinkertn@umich.edu ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr 15758013Sbinkertn@umich.edu sll r25, page_offset_size_bits, r25 // convert pfn to pa 15768013Sbinkertn@umich.edu mtpr r25, pt_ptbr // load the new mmptr 15778013Sbinkertn@umich.edu mtpr r18, pt_pcbb // set new pcbb 15788013Sbinkertn@umich.edu 15798013Sbinkertn@umich.edu bic r17, 3, r17 // clean use pc 15808013Sbinkertn@umich.edu mtpr r17, exc_addr // set new pc 15818013Sbinkertn@umich.edu mtpr r19, mvptbr 15828013Sbinkertn@umich.edu mtpr r19, ivptbr 15838013Sbinkertn@umich.edu 15848013Sbinkertn@umich.edu ldq_p r30, osfpcb_q_Usp(r18) // get new usp 15858013Sbinkertn@umich.edu mtpr r30, pt_usp // save usp 15868013Sbinkertn@umich.edu 15878013Sbinkertn@umich.edu sll r24, dtb_asn_v_asn, r8 15888013Sbinkertn@umich.edu mtpr r8, dtb_asn 15898013Sbinkertn@umich.edu sll r24, itb_asn_v_asn, r24 15908013Sbinkertn@umich.edu mtpr r24, itb_asn 15918013Sbinkertn@umich.edu 15928013Sbinkertn@umich.edu mfpr r25, icsr // get current icsr 15938013Sbinkertn@umich.edu lda r24, 1(r31) 15948013Sbinkertn@umich.edu sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position 15958013Sbinkertn@umich.edu bic r25, r24, r25 // clean out old fpe 15968013Sbinkertn@umich.edu and r22, 1, r22 // isolate new fen bit 15978013Sbinkertn@umich.edu sll r22, icsr_v_fpe, r22 15988013Sbinkertn@umich.edu or r22, r25, r25 // or in new fpe 15998013Sbinkertn@umich.edu mtpr r25, icsr // update ibox ipr 16008013Sbinkertn@umich.edu 16018013Sbinkertn@umich.edu subl r23, r1, r1 // gen new cc offset 16028013Sbinkertn@umich.edu insll r1, 4, r1 // << 32 16038013Sbinkertn@umich.edu mtpr r1, cc // set new offset 16048013Sbinkertn@umich.edu 16058013Sbinkertn@umich.edu or r31, r31, r0 // set success 16068013Sbinkertn@umich.edu ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp 16078013Sbinkertn@umich.edu mfpr r31, pt0 // stall 16088013Sbinkertn@umich.edu hw_rei_stall 16098013Sbinkertn@umich.edu 16108013Sbinkertn@umich.edu// 16118013Sbinkertn@umich.edu//sys_machine_check - Machine check PAL 16128013Sbinkertn@umich.edu// A machine_check trap has occurred. The Icache has been flushed. 16138013Sbinkertn@umich.edu// 16148013Sbinkertn@umich.edu// 16158013Sbinkertn@umich.edu 16168013Sbinkertn@umich.edu ALIGN_BLOCK 16178013Sbinkertn@umich.eduEXPORT(sys_machine_check) 16188013Sbinkertn@umich.edu // Need to fill up the refill buffer (32 instructions) and 16198013Sbinkertn@umich.edu // then flush the Icache again. 16208013Sbinkertn@umich.edu // Also, due to possible 2nd Cbox register file write for 16218013Sbinkertn@umich.edu // uncorrectable errors, no register file read or write for 7 cycles. 16228013Sbinkertn@umich.edu 16238013Sbinkertn@umich.edu nop 16248013Sbinkertn@umich.edu mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites 16258013Sbinkertn@umich.edu // r0 later 16268013Sbinkertn@umich.edu nop 16278013Sbinkertn@umich.edu nop 16288013Sbinkertn@umich.edu 16298013Sbinkertn@umich.edu nop 16308013Sbinkertn@umich.edu nop 16318013Sbinkertn@umich.edu 16328013Sbinkertn@umich.edu nop 16338013Sbinkertn@umich.edu nop 16348013Sbinkertn@umich.edu 16358013Sbinkertn@umich.edu nop 16368013Sbinkertn@umich.edu nop 16378013Sbinkertn@umich.edu // 10 instructions// 5 cycles 16388013Sbinkertn@umich.edu 16398013Sbinkertn@umich.edu nop 16408013Sbinkertn@umich.edu nop 16418013Sbinkertn@umich.edu 16428013Sbinkertn@umich.edu nop 16438013Sbinkertn@umich.edu nop 16448013Sbinkertn@umich.edu 16458013Sbinkertn@umich.edu // Register file can now be written 16468013Sbinkertn@umich.edu lda r0, scb_v_procmchk(r31) // SCB vector 16478013Sbinkertn@umich.edu mfpr r13, pt_mces // Get MCES 16488013Sbinkertn@umich.edu sll r0, 16, r0 // Move SCBv to correct position 16498013Sbinkertn@umich.edu bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit 16508013Sbinkertn@umich.edu 16518013Sbinkertn@umich.edu 16528013Sbinkertn@umich.edu zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word 16538013Sbinkertn@umich.edu mtpr r14, pt_mces 16548013Sbinkertn@umich.edu // 20 instructions 16558013Sbinkertn@umich.edu 16568013Sbinkertn@umich.edu nop 16578013Sbinkertn@umich.edu or r14, r0, r14 // Insert new SCB vector 16588013Sbinkertn@umich.edu lda r0, mchk_c_proc_hrd_error(r31) // MCHK code 16598013Sbinkertn@umich.edu mfpr r12, exc_addr 16608013Sbinkertn@umich.edu 16618013Sbinkertn@umich.edu sll r0, 32, r0 // Move MCHK code to correct position 16628013Sbinkertn@umich.edu mtpr r4, pt4 16638013Sbinkertn@umich.edu or r14, r0, r14 // Insert new MCHK code 16648013Sbinkertn@umich.edu mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv 16658013Sbinkertn@umich.edu 16668013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 16678013Sbinkertn@umich.edu mtpr r1, pt1 // Stash for scratch - 30 instructions 16688013Sbinkertn@umich.edu 16698013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 16708013Sbinkertn@umich.edu mtpr r12, pt10 // Stash exc_addr 16718013Sbinkertn@umich.edu 16728013Sbinkertn@umich.edu 16738013Sbinkertn@umich.edu 16748013Sbinkertn@umich.edu mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed. 16758013Sbinkertn@umich.edu blbs r13, sys_double_machine_check // MCHK halt if double machine check 16768013Sbinkertn@umich.edu 16778013Sbinkertn@umich.edu mtpr r6, pt6 16788013Sbinkertn@umich.edu mtpr r5, pt5 16798013Sbinkertn@umich.edu 16808013Sbinkertn@umich.edu // Look for the powerfail cases here.... 16818013Sbinkertn@umich.edu mfpr r4, isr 16828013Sbinkertn@umich.edu srl r4, isr_v_pfl, r4 16838013Sbinkertn@umich.edu blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending 16848013Sbinkertn@umich.edu lda r4, 0xffc4(r31) // get GBUS$MISCR address bits 16858013Sbinkertn@umich.edu sll r4, 24, r4 // shift to proper position 16868013Sbinkertn@umich.edu ldq_p r4, 0(r4) // read GBUS$MISCR 16878013Sbinkertn@umich.edu srl r4, 5, r4 // isolate bit <5> 16888013Sbinkertn@umich.edu blbc r4, sys_mchk_collect_iprs // skip if already cleared 16898013Sbinkertn@umich.edu // No missed CFAIL mchk 16908013Sbinkertn@umich.edu lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits 16918013Sbinkertn@umich.edu sll r5, 24, r5 // shift to proper position 16928013Sbinkertn@umich.edu lda r6, 0x40(r31) // get bit <6> mask 16938013Sbinkertn@umich.edu ldq_p r4, 0(r5) // read GBUS$SERNUM 16948013Sbinkertn@umich.edu or r4, r6, r6 // set bit <6> 16958013Sbinkertn@umich.edu stq_p r6, 0(r5) // clear GBUS$SERNUM<6> 16968013Sbinkertn@umich.edu mb 16978013Sbinkertn@umich.edu mb 16988013Sbinkertn@umich.edu 16998013Sbinkertn@umich.edu 17008013Sbinkertn@umich.edu // 17018013Sbinkertn@umich.edu // Start to collect the IPRs. Common entry point for mchk flows. 17028013Sbinkertn@umich.edu // 17038013Sbinkertn@umich.edu // Current state: 17048013Sbinkertn@umich.edu // pt0 - saved r0 17058013Sbinkertn@umich.edu // pt1 - saved r1 17068013Sbinkertn@umich.edu // pt4 - saved r4 17078013Sbinkertn@umich.edu // pt5 - saved r5 17088013Sbinkertn@umich.edu // pt6 - saved r6 17098013Sbinkertn@umich.edu // pt10 - saved exc_addr 17108013Sbinkertn@umich.edu // pt_misc<47:32> - mchk code 17118013Sbinkertn@umich.edu // pt_misc<31:16> - scb vector 17128013Sbinkertn@umich.edu // r14 - base of Cbox IPRs in IO space 17138013Sbinkertn@umich.edu // r0, r1, r4, r5, r6, r12, r13, r25 - available 17148013Sbinkertn@umich.edu // r8, r9, r10 - available as all loads are physical 17158013Sbinkertn@umich.edu // MCES<mchk> is set 17168013Sbinkertn@umich.edu // 17178013Sbinkertn@umich.edu // 17188013Sbinkertn@umich.edu 17198013Sbinkertn@umich.eduEXPORT(sys_mchk_collect_iprs) 17208013Sbinkertn@umich.edu mb // MB before reading Scache IPRs 17218013Sbinkertn@umich.edu mfpr r1, icperr_stat 17228013Sbinkertn@umich.edu 17238013Sbinkertn@umich.edu mfpr r8, dcperr_stat 17248013Sbinkertn@umich.edu mtpr r31, dc_flush // Flush the Dcache 17258013Sbinkertn@umich.edu 17268013Sbinkertn@umich.edu mfpr r31, pt0 // Pad Mbox instructions from dc_flush 17278013Sbinkertn@umich.edu mfpr r31, pt0 17288013Sbinkertn@umich.edu nop 17298013Sbinkertn@umich.edu nop 17308013Sbinkertn@umich.edu 17318013Sbinkertn@umich.edu ldq_p r9, sc_addr(r14) // SC_ADDR IPR 17328013Sbinkertn@umich.edu bis r9, r31, r31 // Touch ld to make sure it completes before 17338013Sbinkertn@umich.edu // read of SC_STAT 17348013Sbinkertn@umich.edu ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR 17358013Sbinkertn@umich.edu 17368013Sbinkertn@umich.edu ldq_p r12, ei_addr(r14) // EI_ADDR IPR 17378013Sbinkertn@umich.edu ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR 17388013Sbinkertn@umich.edu ldq_p r0, fill_syn(r14) // FILL_SYN IPR 17398013Sbinkertn@umich.edu bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT 17408013Sbinkertn@umich.edu bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT 17418013Sbinkertn@umich.edu ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 17428013Sbinkertn@umich.edu ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked 17438013Sbinkertn@umich.edu 17448013Sbinkertn@umich.edu 17458013Sbinkertn@umich.edu 17468013Sbinkertn@umich.edu 17478013Sbinkertn@umich.edu // 17488013Sbinkertn@umich.edu // Look for nonretryable cases 17498013Sbinkertn@umich.edu // In this segment: 17508013Sbinkertn@umich.edu // r5<0> = 1 means retryable 17518013Sbinkertn@umich.edu // r4, r6, and r14 are available for scratch 17528013Sbinkertn@umich.edu // 17538013Sbinkertn@umich.edu // 17548013Sbinkertn@umich.edu 17558013Sbinkertn@umich.edu 17568013Sbinkertn@umich.edu bis r31, r31, r5 // Clear local retryable flag 17578013Sbinkertn@umich.edu srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits 17588013Sbinkertn@umich.edu 17598013Sbinkertn@umich.edu lda r4, 1(r31) 17608013Sbinkertn@umich.edu sll r4, icperr_stat_v_tmr, r4 17618013Sbinkertn@umich.edu and r1, r4, r4 // Timeout reset 17628013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17638013Sbinkertn@umich.edu 17648013Sbinkertn@umich.edu and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked 17658013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17668013Sbinkertn@umich.edu 17678013Sbinkertn@umich.edu lda r4, 1(r31) 17688013Sbinkertn@umich.edu sll r4, sc_stat_v_sc_scnd_err, r4 17698013Sbinkertn@umich.edu and r10, r4, r4 // 2nd Scache error occurred 17708013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17718013Sbinkertn@umich.edu 17728013Sbinkertn@umich.edu 17738013Sbinkertn@umich.edu bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control 17748013Sbinkertn@umich.edu // Parity Error, Interface Parity Error, 2nd Error 17758013Sbinkertn@umich.edu 17768013Sbinkertn@umich.edu and r25, r4, r4 17778013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17788013Sbinkertn@umich.edu 17798013Sbinkertn@umich.edu// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4 17808013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 17818013Sbinkertn@umich.edu and r25, r4, r4 // Isolate the Uncorrectable Error Bit 17828013Sbinkertn@umich.edu// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6 17838013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit 17848013Sbinkertn@umich.edu cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error 17858013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17868013Sbinkertn@umich.edu 17878013Sbinkertn@umich.edu lda r4, 7(r31) 17888013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Tag Parity Error bits 17898013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable 17908013Sbinkertn@umich.edu 17918013Sbinkertn@umich.edu 17928013Sbinkertn@umich.edu lda r4, 0x7f8(r31) 17938013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Data Parity Error bits 17948013Sbinkertn@umich.edu srl r10, sc_stat_v_cbox_cmd, r6 17958013Sbinkertn@umich.edu and r6, 0x1f, r6 // Isolate Scache Command field 17968013Sbinkertn@umich.edu subq r6, 1, r6 // Scache Iread command = 1 17978013Sbinkertn@umich.edu cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error 17988013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17998013Sbinkertn@umich.edu 18008013Sbinkertn@umich.edu // Look for the system unretryable cases here.... 18018013Sbinkertn@umich.edu 18028013Sbinkertn@umich.edu mfpr r4, isr // mchk_interrupt pin asserted 18038013Sbinkertn@umich.edu srl r4, isr_v_mck, r4 18048013Sbinkertn@umich.edu blbs r4, sys_cpu_mchk_not_retryable 18058013Sbinkertn@umich.edu 18068013Sbinkertn@umich.edu 18078013Sbinkertn@umich.edu 18088013Sbinkertn@umich.edu // 18098013Sbinkertn@umich.edu // Look for retryable cases 18108013Sbinkertn@umich.edu // In this segment: 18118013Sbinkertn@umich.edu // r5<0> = 1 means retryable 18128013Sbinkertn@umich.edu // r6 - holds the mchk code 18138013Sbinkertn@umich.edu // r4 and r14 are available for scratch 18148013Sbinkertn@umich.edu // 18158013Sbinkertn@umich.edu // 18168013Sbinkertn@umich.edu 18178013Sbinkertn@umich.edu 18188013Sbinkertn@umich.edu // Within the chip, the retryable cases are Istream errors 18198013Sbinkertn@umich.edu lda r4, 3(r31) 18208013Sbinkertn@umich.edu sll r4, icperr_stat_v_dpe, r4 18218013Sbinkertn@umich.edu and r1, r4, r4 18228013Sbinkertn@umich.edu cmovne r4, 1, r5 // Retryable if just Icache parity error 18238013Sbinkertn@umich.edu 18248013Sbinkertn@umich.edu 18258013Sbinkertn@umich.edu lda r4, 0x7f8(r31) 18268013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Data Parity Error bits 18278013Sbinkertn@umich.edu srl r10, sc_stat_v_cbox_cmd, r14 18288013Sbinkertn@umich.edu and r14, 0x1f, r14 // Isolate Scache Command field 18298013Sbinkertn@umich.edu subq r14, 1, r14 // Scache Iread command = 1 18308013Sbinkertn@umich.edu cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set 18318013Sbinkertn@umich.edu cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread 18328013Sbinkertn@umich.edu bis r4, r5, r5 // Accumulate 18338013Sbinkertn@umich.edu 18348013Sbinkertn@umich.edu 18358013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 18368013Sbinkertn@umich.edu and r25, r4, r4 // Isolate the Uncorrectable Error Bit 18378013Sbinkertn@umich.edu and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit 18388013Sbinkertn@umich.edu cmovne r4, 1, r4 // r4 = 1 if uncorr error 18398013Sbinkertn@umich.edu cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread 18408013Sbinkertn@umich.edu bis r4, r5, r5 // Accumulate 18418013Sbinkertn@umich.edu 18428013Sbinkertn@umich.edu mfpr r6, pt_misc 18438013Sbinkertn@umich.edu extwl r6, 4, r6 // Fetch mchk code 18448013Sbinkertn@umich.edu bic r6, 1, r6 // Clear flag from interrupt flow 18458013Sbinkertn@umich.edu cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code 18468013Sbinkertn@umich.edu 18478013Sbinkertn@umich.edu 18488013Sbinkertn@umich.edu // 18498013Sbinkertn@umich.edu // Write the logout frame 18508013Sbinkertn@umich.edu // 18518013Sbinkertn@umich.edu // Current state: 18528013Sbinkertn@umich.edu // r0 - fill_syn 18538013Sbinkertn@umich.edu // r1 - icperr_stat 18548013Sbinkertn@umich.edu // r4 - available 18558013Sbinkertn@umich.edu // r5<0> - retry flag 18568013Sbinkertn@umich.edu // r6 - mchk code 18578013Sbinkertn@umich.edu // r8 - dcperr_stat 18588013Sbinkertn@umich.edu // r9 - sc_addr 18598013Sbinkertn@umich.edu // r10 - sc_stat 18608013Sbinkertn@umich.edu // r12 - ei_addr 18618013Sbinkertn@umich.edu // r13 - bc_tag_addr 18628013Sbinkertn@umich.edu // r14 - available 18638013Sbinkertn@umich.edu // r25 - ei_stat (shifted) 18648013Sbinkertn@umich.edu // pt0 - saved r0 18658013Sbinkertn@umich.edu // pt1 - saved r1 18668013Sbinkertn@umich.edu // pt4 - saved r4 18678013Sbinkertn@umich.edu // pt5 - saved r5 18688013Sbinkertn@umich.edu // pt6 - saved r6 18698013Sbinkertn@umich.edu // pt10 - saved exc_addr 18708013Sbinkertn@umich.edu // 18718013Sbinkertn@umich.edu // 18728013Sbinkertn@umich.edu 18738013Sbinkertn@umich.edusys_mchk_write_logout_frame: 18748013Sbinkertn@umich.edu // Get base of the logout area. 18758013Sbinkertn@umich.edu GET_IMPURE(r14) // addr of per-cpu impure area 18768013Sbinkertn@umich.edu GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14) 18778013Sbinkertn@umich.edu 18788013Sbinkertn@umich.edu // Write the first 2 quadwords of the logout area: 18798013Sbinkertn@umich.edu 18808013Sbinkertn@umich.edu sll r5, 63, r5 // Move retry flag to bit 63 18818013Sbinkertn@umich.edu lda r4, mchk_size(r5) // Combine retry flag and frame size 18828013Sbinkertn@umich.edu stq_p r4, mchk_flag(r14) // store flag/frame size 18838013Sbinkertn@umich.edu lda r4, mchk_sys_base(r31) // sys offset 18848013Sbinkertn@umich.edu sll r4, 32, r4 18858013Sbinkertn@umich.edu lda r4, mchk_cpu_base(r4) // cpu offset 18868013Sbinkertn@umich.edu stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame 18878013Sbinkertn@umich.edu 18888013Sbinkertn@umich.edu // 18898013Sbinkertn@umich.edu // Write the mchk code to the logout area 18908013Sbinkertn@umich.edu // Write error IPRs already fetched to the logout area 18918013Sbinkertn@umich.edu // Restore some GPRs from PALtemps 18928013Sbinkertn@umich.edu // 18938013Sbinkertn@umich.edu 18948013Sbinkertn@umich.edu mfpr r5, pt5 18958013Sbinkertn@umich.edu stq_p r6, mchk_mchk_code(r14) 18968013Sbinkertn@umich.edu mfpr r4, pt4 18978013Sbinkertn@umich.edu stq_p r1, mchk_ic_perr_stat(r14) 18988013Sbinkertn@umich.edu mfpr r6, pt6 18998013Sbinkertn@umich.edu stq_p r8, mchk_dc_perr_stat(r14) 19008013Sbinkertn@umich.edu mfpr r1, pt1 19018013Sbinkertn@umich.edu stq_p r9, mchk_sc_addr(r14) 19028013Sbinkertn@umich.edu stq_p r10, mchk_sc_stat(r14) 19038013Sbinkertn@umich.edu stq_p r12, mchk_ei_addr(r14) 19048013Sbinkertn@umich.edu stq_p r13, mchk_bc_tag_addr(r14) 19058013Sbinkertn@umich.edu stq_p r0, mchk_fill_syn(r14) 19068013Sbinkertn@umich.edu mfpr r0, pt0 19078013Sbinkertn@umich.edu sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position 19088013Sbinkertn@umich.edu // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame 19098013Sbinkertn@umich.edu ldah r13, 0xfff0(r31) 19108013Sbinkertn@umich.edu zapnot r13, 0x1f, r13 19118013Sbinkertn@umich.edu ldq_p r13, ei_stat(r13) 19128013Sbinkertn@umich.edu sll r13, 64-ei_stat_v_bc_tperr, r13 19138013Sbinkertn@umich.edu srl r13, 64-ei_stat_v_bc_tperr, r13 19148013Sbinkertn@umich.edu or r25, r13, r25 19158013Sbinkertn@umich.edu stq_p r25, mchk_ei_stat(r14) 19168013Sbinkertn@umich.edu 19178013Sbinkertn@umich.edu 19188013Sbinkertn@umich.edu 19198013Sbinkertn@umich.edu 19208013Sbinkertn@umich.edu // 19218013Sbinkertn@umich.edu // complete the CPU-specific part of the logout frame 19228013Sbinkertn@umich.edu // 19238013Sbinkertn@umich.edu 19248013Sbinkertn@umich.edu ldah r13, 0xfff0(r31) 19258013Sbinkertn@umich.edu zap r13, 0xE0, r13 // Get Cbox IPR base 19268013Sbinkertn@umich.edu ldq_p r13, ld_lock(r13) // Get ld_lock IPR 19278013Sbinkertn@umich.edu stq_p r13, mchk_ld_lock(r14) // and stash it in the frame 19288013Sbinkertn@umich.edu 19298013Sbinkertn@umich.edu // Unlock IPRs 19308013Sbinkertn@umich.edu lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) 19318013Sbinkertn@umich.edu mtpr r8, dcperr_stat // Clear Dcache parity error status 19328013Sbinkertn@umich.edu 19338013Sbinkertn@umich.edu lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31) 19348013Sbinkertn@umich.edu mtpr r8, icperr_stat // Clear Icache parity error & timeout status 19358013Sbinkertn@umich.edu 19368013Sbinkertn@umich.edu1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value 19378013Sbinkertn@umich.edu GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value 19388013Sbinkertn@umich.edu and r0, r8, r0 // compare 19398013Sbinkertn@umich.edu beq r0, 2f // check next case if nothing set 19408013Sbinkertn@umich.edu lda r0, mchk_c_retryable_ird(r31) // set new MCHK code 19418013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19428013Sbinkertn@umich.edu 19438013Sbinkertn@umich.edu2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value 19448013Sbinkertn@umich.edu GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value 19458013Sbinkertn@umich.edu and r0, r8, r0 // compare 19468013Sbinkertn@umich.edu beq r0, 3f // check next case if nothing set 19478013Sbinkertn@umich.edu lda r0, mchk_c_dcperr(r31) // set new MCHK code 19488013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19498013Sbinkertn@umich.edu 19508013Sbinkertn@umich.edu3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value 19518013Sbinkertn@umich.edu GET_ADDR(r0,0x107ff,r31) // get SC_STAT value 19528013Sbinkertn@umich.edu and r0, r8, r0 // compare 19538013Sbinkertn@umich.edu beq r0, 4f // check next case if nothing set 19548013Sbinkertn@umich.edu lda r0, mchk_c_scperr(r31) // set new MCHK code 19558013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19568013Sbinkertn@umich.edu 19578013Sbinkertn@umich.edu4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value 19588013Sbinkertn@umich.edu GET_ADDR(r0,0x30000000,r31) // get EI_STAT value 19598013Sbinkertn@umich.edu and r0, r8, r0 // compare 19608013Sbinkertn@umich.edu beq r0, 5f // check next case if nothing set 19618013Sbinkertn@umich.edu lda r0, mchk_c_bcperr(r31) // set new MCHK code 19628013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19638013Sbinkertn@umich.edu 19648013Sbinkertn@umich.edu5: ldl_p r8, mchk_tlber(r14) // get TLBER value 19658013Sbinkertn@umich.edu GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value 19668013Sbinkertn@umich.edu sll r0, 16, r0 // shift into proper position 19678013Sbinkertn@umich.edu GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value 19688013Sbinkertn@umich.edu or r0, r1, r0 // merge mask values 19698013Sbinkertn@umich.edu and r0, r8, r0 // compare 19708013Sbinkertn@umich.edu beq r0, 6f // check next case if nothing set 19718013Sbinkertn@umich.edu GET_ADDR(r0, 0xfff0, r31) // set new MCHK code 19728013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19738013Sbinkertn@umich.edu 19748013Sbinkertn@umich.edu6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value 19758013Sbinkertn@umich.edu GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value 19768013Sbinkertn@umich.edu and r0, r8, r0 // compare 19778013Sbinkertn@umich.edu beq r0, 7f // check next case if nothing set 19788013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffa, r31) // set new MCHK code 19798013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19808013Sbinkertn@umich.edu 19818013Sbinkertn@umich.edu7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value 19828013Sbinkertn@umich.edu GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value 19838013Sbinkertn@umich.edu and r0, r8, r0 // compare 19848013Sbinkertn@umich.edu beq r0, 8f // check next case if nothing set 19858013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffb, r31) // set new MCHK code 19868013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19878013Sbinkertn@umich.edu 19888013Sbinkertn@umich.edu8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value 19898013Sbinkertn@umich.edu GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value 19908013Sbinkertn@umich.edu and r0, r8, r0 // compare 19918013Sbinkertn@umich.edu beq r0, 9f // check next case if nothing set 19928013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffc, r31) // set new MCHK code 19938013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19948013Sbinkertn@umich.edu 19958013Sbinkertn@umich.edu9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value 19968013Sbinkertn@umich.edu GET_ADDR(r0,0xb,r31) // get EI_STAT mask value 19978013Sbinkertn@umich.edu sll r0, 32, r0 // shift to upper lw 19988013Sbinkertn@umich.edu and r0, r8, r0 // compare 19998013Sbinkertn@umich.edu beq r0, 1f // check next case if nothing set 20008013Sbinkertn@umich.edu GET_ADDR(r0,0xfffd,r31) // set new MCHK code 20018013Sbinkertn@umich.edu br r31, do_660 // setup new vector 20028013Sbinkertn@umich.edu 20038013Sbinkertn@umich.edu1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value 20048013Sbinkertn@umich.edu GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value 20058013Sbinkertn@umich.edu and r0, r8, r0 // compare 20068013Sbinkertn@umich.edu beq r0, cont_logout_frame // check next case if nothing set 20078013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffe, r31) // set new MCHK code 20088013Sbinkertn@umich.edu br r31, do_660 // setup new vector 20098013Sbinkertn@umich.edu 20108013Sbinkertn@umich.edudo_670: lda r8, scb_v_procmchk(r31) // SCB vector 20118013Sbinkertn@umich.edu br r31, do_6x0_cont 20128013Sbinkertn@umich.edudo_660: lda r8, scb_v_sysmchk(r31) // SCB vector 20138013Sbinkertn@umich.edudo_6x0_cont: 20148013Sbinkertn@umich.edu sll r8, 16, r8 // shift to proper position 20158013Sbinkertn@umich.edu mfpr r1, pt_misc // fetch current pt_misc 20168013Sbinkertn@umich.edu GET_ADDR(r4,0xffff, r31) // mask for vector field 20178013Sbinkertn@umich.edu sll r4, 16, r4 // shift to proper position 20188013Sbinkertn@umich.edu bic r1, r4, r1 // clear out old vector field 20198013Sbinkertn@umich.edu or r1, r8, r1 // merge in new vector 20208013Sbinkertn@umich.edu mtpr r1, pt_misc // save new vector field 20218013Sbinkertn@umich.edu stl_p r0, mchk_mchk_code(r14) // save new mchk code 20228013Sbinkertn@umich.edu 20238013Sbinkertn@umich.educont_logout_frame: 20248013Sbinkertn@umich.edu // Restore some GPRs from PALtemps 20258013Sbinkertn@umich.edu mfpr r0, pt0 20268013Sbinkertn@umich.edu mfpr r1, pt1 20278013Sbinkertn@umich.edu mfpr r4, pt4 20288013Sbinkertn@umich.edu 20298013Sbinkertn@umich.edu mfpr r12, pt10 // fetch original PC 20308013Sbinkertn@umich.edu blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal 20318013Sbinkertn@umich.edu 20328013Sbinkertn@umich.edu//XXXbugnion pvc_jsr armc, bsr=1 20338013Sbinkertn@umich.edu bsr r12, sys_arith_and_mchk // go check for and deal with arith trap 20348013Sbinkertn@umich.edu 20358013Sbinkertn@umich.edu mtpr r31, exc_sum // Clear Exception Summary 20368013Sbinkertn@umich.edu 20378013Sbinkertn@umich.edu mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc 20388013Sbinkertn@umich.edu stq_p r25, mchk_exc_addr(r14) 20398013Sbinkertn@umich.edu 20408013Sbinkertn@umich.edu // 20418013Sbinkertn@umich.edu // Set up the km trap 20428013Sbinkertn@umich.edu // 20438013Sbinkertn@umich.edu 20448013Sbinkertn@umich.edu 20458013Sbinkertn@umich.edusys_post_mchk_trap: 20468013Sbinkertn@umich.edu mfpr r25, pt_misc // Check for flag from mchk interrupt 20478013Sbinkertn@umich.edu extwl r25, 4, r25 20488013Sbinkertn@umich.edu blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow 20498013Sbinkertn@umich.edu 20508013Sbinkertn@umich.edu bis r14, r31, r12 // stash pointer to logout area 20518013Sbinkertn@umich.edu mfpr r14, pt10 // get exc_addr 20528013Sbinkertn@umich.edu 20538013Sbinkertn@umich.edu sll r11, 63-3, r25 // get mode to msb 20548013Sbinkertn@umich.edu bge r25, 3f 20558013Sbinkertn@umich.edu 20568013Sbinkertn@umich.edu mtpr r31, dtb_cm 20578013Sbinkertn@umich.edu mtpr r31, ev5__ps 20588013Sbinkertn@umich.edu 20598013Sbinkertn@umich.edu mtpr r30, pt_usp // save user stack 20608013Sbinkertn@umich.edu mfpr r30, pt_ksp 20618013Sbinkertn@umich.edu 20628013Sbinkertn@umich.edu3: 20638013Sbinkertn@umich.edu lda sp, 0-osfsf_c_size(sp) // allocate stack space 20648013Sbinkertn@umich.edu nop 20658013Sbinkertn@umich.edu 20668013Sbinkertn@umich.edu stq r18, osfsf_a2(sp) // a2 20678013Sbinkertn@umich.edu stq r11, osfsf_ps(sp) // save ps 20688013Sbinkertn@umich.edu 20698013Sbinkertn@umich.edu stq r14, osfsf_pc(sp) // save pc 20708013Sbinkertn@umich.edu mfpr r25, pt_entint // get the VA of the interrupt routine 20718013Sbinkertn@umich.edu 20728013Sbinkertn@umich.edu stq r16, osfsf_a0(sp) // a0 20738013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk in a0 20748013Sbinkertn@umich.edu 20758013Sbinkertn@umich.edu stq r17, osfsf_a1(sp) // a1 20768013Sbinkertn@umich.edu mfpr r17, pt_misc // get vector 20778013Sbinkertn@umich.edu 20788013Sbinkertn@umich.edu stq r29, osfsf_gp(sp) // old gp 20798013Sbinkertn@umich.edu mtpr r25, exc_addr // 20808013Sbinkertn@umich.edu 20818013Sbinkertn@umich.edu or r31, 7, r11 // get new ps (km, high ipl) 20828013Sbinkertn@umich.edu subq r31, 1, r18 // get a -1 20838013Sbinkertn@umich.edu 20848013Sbinkertn@umich.edu extwl r17, 2, r17 // a1 <- interrupt vector 20858013Sbinkertn@umich.edu bis r31, ipl_machine_check, r25 20868013Sbinkertn@umich.edu 20878013Sbinkertn@umich.edu mtpr r25, ipl // Set internal ipl 20888013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 20898013Sbinkertn@umich.edu 20908013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 20918013Sbinkertn@umich.edu mfpr r29, pt_kgp // get the kern r29 20928013Sbinkertn@umich.edu 20938013Sbinkertn@umich.edu or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 20948013Sbinkertn@umich.edu hw_rei_spe // out to interrupt dispatch routine 20958013Sbinkertn@umich.edu 20968013Sbinkertn@umich.edu 20978013Sbinkertn@umich.edu // 20988013Sbinkertn@umich.edu // The stack is pushed. Load up a0,a1,a2 and vector via entInt 20998013Sbinkertn@umich.edu // 21008013Sbinkertn@umich.edu // 21018013Sbinkertn@umich.edu ALIGN_BRANCH 21028013Sbinkertn@umich.edusys_mchk_stack_done: 21038013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 21048013Sbinkertn@umich.edu lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector 21058013Sbinkertn@umich.edu 21068013Sbinkertn@umich.edu subq r31, 1, r18 // get a -1 21078013Sbinkertn@umich.edu mfpr r25, pt_entInt 21088013Sbinkertn@umich.edu 21098013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 21108013Sbinkertn@umich.edu mtpr r25, exc_addr // load interrupt vector 21118013Sbinkertn@umich.edu 21128013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 21138013Sbinkertn@umich.edu or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 21148013Sbinkertn@umich.edu 21158013Sbinkertn@umich.edu hw_rei_spe // done 21168013Sbinkertn@umich.edu 21178013Sbinkertn@umich.edu 21188013Sbinkertn@umich.edu ALIGN_BRANCH 21198013Sbinkertn@umich.edusys_cpu_mchk_not_retryable: 21208013Sbinkertn@umich.edu mfpr r6, pt_misc 21218013Sbinkertn@umich.edu extwl r6, 4, r6 // Fetch mchk code 21228013Sbinkertn@umich.edu br r31, sys_mchk_write_logout_frame // 21238013Sbinkertn@umich.edu 21248013Sbinkertn@umich.edu 21258013Sbinkertn@umich.edu 21268013Sbinkertn@umich.edu// 21278013Sbinkertn@umich.edu//sys_double_machine_check - a machine check was started, but MCES<MCHK> was 21288013Sbinkertn@umich.edu// already set. We will now double machine check halt. 21298013Sbinkertn@umich.edu// 21308013Sbinkertn@umich.edu// pt0 - old R0 21318013Sbinkertn@umich.edu// 21328013Sbinkertn@umich.edu// 21338013Sbinkertn@umich.edu 21348013Sbinkertn@umich.eduEXPORT(sys_double_machine_check) 21358013Sbinkertn@umich.edu lda r0, hlt_c_dbl_mchk(r31) 21368013Sbinkertn@umich.edu br r31, sys_enter_console 21378013Sbinkertn@umich.edu 21388013Sbinkertn@umich.edu// 21398013Sbinkertn@umich.edu// sys_machine_check_while_in_pal - a machine check was started, 21408013Sbinkertn@umich.edu// exc_addr points to a PAL PC. We will now machine check halt. 21418013Sbinkertn@umich.edu// 21428013Sbinkertn@umich.edu// pt0 - old R0 21438013Sbinkertn@umich.edu// 21448013Sbinkertn@umich.edu// 21458013Sbinkertn@umich.edusys_machine_check_while_in_pal: 21468013Sbinkertn@umich.edu stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written 21478013Sbinkertn@umich.edu lda r0, hlt_c_mchk_from_pal(r31) 21488013Sbinkertn@umich.edu br r31, sys_enter_console 21498013Sbinkertn@umich.edu 21508013Sbinkertn@umich.edu 21518013Sbinkertn@umich.edu//ARITH and MCHK 21528013Sbinkertn@umich.edu// Check for arithmetic errors and build trap frame, 21538013Sbinkertn@umich.edu// but don't post the trap. 21548013Sbinkertn@umich.edu// on entry: 21558013Sbinkertn@umich.edu// pt10 - exc_addr 21568013Sbinkertn@umich.edu// r12 - return address 21578013Sbinkertn@umich.edu// r14 - logout frame pointer 21588013Sbinkertn@umich.edu// r13 - available 21598013Sbinkertn@umich.edu// r8,r9,r10 - available except across stq's 21608013Sbinkertn@umich.edu// pt0,1,6 - available 21618013Sbinkertn@umich.edu// 21628013Sbinkertn@umich.edu// on exit: 21638013Sbinkertn@umich.edu// pt10 - new exc_addr 21648013Sbinkertn@umich.edu// r17 = exc_mask 21658013Sbinkertn@umich.edu// r16 = exc_sum 21668013Sbinkertn@umich.edu// r14 - logout frame pointer 21678013Sbinkertn@umich.edu// 21688013Sbinkertn@umich.edu ALIGN_BRANCH 21698013Sbinkertn@umich.edusys_arith_and_mchk: 21708013Sbinkertn@umich.edu mfpr r13, ev5__exc_sum 21718013Sbinkertn@umich.edu srl r13, exc_sum_v_swc, r13 21728013Sbinkertn@umich.edu bne r13, handle_arith_and_mchk 21738013Sbinkertn@umich.edu 21748013Sbinkertn@umich.edu// XXX bugnion pvc$jsr armc, bsr=1, dest=1 21758013Sbinkertn@umich.edu ret r31, (r12) // return if no outstanding arithmetic error 21768013Sbinkertn@umich.edu 21778013Sbinkertn@umich.eduhandle_arith_and_mchk: 21788013Sbinkertn@umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel 21798013Sbinkertn@umich.edu // no virt ref for next 2 cycles 21808013Sbinkertn@umich.edu mtpr r14, pt0 21818013Sbinkertn@umich.edu 21828013Sbinkertn@umich.edu mtpr r1, pt1 // get a scratch reg 21838013Sbinkertn@umich.edu and r11, osfps_m_mode, r1 // get mode bit 21848013Sbinkertn@umich.edu 21858013Sbinkertn@umich.edu bis r11, r31, r25 // save ps 21868013Sbinkertn@umich.edu beq r1, 1f // if zero we are in kern now 21878013Sbinkertn@umich.edu 21888013Sbinkertn@umich.edu bis r31, r31, r25 // set the new ps 21898013Sbinkertn@umich.edu mtpr r30, pt_usp // save user stack 21908013Sbinkertn@umich.edu 21918013Sbinkertn@umich.edu mfpr r30, pt_ksp // get kern stack 21928013Sbinkertn@umich.edu1: 21938013Sbinkertn@umich.edu mfpr r14, exc_addr // get pc into r14 in case stack writes fault 21948013Sbinkertn@umich.edu 21958013Sbinkertn@umich.edu lda sp, 0-osfsf_c_size(sp) // allocate stack space 21968013Sbinkertn@umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 21978013Sbinkertn@umich.edu 21988013Sbinkertn@umich.edu mfpr r1, pt_entArith 21998013Sbinkertn@umich.edu stq r14, osfsf_pc(sp) // save pc 22008013Sbinkertn@umich.edu 22018013Sbinkertn@umich.edu stq r17, osfsf_a1(sp) 22028013Sbinkertn@umich.edu mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 22038013Sbinkertn@umich.edu 22048013Sbinkertn@umich.edu stq r29, osfsf_gp(sp) 22058013Sbinkertn@umich.edu stq r16, osfsf_a0(sp) // save regs 22068013Sbinkertn@umich.edu 22078013Sbinkertn@umich.edu bis r13, r31, r16 // move exc_sum to r16 22088013Sbinkertn@umich.edu stq r18, osfsf_a2(sp) 22098013Sbinkertn@umich.edu 22108013Sbinkertn@umich.edu stq r11, osfsf_ps(sp) // save ps 22118013Sbinkertn@umich.edu mfpr r29, pt_kgp // get the kern gp 22128013Sbinkertn@umich.edu 22138013Sbinkertn@umich.edu mfpr r14, pt0 // restore logout frame pointer from pt0 22148013Sbinkertn@umich.edu bis r25, r31, r11 // set new ps 22158013Sbinkertn@umich.edu 22168013Sbinkertn@umich.edu mtpr r1, pt10 // Set new PC 22178013Sbinkertn@umich.edu mfpr r1, pt1 22188013Sbinkertn@umich.edu 22198013Sbinkertn@umich.edu// XXX bugnion pvc$jsr armc, bsr=1, dest=1 22208013Sbinkertn@umich.edu ret r31, (r12) // return if no outstanding arithmetic error 22218013Sbinkertn@umich.edu 22228013Sbinkertn@umich.edu 22238013Sbinkertn@umich.edu 22248013Sbinkertn@umich.edu// sys_enter_console - Common PALcode for ENTERING console 22258013Sbinkertn@umich.edu// 22268013Sbinkertn@umich.edu// Entry: 22278013Sbinkertn@umich.edu// Entered when PAL wants to enter the console. 22288013Sbinkertn@umich.edu// usually as the result of a HALT instruction or button, 22298013Sbinkertn@umich.edu// or catastrophic error. 22308013Sbinkertn@umich.edu// 22318013Sbinkertn@umich.edu// Regs on entry... 22328013Sbinkertn@umich.edu// 22338013Sbinkertn@umich.edu// R0 = halt code 22348013Sbinkertn@umich.edu// pt0 <- r0 22358013Sbinkertn@umich.edu// 22368013Sbinkertn@umich.edu// Function: 22378013Sbinkertn@umich.edu// 22388013Sbinkertn@umich.edu// Save all readable machine state, and "call" the console 22398013Sbinkertn@umich.edu// 22408013Sbinkertn@umich.edu// Returns: 22418013Sbinkertn@umich.edu// 22428013Sbinkertn@umich.edu// 22438013Sbinkertn@umich.edu// Notes: 22448013Sbinkertn@umich.edu// 22458013Sbinkertn@umich.edu// In these routines, once the save state routine has been executed, 22468013Sbinkertn@umich.edu// the remainder of the registers become scratchable, as the only 22478013Sbinkertn@umich.edu// "valid" copy of them is the "saved" copy. 22488013Sbinkertn@umich.edu// 22498013Sbinkertn@umich.edu// Any registers or PTs that are modified before calling the save 22508013Sbinkertn@umich.edu// routine will have there data lost. The code below will save all 22518013Sbinkertn@umich.edu// state, but will loose pt 0,4,5. 22528013Sbinkertn@umich.edu// 22538013Sbinkertn@umich.edu// 22548013Sbinkertn@umich.edu 22558013Sbinkertn@umich.edu ALIGN_BLOCK 22568013Sbinkertn@umich.eduEXPORT(sys_enter_console) 22578013Sbinkertn@umich.edu mtpr r1, pt4 22588013Sbinkertn@umich.edu mtpr r3, pt5 22598013Sbinkertn@umich.edu subq r31, 1, r1 22608013Sbinkertn@umich.edu sll r1, 42, r1 22618013Sbinkertn@umich.edu ldah r1, 1(r1) 22628013Sbinkertn@umich.edu 22638013Sbinkertn@umich.edu /* taken from scrmax, seems like the obvious thing to do */ 22648013Sbinkertn@umich.edu mtpr r1, exc_addr 22658013Sbinkertn@umich.edu mfpr r1, pt4 22668013Sbinkertn@umich.edu mfpr r3, pt5 22678013Sbinkertn@umich.edu STALL 22688013Sbinkertn@umich.edu STALL 22698013Sbinkertn@umich.edu hw_rei_stall 22708013Sbinkertn@umich.edu 22718013Sbinkertn@umich.edu 22728013Sbinkertn@umich.edu// 22738013Sbinkertn@umich.edu// sys_exit_console - Common PALcode for ENTERING console 22748013Sbinkertn@umich.edu// 22758013Sbinkertn@umich.edu// Entry: 22768013Sbinkertn@umich.edu// Entered when console wants to reenter PAL. 22778013Sbinkertn@umich.edu// usually as the result of a CONTINUE. 22788013Sbinkertn@umich.edu// 22798013Sbinkertn@umich.edu// 22808013Sbinkertn@umich.edu// Regs' on entry... 22818013Sbinkertn@umich.edu// 22828013Sbinkertn@umich.edu// 22838013Sbinkertn@umich.edu// Function: 22848013Sbinkertn@umich.edu// 22858013Sbinkertn@umich.edu// Restore all readable machine state, and return to user code. 22868013Sbinkertn@umich.edu// 22878013Sbinkertn@umich.edu// 22888013Sbinkertn@umich.edu// 22898013Sbinkertn@umich.edu// 22908013Sbinkertn@umich.edu ALIGN_BLOCK 22918013Sbinkertn@umich.edusys_exit_console: 22928013Sbinkertn@umich.edu 22938013Sbinkertn@umich.edu GET_IMPURE(r1) 22948013Sbinkertn@umich.edu 22958013Sbinkertn@umich.edu // clear lock and intr_flags prior to leaving console 22968013Sbinkertn@umich.edu rc r31 // clear intr_flag 22978013Sbinkertn@umich.edu // lock flag cleared by restore_state 22988013Sbinkertn@umich.edu // TB's have been flushed 22998013Sbinkertn@umich.edu 23008013Sbinkertn@umich.edu ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3 23018013Sbinkertn@umich.edu ldq_p r1, (cns_gpr+8)(r1) // restore r1 23028013Sbinkertn@umich.edu hw_rei_stall // back to user 23038013Sbinkertn@umich.edu 23048013Sbinkertn@umich.edu 23058013Sbinkertn@umich.edu// kludge_initial_pcbb - PCB for Boot use only 23068013Sbinkertn@umich.edu 23078013Sbinkertn@umich.edu ALIGN_128 23088013Sbinkertn@umich.edu.globl kludge_initial_pcbb 23098013Sbinkertn@umich.edukludge_initial_pcbb: // PCB is 128 bytes long 23108013Sbinkertn@umich.edu nop 23118013Sbinkertn@umich.edu nop 23128013Sbinkertn@umich.edu nop 23138013Sbinkertn@umich.edu nop 23148013Sbinkertn@umich.edu 23158013Sbinkertn@umich.edu nop 23168013Sbinkertn@umich.edu nop 23178013Sbinkertn@umich.edu nop 23188013Sbinkertn@umich.edu nop 23198013Sbinkertn@umich.edu 23208013Sbinkertn@umich.edu nop 23218013Sbinkertn@umich.edu nop 23228013Sbinkertn@umich.edu nop 23238013Sbinkertn@umich.edu nop 23248013Sbinkertn@umich.edu 23258013Sbinkertn@umich.edu nop 23268013Sbinkertn@umich.edu nop 23278013Sbinkertn@umich.edu nop 23288013Sbinkertn@umich.edu nop 23298013Sbinkertn@umich.edu 23308013Sbinkertn@umich.edu 23318013Sbinkertn@umich.edu// SET_SC_BC_CTL subroutine 23328013Sbinkertn@umich.edu// 23338013Sbinkertn@umich.edu// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and 23348013Sbinkertn@umich.edu// flush the Scache 23358013Sbinkertn@umich.edu// There must be no outstanding memory references -- istream or 23368013Sbinkertn@umich.edu// dstream -- when these registers are written. EV5 prefetcher is 23378013Sbinkertn@umich.edu// difficult to turn off. So, this routine needs to be exactly 32 23388013Sbinkertn@umich.edu// instructions long// the final jmp must be in the last octaword of a 23398013Sbinkertn@umich.edu// page (prefetcher doesn't go across page) 23408013Sbinkertn@umich.edu// 23418013Sbinkertn@umich.edu// 23428013Sbinkertn@umich.edu// Register expecations: 23438013Sbinkertn@umich.edu// r0 base address of CBOX iprs 23448013Sbinkertn@umich.edu// r5 value to set sc_ctl to (flush bit is added in) 23458013Sbinkertn@umich.edu// r6 value to set bc_ctl to 23468013Sbinkertn@umich.edu// r7 value to set bc_config to 23478013Sbinkertn@umich.edu// r10 return address 23488013Sbinkertn@umich.edu// r19 old sc_ctl value 23498013Sbinkertn@umich.edu// r20 old value of bc_ctl 23508013Sbinkertn@umich.edu// r21 old value of bc_config 23518013Sbinkertn@umich.edu// r23 flush scache flag 23528013Sbinkertn@umich.edu// Register usage: 23538013Sbinkertn@umich.edu// r17 sc_ctl with flush bit cleared 23548013Sbinkertn@umich.edu// r22 loop address 23558013Sbinkertn@umich.edu// 23568013Sbinkertn@umich.edu// 23578013Sbinkertn@umich.eduset_sc_bc_ctl: 23588013Sbinkertn@umich.edu ret r31, (r10) // return to where we came from 2359