osfpal.S revision 8012
18012Ssaidi@eecs.umich.edu/* 28012Ssaidi@eecs.umich.edu * Copyright (c) 2003, 2004 38012Ssaidi@eecs.umich.edu * The Regents of The University of Michigan 48012Ssaidi@eecs.umich.edu * All Rights Reserved 58012Ssaidi@eecs.umich.edu * 68012Ssaidi@eecs.umich.edu * This code is part of the M5 simulator, developed by Nathan Binkert, 78012Ssaidi@eecs.umich.edu * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 88012Ssaidi@eecs.umich.edu * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew 98012Ssaidi@eecs.umich.edu * Schultz. 108012Ssaidi@eecs.umich.edu * 118012Ssaidi@eecs.umich.edu * Permission is granted to use, copy, create derivative works and 128012Ssaidi@eecs.umich.edu * redistribute this software and such derivative works for any 138012Ssaidi@eecs.umich.edu * purpose, so long as the copyright notice above, this grant of 148012Ssaidi@eecs.umich.edu * permission, and the disclaimer below appear in all copies made; and 158012Ssaidi@eecs.umich.edu * so long as the name of The University of Michigan is not used in 168012Ssaidi@eecs.umich.edu * any advertising or publicity pertaining to the use or distribution 178012Ssaidi@eecs.umich.edu * of this software without specific, written prior authorization. 188012Ssaidi@eecs.umich.edu * 198012Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 208012Ssaidi@eecs.umich.edu * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 218012Ssaidi@eecs.umich.edu * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 228012Ssaidi@eecs.umich.edu * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 238012Ssaidi@eecs.umich.edu * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 248012Ssaidi@eecs.umich.edu * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 258012Ssaidi@eecs.umich.edu * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 268012Ssaidi@eecs.umich.edu * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 278012Ssaidi@eecs.umich.edu * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 288012Ssaidi@eecs.umich.edu * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 298012Ssaidi@eecs.umich.edu * DAMAGES. 308012Ssaidi@eecs.umich.edu */ 318012Ssaidi@eecs.umich.edu 328012Ssaidi@eecs.umich.edu/* 338012Ssaidi@eecs.umich.eduCopyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P. 348012Ssaidi@eecs.umich.edu 358012Ssaidi@eecs.umich.eduPermission is hereby granted, free of charge, to any person obtaining a copy of 368012Ssaidi@eecs.umich.eduthis software and associated documentation files (the "Software"), to deal in 378012Ssaidi@eecs.umich.eduthe Software without restriction, including without limitation the rights to 388012Ssaidi@eecs.umich.eduuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 398012Ssaidi@eecs.umich.eduof the Software, and to permit persons to whom the Software is furnished to do 408012Ssaidi@eecs.umich.eduso, subject to the following conditions: 418012Ssaidi@eecs.umich.edu 428012Ssaidi@eecs.umich.eduThe above copyright notice and this permission notice shall be included in all 438012Ssaidi@eecs.umich.educopies or substantial portions of the Software. 448012Ssaidi@eecs.umich.edu 458012Ssaidi@eecs.umich.eduTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 468012Ssaidi@eecs.umich.eduIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 478012Ssaidi@eecs.umich.eduFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 488012Ssaidi@eecs.umich.eduAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 498012Ssaidi@eecs.umich.eduLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 508012Ssaidi@eecs.umich.eduOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 518012Ssaidi@eecs.umich.eduSOFTWARE. 528012Ssaidi@eecs.umich.edu*/ 538012Ssaidi@eecs.umich.edu 548007Ssaidi@eecs.umich.edu// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl 558007Ssaidi@eecs.umich.edu// since we don't have a mechanism to expand the data structures.... pb Nov/95 568007Ssaidi@eecs.umich.edu 578007Ssaidi@eecs.umich.edu// build_fixed_image: not sure what means 588007Ssaidi@eecs.umich.edu// real_mm to be replaced during rewrite 598007Ssaidi@eecs.umich.edu// remove_save_state remove_restore_state can be remooved to save space ?? 608007Ssaidi@eecs.umich.edu 618007Ssaidi@eecs.umich.edu 628007Ssaidi@eecs.umich.edu#include "ev5_defs.h" 638007Ssaidi@eecs.umich.edu#include "ev5_impure.h" 648007Ssaidi@eecs.umich.edu#include "ev5_alpha_defs.h" 658007Ssaidi@eecs.umich.edu#include "ev5_paldef.h" 668007Ssaidi@eecs.umich.edu#include "ev5_osfalpha_defs.h" 678007Ssaidi@eecs.umich.edu#include "fromHudsonMacros.h" 688007Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" 698007Ssaidi@eecs.umich.edu#include "dc21164FromGasSources.h" 708007Ssaidi@eecs.umich.edu 718007Ssaidi@eecs.umich.edu#ifdef SIMOS 728007Ssaidi@eecs.umich.edu#define DEBUGSTORE(c) nop 738007Ssaidi@eecs.umich.edu#else 748007Ssaidi@eecs.umich.edu#define DEBUGSTORE(c) \ 758007Ssaidi@eecs.umich.edu lda r13, c(zero) ; \ 768007Ssaidi@eecs.umich.edu bsr r25, debugstore 778007Ssaidi@eecs.umich.edu#endif 788007Ssaidi@eecs.umich.edu 798007Ssaidi@eecs.umich.edu#define DEBUG_EXC_ADDR()\ 808007Ssaidi@eecs.umich.edu bsr r25, put_exc_addr; \ 818007Ssaidi@eecs.umich.edu DEBUGSTORE(13) ; \ 828007Ssaidi@eecs.umich.edu DEBUGSTORE(10) 838007Ssaidi@eecs.umich.edu 848007Ssaidi@eecs.umich.edu#define egore 0 858007Ssaidi@eecs.umich.edu#define acore 0 868007Ssaidi@eecs.umich.edu#define beh_model 0 878007Ssaidi@eecs.umich.edu#define ev5_p2 1 888007Ssaidi@eecs.umich.edu#define ev5_p1 0 898007Ssaidi@eecs.umich.edu#define ldvpte_bug_fix 1 908007Ssaidi@eecs.umich.edu#define osf_chm_fix 0 918007Ssaidi@eecs.umich.edu 928007Ssaidi@eecs.umich.edu// Do we want to do this?? pb 938007Ssaidi@eecs.umich.edu#define spe_fix 0 948007Ssaidi@eecs.umich.edu// Do we want to do this?? pb 958007Ssaidi@eecs.umich.edu#define build_fixed_image 0 968007Ssaidi@eecs.umich.edu 978007Ssaidi@eecs.umich.edu#define ev5_pass2 988007Ssaidi@eecs.umich.edu#define enable_p4_fixups 0 998007Ssaidi@eecs.umich.edu#define osf_svmin 1 1008007Ssaidi@eecs.umich.edu#define enable_physical_console 0 1018007Ssaidi@eecs.umich.edu#define fill_err_hack 0 1028007Ssaidi@eecs.umich.edu#define icflush_on_tbix 0 1038007Ssaidi@eecs.umich.edu#define max_cpuid 1 1048007Ssaidi@eecs.umich.edu#define perfmon_debug 0 1058007Ssaidi@eecs.umich.edu#define rawhide_system 0 1068007Ssaidi@eecs.umich.edu#define rax_mode 0 1078007Ssaidi@eecs.umich.edu 1088007Ssaidi@eecs.umich.edu 1098007Ssaidi@eecs.umich.edu// This is the fix for the user-mode super page references causing the machine to crash. 1108007Ssaidi@eecs.umich.edu#if (spe_fix == 1) && (build_fixed_image==1) 1118007Ssaidi@eecs.umich.edu#define hw_rei_spe br r31, hw_rei_update_spe 1128007Ssaidi@eecs.umich.edu#else 1138007Ssaidi@eecs.umich.edu#define hw_rei_spe hw_rei 1148007Ssaidi@eecs.umich.edu#endif 1158007Ssaidi@eecs.umich.edu 1168007Ssaidi@eecs.umich.edu 1178007Ssaidi@eecs.umich.edu// redefine a few of the distribution-code names to match the Hudson gas names. 1188007Ssaidi@eecs.umich.edu// opcodes 1198007Ssaidi@eecs.umich.edu#define ldqp ldq_p 1208007Ssaidi@eecs.umich.edu#define stqp stq_p 1218007Ssaidi@eecs.umich.edu#define ldlp ldl_p 1228007Ssaidi@eecs.umich.edu#define stlp stl_p 1238007Ssaidi@eecs.umich.edu 1248007Ssaidi@eecs.umich.edu#define r0 $0 1258007Ssaidi@eecs.umich.edu#define r1 $1 1268007Ssaidi@eecs.umich.edu#define r2 $2 1278007Ssaidi@eecs.umich.edu#define r3 $3 1288007Ssaidi@eecs.umich.edu#define r4 $4 1298007Ssaidi@eecs.umich.edu#define r5 $5 1308007Ssaidi@eecs.umich.edu#define r6 $6 1318007Ssaidi@eecs.umich.edu#define r7 $7 1328007Ssaidi@eecs.umich.edu#define r8 $8 1338007Ssaidi@eecs.umich.edu#define r9 $9 1348007Ssaidi@eecs.umich.edu#define r10 $10 1358007Ssaidi@eecs.umich.edu#define r11 $11 1368007Ssaidi@eecs.umich.edu#define r12 $12 1378007Ssaidi@eecs.umich.edu#define r13 $13 1388007Ssaidi@eecs.umich.edu#define r14 $14 1398007Ssaidi@eecs.umich.edu#define r15 $15 1408007Ssaidi@eecs.umich.edu#define r16 $16 1418007Ssaidi@eecs.umich.edu#define r17 $17 1428007Ssaidi@eecs.umich.edu#define r18 $18 1438007Ssaidi@eecs.umich.edu#define r19 $19 1448007Ssaidi@eecs.umich.edu#define r20 $20 1458007Ssaidi@eecs.umich.edu#define r21 $21 1468007Ssaidi@eecs.umich.edu#define r22 $22 1478007Ssaidi@eecs.umich.edu#define r23 $23 1488007Ssaidi@eecs.umich.edu#define r24 $24 1498007Ssaidi@eecs.umich.edu#define r25 $25 1508007Ssaidi@eecs.umich.edu#define r26 $26 1518007Ssaidi@eecs.umich.edu#define r27 $27 1528007Ssaidi@eecs.umich.edu#define r28 $28 1538007Ssaidi@eecs.umich.edu#define r29 $29 1548007Ssaidi@eecs.umich.edu#define r30 $30 1558007Ssaidi@eecs.umich.edu#define r31 $31 1568007Ssaidi@eecs.umich.edu 1578007Ssaidi@eecs.umich.edu// .title "EV5 OSF PAL" 1588007Ssaidi@eecs.umich.edu// .ident "V1.18" 1598007Ssaidi@eecs.umich.edu// 1608007Ssaidi@eecs.umich.edu//**************************************************************************** 1618007Ssaidi@eecs.umich.edu//* * 1628007Ssaidi@eecs.umich.edu//* Copyright (c) 1992, 1993, 1994, 1995 * 1638007Ssaidi@eecs.umich.edu//* by DIGITAL Equipment Corporation, Maynard, Mass. * 1648007Ssaidi@eecs.umich.edu//* * 1658007Ssaidi@eecs.umich.edu//* This software is furnished under a license and may be used and copied * 1668007Ssaidi@eecs.umich.edu//* only in accordance with the terms of such license and with the * 1678007Ssaidi@eecs.umich.edu//* inclusion of the above copyright notice. This software or any other * 1688007Ssaidi@eecs.umich.edu//* copies thereof may not be provided or otherwise made available to any * 1698007Ssaidi@eecs.umich.edu//* other person. No title to and ownership of the software is hereby * 1708007Ssaidi@eecs.umich.edu//* transferred. * 1718007Ssaidi@eecs.umich.edu//* * 1728007Ssaidi@eecs.umich.edu//* The information in this software is subject to change without notice * 1738007Ssaidi@eecs.umich.edu//* and should not be construed as a commitment by DIGITAL Equipment * 1748007Ssaidi@eecs.umich.edu//* Corporation. * 1758007Ssaidi@eecs.umich.edu//* * 1768007Ssaidi@eecs.umich.edu//* DIGITAL assumes no responsibility for the use or reliability of its * 1778007Ssaidi@eecs.umich.edu//* software on equipment which is not supplied by DIGITAL. * 1788007Ssaidi@eecs.umich.edu//* * 1798007Ssaidi@eecs.umich.edu//**************************************************************************** 1808007Ssaidi@eecs.umich.edu 1818007Ssaidi@eecs.umich.edu// .sbttl "Edit History" 1828007Ssaidi@eecs.umich.edu//+ 1838007Ssaidi@eecs.umich.edu// Who Rev When What 1848007Ssaidi@eecs.umich.edu// ------------ --- ----------- -------------------------------- 1858007Ssaidi@eecs.umich.edu// DB 0.0 03-Nov-1992 Start 1868007Ssaidi@eecs.umich.edu// DB 0.1 28-Dec-1992 add swpctx 1878007Ssaidi@eecs.umich.edu// DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug 1888007Ssaidi@eecs.umich.edu// DB 0.3 11-Jan-1993 rearrange trap entry points 1898007Ssaidi@eecs.umich.edu// DB 0.4 01-Feb-1993 add tbi 1908007Ssaidi@eecs.umich.edu// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal 1918007Ssaidi@eecs.umich.edu// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14) 1928007Ssaidi@eecs.umich.edu// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC 1938007Ssaidi@eecs.umich.edu// Bug: typo on register number for store in wrunique 1948007Ssaidi@eecs.umich.edu// Bug: rti to kern uses r16 as scratch 1958007Ssaidi@eecs.umich.edu// Bug: callsys saving wrong value in pt_usp 1968007Ssaidi@eecs.umich.edu// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp 1978007Ssaidi@eecs.umich.edu// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice 1988007Ssaidi@eecs.umich.edu// Bug: rti stl_c could corrupt the stack 1998007Ssaidi@eecs.umich.edu// Bug: unaligned returning wrong value in r17 (or should be and) 2008007Ssaidi@eecs.umich.edu// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt 2018007Ssaidi@eecs.umich.edu// DB 0.11 23-Feb-1993 Turn caches on in reset flow 2028007Ssaidi@eecs.umich.edu// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow 2038007Ssaidi@eecs.umich.edu// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses 2048007Ssaidi@eecs.umich.edu// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS 2058007Ssaidi@eecs.umich.edu// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES 2068007Ssaidi@eecs.umich.edu// DB 0.16 12-May-1993 Update reset 2078007Ssaidi@eecs.umich.edu// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows 2088007Ssaidi@eecs.umich.edu// Bug: in wrmces, not clearing DPC, DSC 2098007Ssaidi@eecs.umich.edu// Update swppal 2108007Ssaidi@eecs.umich.edu// Add pal bugchecks, pal_save_state, pal_restore_state 2118007Ssaidi@eecs.umich.edu// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps. 2128007Ssaidi@eecs.umich.edu// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn 2138007Ssaidi@eecs.umich.edu// DB 0.18 26-May-1993 PVC fixes 2148007Ssaidi@eecs.umich.edu// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores 2158007Ssaidi@eecs.umich.edu// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl 2168007Ssaidi@eecs.umich.edu// Bug: exc_addr was being loaded before stores that could dtb_miss in the following 2178007Ssaidi@eecs.umich.edu// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN 2188007Ssaidi@eecs.umich.edu// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines: 2198007Ssaidi@eecs.umich.edu// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN:: 2208007Ssaidi@eecs.umich.edu// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler: 2218007Ssaidi@eecs.umich.edu// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN:: 2228007Ssaidi@eecs.umich.edu// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles 2238007Ssaidi@eecs.umich.edu// JM 0.22 28-jul-1993 Add WRIPIR instruction 2248007Ssaidi@eecs.umich.edu// JM 0.23 05-aug-1993 Bump version number for release 2258007Ssaidi@eecs.umich.edu// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation 2268007Ssaidi@eecs.umich.edu// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals; 2278007Ssaidi@eecs.umich.edu// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode), 2288007Ssaidi@eecs.umich.edu// and SWPCTX 2298007Ssaidi@eecs.umich.edu// JM 0.26 07-oct-1993 Re-implement pal_version 2308007Ssaidi@eecs.umich.edu// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM 2318007Ssaidi@eecs.umich.edu// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush 2328007Ssaidi@eecs.umich.edu// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead 2338007Ssaidi@eecs.umich.edu// of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld. 2348007Ssaidi@eecs.umich.edu// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys 2358007Ssaidi@eecs.umich.edu// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0 2368007Ssaidi@eecs.umich.edu// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0 2378007Ssaidi@eecs.umich.edu// JM 0.33 24-nov-1993 save/restore_state - 2388007Ssaidi@eecs.umich.edu// BUG: use ivptbr to restore mvptbr 2398007Ssaidi@eecs.umich.edu// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit 2408007Ssaidi@eecs.umich.edu// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors 2418007Ssaidi@eecs.umich.edu// JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case 2428007Ssaidi@eecs.umich.edu// BUG: generate ksnv halt when tb miss on kernel stack accesses 2438007Ssaidi@eecs.umich.edu// save exc_addr in r14 for invalid_dpte stack builder 2448007Ssaidi@eecs.umich.edu// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in 2458007Ssaidi@eecs.umich.edu// the same shadow 2468007Ssaidi@eecs.umich.edu// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS 2478007Ssaidi@eecs.umich.edu// New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen 2488007Ssaidi@eecs.umich.edu// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions 2498007Ssaidi@eecs.umich.edu// Hide impure area manipulations in macros 2508007Ssaidi@eecs.umich.edu// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st 2518007Ssaidi@eecs.umich.edu// Add some pvc_violate statements 2528007Ssaidi@eecs.umich.edu// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality; 2538007Ssaidi@eecs.umich.edu// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments 2548007Ssaidi@eecs.umich.edu// Add code to ensure fen bit set in icsr before ldt 2558007Ssaidi@eecs.umich.edu// conditionally compile rax_more_reset out. 2568007Ssaidi@eecs.umich.edu// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here 2578007Ssaidi@eecs.umich.edu// move rax reset stuff to ev5_osf_system_pal.m64 2588007Ssaidi@eecs.umich.edu// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow 2598007Ssaidi@eecs.umich.edu// and performance monitoring bits 2608007Ssaidi@eecs.umich.edu// Change to save_state routine to save more iprs. 2618007Ssaidi@eecs.umich.edu// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in 2628007Ssaidi@eecs.umich.edu// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems) 2638007Ssaidi@eecs.umich.edu// remove_save_state,remove_restore_state;fix new pvc violation in save_state 2648007Ssaidi@eecs.umich.edu// JM 0.42 22-feb-1994 BUG: save_state overwriting r3 2658007Ssaidi@eecs.umich.edu// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr 2668007Ssaidi@eecs.umich.edu// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions 2678007Ssaidi@eecs.umich.edu// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem) 2688007Ssaidi@eecs.umich.edu// New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles 2698007Ssaidi@eecs.umich.edu// Add exc_sum and exc_mask to pal_save_state (not restore) 2708007Ssaidi@eecs.umich.edu// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure 2718007Ssaidi@eecs.umich.edu// area. 2728007Ssaidi@eecs.umich.edu// Add performance counter support to swpctx and wrperfmon 2738007Ssaidi@eecs.umich.edu// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix) 2748007Ssaidi@eecs.umich.edu// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts 2758007Ssaidi@eecs.umich.edu// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is 2768007Ssaidi@eecs.umich.edu// taken in the interrupt flow, stack is pushed twice. 2778007Ssaidi@eecs.umich.edu// SWPPAL - update to support ECO 59 to allow 0 as a valid address 2788007Ssaidi@eecs.umich.edu// Add itb flush to save/restore state routines 2798007Ssaidi@eecs.umich.edu// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but 2808007Ssaidi@eecs.umich.edu// conforms to itbia restriction. 2818007Ssaidi@eecs.umich.edu// Added enable_physical_console flag (for enter/exit console routines only) 2828007Ssaidi@eecs.umich.edu// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a 2838007Ssaidi@eecs.umich.edu// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and 2848007Ssaidi@eecs.umich.edu// nmiss_fetch_err to nmiss_fetch_ldr31_err. 2858007Ssaidi@eecs.umich.edu// JM 1.00 1-aug-1994 Add pass2 support (swpctx) 2868007Ssaidi@eecs.umich.edu// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2 2878007Ssaidi@eecs.umich.edu// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2) 2888007Ssaidi@eecs.umich.edu// Moved perfmon code here from system file. 2898007Ssaidi@eecs.umich.edu// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1) 2908007Ssaidi@eecs.umich.edu// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit. 2918007Ssaidi@eecs.umich.edu// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change 2928007Ssaidi@eecs.umich.edu// after ISR read, but we won't catch the ISR update. reverse order 2938007Ssaidi@eecs.umich.edu// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31 2948007Ssaidi@eecs.umich.edu// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code) 2958007Ssaidi@eecs.umich.edu// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to 2968007Ssaidi@eecs.umich.edu// DTBMISS_SINGLE if not in palmode. 2978007Ssaidi@eecs.umich.edu// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame 2988007Ssaidi@eecs.umich.edu// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox 2998007Ssaidi@eecs.umich.edu// superpage mode in User mode and re-enable in kernel mode. 3008007Ssaidi@eecs.umich.edu// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this. 3018007Ssaidi@eecs.umich.edu// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2 3028007Ssaidi@eecs.umich.edu// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid 3038007Ssaidi@eecs.umich.edu// cpu bug. 3048007Ssaidi@eecs.umich.edu// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state 3058007Ssaidi@eecs.umich.edu// ES 1.13 17-mar-1995 Refine osf_chm_fix 3068007Ssaidi@eecs.umich.edu// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix 3078007Ssaidi@eecs.umich.edu// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state 3088007Ssaidi@eecs.umich.edu// Force pvc checking of exit_console 3098007Ssaidi@eecs.umich.edu// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0 3108007Ssaidi@eecs.umich.edu// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting) 3118007Ssaidi@eecs.umich.edu// instead of xor to maintain previous mode in pt_misc 3128007Ssaidi@eecs.umich.edu// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does 3138007Ssaidi@eecs.umich.edu// not have pme set. The bits in icsr maintain the master enable state. 3148007Ssaidi@eecs.umich.edu// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable 3158007Ssaidi@eecs.umich.edu// 3168007Ssaidi@eecs.umich.edu#define vmaj 1 3178007Ssaidi@eecs.umich.edu#define vmin 18 3188007Ssaidi@eecs.umich.edu#define vms_pal 1 3198007Ssaidi@eecs.umich.edu#define osf_pal 2 3208007Ssaidi@eecs.umich.edu#define pal_type osf_pal 3218007Ssaidi@eecs.umich.edu#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) 3228007Ssaidi@eecs.umich.edu//- 3238007Ssaidi@eecs.umich.edu 3248007Ssaidi@eecs.umich.edu// .sbttl "PALtemp register usage" 3258007Ssaidi@eecs.umich.edu 3268007Ssaidi@eecs.umich.edu//+ 3278007Ssaidi@eecs.umich.edu// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage 3288007Ssaidi@eecs.umich.edu// for these PALtemps: 3298007Ssaidi@eecs.umich.edu// 3308007Ssaidi@eecs.umich.edu// pt0 local scratch 3318007Ssaidi@eecs.umich.edu// pt1 local scratch 3328007Ssaidi@eecs.umich.edu// pt2 entUna pt_entUna 3338007Ssaidi@eecs.umich.edu// pt3 CPU specific impure area pointer pt_impure 3348007Ssaidi@eecs.umich.edu// pt4 memory management temp 3358007Ssaidi@eecs.umich.edu// pt5 memory management temp 3368007Ssaidi@eecs.umich.edu// pt6 memory management temp 3378007Ssaidi@eecs.umich.edu// pt7 entIF pt_entIF 3388007Ssaidi@eecs.umich.edu// pt8 intmask pt_intmask 3398007Ssaidi@eecs.umich.edu// pt9 entSys pt_entSys 3408007Ssaidi@eecs.umich.edu// pt10 3418007Ssaidi@eecs.umich.edu// pt11 entInt pt_entInt 3428007Ssaidi@eecs.umich.edu// pt12 entArith pt_entArith 3438007Ssaidi@eecs.umich.edu// pt13 reserved for system specific PAL 3448007Ssaidi@eecs.umich.edu// pt14 reserved for system specific PAL 3458007Ssaidi@eecs.umich.edu// pt15 reserved for system specific PAL 3468007Ssaidi@eecs.umich.edu// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces 3478007Ssaidi@eecs.umich.edu// pt17 sysval pt_sysval 3488007Ssaidi@eecs.umich.edu// pt18 usp pt_usp 3498007Ssaidi@eecs.umich.edu// pt19 ksp pt_ksp 3508007Ssaidi@eecs.umich.edu// pt20 PTBR pt_ptbr 3518007Ssaidi@eecs.umich.edu// pt21 entMM pt_entMM 3528007Ssaidi@eecs.umich.edu// pt22 kgp pt_kgp 3538007Ssaidi@eecs.umich.edu// pt23 PCBB pt_pcbb 3548007Ssaidi@eecs.umich.edu// 3558007Ssaidi@eecs.umich.edu//- 3568007Ssaidi@eecs.umich.edu 3578007Ssaidi@eecs.umich.edu// .sbttl "PALshadow register usage" 3588007Ssaidi@eecs.umich.edu// 3598007Ssaidi@eecs.umich.edu//+ 3608007Ssaidi@eecs.umich.edu// 3618007Ssaidi@eecs.umich.edu// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1. 3628007Ssaidi@eecs.umich.edu// This maps the OSF PAL usage of R8 - R14 and R25: 3638007Ssaidi@eecs.umich.edu// 3648007Ssaidi@eecs.umich.edu// r8 ITBmiss/DTBmiss scratch 3658007Ssaidi@eecs.umich.edu// r9 ITBmiss/DTBmiss scratch 3668007Ssaidi@eecs.umich.edu// r10 ITBmiss/DTBmiss scratch 3678007Ssaidi@eecs.umich.edu// r11 PS 3688007Ssaidi@eecs.umich.edu// r12 local scratch 3698007Ssaidi@eecs.umich.edu// r13 local scratch 3708007Ssaidi@eecs.umich.edu// r14 local scratch 3718007Ssaidi@eecs.umich.edu// r25 local scratch 3728007Ssaidi@eecs.umich.edu// 3738007Ssaidi@eecs.umich.edu// 3748007Ssaidi@eecs.umich.edu//- 3758007Ssaidi@eecs.umich.edu 3768007Ssaidi@eecs.umich.edu// .sbttl "ALPHA symbol definitions" 3778007Ssaidi@eecs.umich.edu// _OSF_PSDEF GLOBAL 3788007Ssaidi@eecs.umich.edu// _OSF_PTEDEF GLOBAL 3798007Ssaidi@eecs.umich.edu// _OSF_VADEF GLOBAL 3808007Ssaidi@eecs.umich.edu// _OSF_PCBDEF GLOBAL 3818007Ssaidi@eecs.umich.edu// _OSF_SFDEF GLOBAL 3828007Ssaidi@eecs.umich.edu// _OSF_MMCSR_DEF GLOBAL 3838007Ssaidi@eecs.umich.edu// _SCBDEF GLOBAL 3848007Ssaidi@eecs.umich.edu// _FRMDEF GLOBAL 3858007Ssaidi@eecs.umich.edu// _EXSDEF GLOBAL 3868007Ssaidi@eecs.umich.edu// _OSF_A0_DEF GLOBAL 3878007Ssaidi@eecs.umich.edu// _MCESDEF GLOBAL 3888007Ssaidi@eecs.umich.edu 3898007Ssaidi@eecs.umich.edu// .sbttl "EV5 symbol definitions" 3908007Ssaidi@eecs.umich.edu 3918007Ssaidi@eecs.umich.edu// _EV5DEF 3928007Ssaidi@eecs.umich.edu// _PALTEMP 3938007Ssaidi@eecs.umich.edu// _MM_STAT_DEF 3948007Ssaidi@eecs.umich.edu// _EV5_MM 3958007Ssaidi@eecs.umich.edu// _EV5_IPLDEF 3968007Ssaidi@eecs.umich.edu 3978007Ssaidi@eecs.umich.edu// _HALT_CODES GLOBAL 3988007Ssaidi@eecs.umich.edu// _MCHK_CODES GLOBAL 3998007Ssaidi@eecs.umich.edu 4008007Ssaidi@eecs.umich.edu// _PAL_IMPURE 4018007Ssaidi@eecs.umich.edu// _PAL_LOGOUT 4028007Ssaidi@eecs.umich.edu 4038007Ssaidi@eecs.umich.edu 4048007Ssaidi@eecs.umich.edu 4058007Ssaidi@eecs.umich.edu 4068007Ssaidi@eecs.umich.edu// .sbttl "PALcode configuration options" 4078007Ssaidi@eecs.umich.edu 4088007Ssaidi@eecs.umich.edu// There are a number of options that may be assembled into this version of 4098007Ssaidi@eecs.umich.edu// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit 4108007Ssaidi@eecs.umich.edu// the following). The options that can be adjusted cause the resultant PALcode 4118007Ssaidi@eecs.umich.edu// to reflect the desired target system. 4128007Ssaidi@eecs.umich.edu 4138007Ssaidi@eecs.umich.edu 4148007Ssaidi@eecs.umich.edu#define osfpal 1 // This is the PALcode for OSF. 4158007Ssaidi@eecs.umich.edu 4168007Ssaidi@eecs.umich.edu#ifndef rawhide_system 4178007Ssaidi@eecs.umich.edu 4188007Ssaidi@eecs.umich.edu#define rawhide_system 0 4198007Ssaidi@eecs.umich.edu#endif 4208007Ssaidi@eecs.umich.edu 4218007Ssaidi@eecs.umich.edu 4228007Ssaidi@eecs.umich.edu#ifndef real_mm 4238007Ssaidi@eecs.umich.edu// Page table translation vs 1-1 mapping 4248007Ssaidi@eecs.umich.edu#define real_mm 1 4258007Ssaidi@eecs.umich.edu#endif 4268007Ssaidi@eecs.umich.edu 4278007Ssaidi@eecs.umich.edu 4288007Ssaidi@eecs.umich.edu#ifndef rax_mode 4298007Ssaidi@eecs.umich.edu 4308007Ssaidi@eecs.umich.edu#define rax_mode 0 4318007Ssaidi@eecs.umich.edu#endif 4328007Ssaidi@eecs.umich.edu 4338007Ssaidi@eecs.umich.edu#ifndef egore 4348007Ssaidi@eecs.umich.edu// End of reset flow starts a program at 200000(hex). 4358007Ssaidi@eecs.umich.edu#define egore 1 4368007Ssaidi@eecs.umich.edu#endif 4378007Ssaidi@eecs.umich.edu 4388007Ssaidi@eecs.umich.edu#ifndef acore 4398007Ssaidi@eecs.umich.edu// End of reset flow starts a program at 40000(hex). 4408007Ssaidi@eecs.umich.edu#define acore 0 4418007Ssaidi@eecs.umich.edu#endif 4428007Ssaidi@eecs.umich.edu 4438007Ssaidi@eecs.umich.edu 4448007Ssaidi@eecs.umich.edu// assume acore+egore+rax_mode lt 2 // Assertion checker 4458007Ssaidi@eecs.umich.edu 4468007Ssaidi@eecs.umich.edu#ifndef beh_model 4478007Ssaidi@eecs.umich.edu// EV5 behavioral model specific code 4488007Ssaidi@eecs.umich.edu#define beh_model 1 4498007Ssaidi@eecs.umich.edu#endif 4508007Ssaidi@eecs.umich.edu 4518007Ssaidi@eecs.umich.edu#ifndef init_cbox 4528007Ssaidi@eecs.umich.edu// Reset flow init of Bcache and Scache 4538007Ssaidi@eecs.umich.edu#define init_cbox 1 4548007Ssaidi@eecs.umich.edu#endif 4558007Ssaidi@eecs.umich.edu 4568007Ssaidi@eecs.umich.edu#ifndef disable_crd 4578007Ssaidi@eecs.umich.edu// Decides whether the reset flow will disable 4588007Ssaidi@eecs.umich.edu#define disable_crd 0 4598007Ssaidi@eecs.umich.edu#endif 4608007Ssaidi@eecs.umich.edu 4618007Ssaidi@eecs.umich.edu // correctable read interrupts via ICSR 4628007Ssaidi@eecs.umich.edu#ifndef perfmon_debug 4638007Ssaidi@eecs.umich.edu#define perfmon_debug 0 4648007Ssaidi@eecs.umich.edu#endif 4658007Ssaidi@eecs.umich.edu 4668007Ssaidi@eecs.umich.edu#ifndef icflush_on_tbix 4678007Ssaidi@eecs.umich.edu#define icflush_on_tbix 0 4688007Ssaidi@eecs.umich.edu#endif 4698007Ssaidi@eecs.umich.edu 4708007Ssaidi@eecs.umich.edu#ifndef remove_restore_state 4718007Ssaidi@eecs.umich.edu#define remove_restore_state 0 4728007Ssaidi@eecs.umich.edu#endif 4738007Ssaidi@eecs.umich.edu 4748007Ssaidi@eecs.umich.edu#ifndef remove_save_state 4758007Ssaidi@eecs.umich.edu#define remove_save_state 0 4768007Ssaidi@eecs.umich.edu#endif 4778007Ssaidi@eecs.umich.edu 4788007Ssaidi@eecs.umich.edu#ifndef enable_physical_console 4798007Ssaidi@eecs.umich.edu#define enable_physical_console 0 4808007Ssaidi@eecs.umich.edu#endif 4818007Ssaidi@eecs.umich.edu 4828007Ssaidi@eecs.umich.edu#ifndef ev5_p1 4838007Ssaidi@eecs.umich.edu#define ev5_p1 0 4848007Ssaidi@eecs.umich.edu#endif 4858007Ssaidi@eecs.umich.edu 4868007Ssaidi@eecs.umich.edu#ifndef ev5_p2 4878007Ssaidi@eecs.umich.edu#define ev5_p2 1 4888007Ssaidi@eecs.umich.edu#endif 4898007Ssaidi@eecs.umich.edu 4908007Ssaidi@eecs.umich.edu// assume ev5_p1+ev5_p2 eq 1 4918007Ssaidi@eecs.umich.edu 4928007Ssaidi@eecs.umich.edu#ifndef ldvpte_bug_fix 4938007Ssaidi@eecs.umich.edu#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow. 4948007Ssaidi@eecs.umich.edu#endif 4958007Ssaidi@eecs.umich.edu 4968007Ssaidi@eecs.umich.edu#ifndef spe_fix 4978007Ssaidi@eecs.umich.edu// If set, disable super-page mode in user mode and re-enable 4988007Ssaidi@eecs.umich.edu#define spe_fix 0 4998007Ssaidi@eecs.umich.edu#endif 5008007Ssaidi@eecs.umich.edu // in kernel. Workaround for cpu bug. 5018007Ssaidi@eecs.umich.edu#ifndef build_fixed_image 5028007Ssaidi@eecs.umich.edu#define build_fixed_image 0 5038007Ssaidi@eecs.umich.edu#endif 5048007Ssaidi@eecs.umich.edu 5058007Ssaidi@eecs.umich.edu 5068007Ssaidi@eecs.umich.edu#ifndef fill_err_hack 5078007Ssaidi@eecs.umich.edu// If set, disable fill_error mode in user mode and re-enable 5088007Ssaidi@eecs.umich.edu#define fill_err_hack 0 5098007Ssaidi@eecs.umich.edu#endif 5108007Ssaidi@eecs.umich.edu 5118007Ssaidi@eecs.umich.edu // in kernel. Workaround for cpu bug. 5128007Ssaidi@eecs.umich.edu 5138007Ssaidi@eecs.umich.edu// .macro hw_rei_spe 5148007Ssaidi@eecs.umich.edu// .iif eq spe_fix, hw_rei 5158007Ssaidi@eecs.umich.edu//#if spe_fix != 0 5168007Ssaidi@eecs.umich.edu// 5178007Ssaidi@eecs.umich.edu// 5188007Ssaidi@eecs.umich.edu//#define hw_rei_chm_count hw_rei_chm_count + 1 5198007Ssaidi@eecs.umich.edu// p4_fixup_label \hw_rei_chm_count 5208007Ssaidi@eecs.umich.edu// .iif eq build_fixed_image, br r31, hw_rei_update_spe 5218007Ssaidi@eecs.umich.edu// .iif ne build_fixed_image, hw_rei 5228007Ssaidi@eecs.umich.edu//#endif 5238007Ssaidi@eecs.umich.edu// 5248007Ssaidi@eecs.umich.edu// .endm 5258007Ssaidi@eecs.umich.edu 5268007Ssaidi@eecs.umich.edu// Add flag "osf_chm_fix" to enable dcache in user mode only 5278007Ssaidi@eecs.umich.edu// to avoid cpu bug. 5288007Ssaidi@eecs.umich.edu 5298007Ssaidi@eecs.umich.edu#ifndef osf_chm_fix 5308007Ssaidi@eecs.umich.edu// If set, enable D-Cache in 5318007Ssaidi@eecs.umich.edu#define osf_chm_fix 0 5328007Ssaidi@eecs.umich.edu#endif 5338007Ssaidi@eecs.umich.edu 5348007Ssaidi@eecs.umich.edu#if osf_chm_fix != 0 5358007Ssaidi@eecs.umich.edu// user mode only. 5368007Ssaidi@eecs.umich.edu#define hw_rei_chm_count 0 5378007Ssaidi@eecs.umich.edu#endif 5388007Ssaidi@eecs.umich.edu 5398007Ssaidi@eecs.umich.edu#if osf_chm_fix != 0 5408007Ssaidi@eecs.umich.edu 5418007Ssaidi@eecs.umich.edu#define hw_rei_stall_chm_count 0 5428007Ssaidi@eecs.umich.edu#endif 5438007Ssaidi@eecs.umich.edu 5448007Ssaidi@eecs.umich.edu#ifndef enable_p4_fixups 5458007Ssaidi@eecs.umich.edu 5468007Ssaidi@eecs.umich.edu#define enable_p4_fixups 0 5478007Ssaidi@eecs.umich.edu#endif 5488007Ssaidi@eecs.umich.edu 5498007Ssaidi@eecs.umich.edu // If set, do EV5 Pass 4 fixups 5508007Ssaidi@eecs.umich.edu#if spe_fix == 0 5518007Ssaidi@eecs.umich.edu 5528007Ssaidi@eecs.umich.edu#define osf_chm_fix 0 5538007Ssaidi@eecs.umich.edu#endif 5548007Ssaidi@eecs.umich.edu 5558007Ssaidi@eecs.umich.edu#if spe_fix == 0 5568007Ssaidi@eecs.umich.edu 5578007Ssaidi@eecs.umich.edu#define enable_p4_fixups 0 5588007Ssaidi@eecs.umich.edu#endif 5598007Ssaidi@eecs.umich.edu 5608007Ssaidi@eecs.umich.edu // Only allow fixups if fix enabled 5618007Ssaidi@eecs.umich.edu 5628007Ssaidi@eecs.umich.edu //Turn off fill_errors and MEM_NEM in user mode 5638007Ssaidi@eecs.umich.edu// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_ 5648007Ssaidi@eecs.umich.edu// //save r22,r23,r24 5658007Ssaidi@eecs.umich.edu// stqp r22, 0x150(r31) //add 5668007Ssaidi@eecs.umich.edu// stqp r23, 0x158(r31) //contents 5678007Ssaidi@eecs.umich.edu// stqp r24, 0x160(r31) //bit mask 5688007Ssaidi@eecs.umich.edu// 5698007Ssaidi@eecs.umich.edu// lda r22, 0x82(r31) 5708007Ssaidi@eecs.umich.edu// ldah r22, 0x8740(r22) 5718007Ssaidi@eecs.umich.edu// sll r22, 8, r22 5728007Ssaidi@eecs.umich.edu// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK 5738007Ssaidi@eecs.umich.edu// bis r23,r31,r23 5748007Ssaidi@eecs.umich.edu// 5758007Ssaidi@eecs.umich.edu// lda r24, 0x8(r31) // r24 <- MEM_NEM bit 5768007Ssaidi@eecs.umich.edu// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode 5778007Ssaidi@eecs.umich.edu// bic r23, r24, r23 // set fillerr_en bit 5788007Ssaidi@eecs.umich.edu// br r31, L20_ // ELSE 5798007Ssaidi@eecs.umich.edu//L10_: bis r23, r24, r23 // clear fillerr_en bit 5808007Ssaidi@eecs.umich.edu//L20_: // ENDIF 5818007Ssaidi@eecs.umich.edu// 5828007Ssaidi@eecs.umich.edu// stlp r23, 0x80(r22) // write back the CIA_MASK register 5838007Ssaidi@eecs.umich.edu// mb 5848007Ssaidi@eecs.umich.edu// ldlp r23, 0x80(r22) 5858007Ssaidi@eecs.umich.edu// bis r23,r31,r23 5868007Ssaidi@eecs.umich.edu// mb 5878007Ssaidi@eecs.umich.edu// 5888007Ssaidi@eecs.umich.edu// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL 5898007Ssaidi@eecs.umich.edu// ldah r22, 0x8740(r22) 5908007Ssaidi@eecs.umich.edu// sll r22, 8, r22 5918007Ssaidi@eecs.umich.edu// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL 5928007Ssaidi@eecs.umich.edu// bis r23,r31,r23 5938007Ssaidi@eecs.umich.edu// 5948007Ssaidi@eecs.umich.edu// 5958007Ssaidi@eecs.umich.edu// lda r24, 0x400(r31) // r9 <- fillerr_en bit 5968007Ssaidi@eecs.umich.edu// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode 5978007Ssaidi@eecs.umich.edu// bic r23, r24, r23 // set fillerr_en bit 5988007Ssaidi@eecs.umich.edu// br r31, L40_ // ELSE 5998007Ssaidi@eecs.umich.edu//L30_: bis r23, r24, r23 // clear fillerr_en bit 6008007Ssaidi@eecs.umich.edu//L40_: // ENDIF 6018007Ssaidi@eecs.umich.edu// 6028007Ssaidi@eecs.umich.edu// stlp r23, 0(r22) // write back the CIA_CTRL register 6038007Ssaidi@eecs.umich.edu// mb 6048007Ssaidi@eecs.umich.edu// ldlp r23, 0(r22) 6058007Ssaidi@eecs.umich.edu// bis r23,r31,r23 6068007Ssaidi@eecs.umich.edu// mb 6078007Ssaidi@eecs.umich.edu// 6088007Ssaidi@eecs.umich.edu// //restore r22,r23,r24 6098007Ssaidi@eecs.umich.edu// ldqp r22, 0x150(r31) 6108007Ssaidi@eecs.umich.edu// ldqp r23, 0x158(r31) 6118007Ssaidi@eecs.umich.edu// ldqp r24, 0x160(r31) 6128007Ssaidi@eecs.umich.edu// 6138007Ssaidi@eecs.umich.edu// .endm 6148007Ssaidi@eecs.umich.edu 6158007Ssaidi@eecs.umich.edu// multiprocessor support can be enabled for a max of n processors by 6168007Ssaidi@eecs.umich.edu// setting the following to the number of processors on the system. 6178007Ssaidi@eecs.umich.edu// Note that this is really the max cpuid. 6188007Ssaidi@eecs.umich.edu 6198007Ssaidi@eecs.umich.edu#ifndef max_cpuid 6208007Ssaidi@eecs.umich.edu#define max_cpuid 8 6218007Ssaidi@eecs.umich.edu#endif 6228007Ssaidi@eecs.umich.edu 6238007Ssaidi@eecs.umich.edu#ifndef osf_svmin // platform specific palcode version number 6248007Ssaidi@eecs.umich.edu#define osf_svmin 0 6258007Ssaidi@eecs.umich.edu#endif 6268007Ssaidi@eecs.umich.edu 6278007Ssaidi@eecs.umich.edu 6288007Ssaidi@eecs.umich.edu#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) 6298007Ssaidi@eecs.umich.edu 6308007Ssaidi@eecs.umich.edu// .mcall ldqp // override macro64 definition with macro from library 6318007Ssaidi@eecs.umich.edu// .mcall stqp // override macro64 definition with macro from library 6328007Ssaidi@eecs.umich.edu 6338007Ssaidi@eecs.umich.edu 6348007Ssaidi@eecs.umich.edu// .psect _pal,mix 6358007Ssaidi@eecs.umich.edu// huh pb pal_base: 6368007Ssaidi@eecs.umich.edu// huh pb #define current_block_base . - pal_base 6378007Ssaidi@eecs.umich.edu 6388007Ssaidi@eecs.umich.edu// .sbttl "RESET - Reset Trap Entry Point" 6398007Ssaidi@eecs.umich.edu//+ 6408007Ssaidi@eecs.umich.edu// RESET - offset 0000 6418007Ssaidi@eecs.umich.edu// Entry: 6428007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on reset, or branched to 6438007Ssaidi@eecs.umich.edu// on swppal. 6448007Ssaidi@eecs.umich.edu// 6458007Ssaidi@eecs.umich.edu// r0 = whami 6468007Ssaidi@eecs.umich.edu// r1 = pal_base 6478007Ssaidi@eecs.umich.edu// r2 = base of scratch area 6488007Ssaidi@eecs.umich.edu// r3 = halt code 6498007Ssaidi@eecs.umich.edu// 6508007Ssaidi@eecs.umich.edu// 6518007Ssaidi@eecs.umich.edu// Function: 6528007Ssaidi@eecs.umich.edu// 6538007Ssaidi@eecs.umich.edu//- 6548007Ssaidi@eecs.umich.edu 6558007Ssaidi@eecs.umich.edu .text 0 6568007Ssaidi@eecs.umich.edu . = 0x0000 6578007Ssaidi@eecs.umich.edu .globl Pal_Base 6588007Ssaidi@eecs.umich.eduPal_Base: 6598007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_RESET_ENTRY) 6608007Ssaidi@eecs.umich.eduTrap_Reset: 6618007Ssaidi@eecs.umich.edu nop 6628007Ssaidi@eecs.umich.edu#ifdef SIMOS 6638007Ssaidi@eecs.umich.edu /* 6648007Ssaidi@eecs.umich.edu * store into r1 6658007Ssaidi@eecs.umich.edu */ 6668007Ssaidi@eecs.umich.edu br r1,sys_reset 6678007Ssaidi@eecs.umich.edu#else 6688007Ssaidi@eecs.umich.edu /* following is a srcmax change */ 6698007Ssaidi@eecs.umich.edu 6708007Ssaidi@eecs.umich.edu DEBUGSTORE(0x41) 6718007Ssaidi@eecs.umich.edu /* The original code jumped using r1 as a linkage register to pass the base 6728007Ssaidi@eecs.umich.edu of PALcode to the platform specific code. We use r1 to pass a parameter 6738007Ssaidi@eecs.umich.edu from the SROM, so we hardcode the address of Pal_Base in platform.s 6748007Ssaidi@eecs.umich.edu */ 6758007Ssaidi@eecs.umich.edu br r31, sys_reset 6768007Ssaidi@eecs.umich.edu#endif 6778007Ssaidi@eecs.umich.edu 6788007Ssaidi@eecs.umich.edu // Specify PAL version info as a constant 6798007Ssaidi@eecs.umich.edu // at a known location (reset + 8). 6808007Ssaidi@eecs.umich.edu 6818007Ssaidi@eecs.umich.edu .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0> 6828007Ssaidi@eecs.umich.edu .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0> 6838007Ssaidi@eecs.umich.edu .long 0 6848007Ssaidi@eecs.umich.edu .long 0 6858007Ssaidi@eecs.umich.edupal_impure_start: 6868007Ssaidi@eecs.umich.edu .quad 0 6878007Ssaidi@eecs.umich.edupal_debug_ptr: 6888007Ssaidi@eecs.umich.edu .quad 0 // reserved for debug pointer ; 20 6898007Ssaidi@eecs.umich.edu#if beh_model == 0 6908007Ssaidi@eecs.umich.edu 6918007Ssaidi@eecs.umich.edu 6928007Ssaidi@eecs.umich.edu#if enable_p4_fixups != 0 6938007Ssaidi@eecs.umich.edu 6948007Ssaidi@eecs.umich.edu 6958007Ssaidi@eecs.umich.edu .quad 0 6968007Ssaidi@eecs.umich.edu .long p4_fixup_hw_rei_fixup_table 6978007Ssaidi@eecs.umich.edu#endif 6988007Ssaidi@eecs.umich.edu 6998007Ssaidi@eecs.umich.edu#else 7008007Ssaidi@eecs.umich.edu 7018007Ssaidi@eecs.umich.edu .quad 0 // 7028007Ssaidi@eecs.umich.edu .quad 0 //0x0030 7038007Ssaidi@eecs.umich.edu .quad 0 7048007Ssaidi@eecs.umich.edu .quad 0 //0x0040 7058007Ssaidi@eecs.umich.edu .quad 0 7068007Ssaidi@eecs.umich.edu .quad 0 //0x0050 7078007Ssaidi@eecs.umich.edu .quad 0 7088007Ssaidi@eecs.umich.edu .quad 0 //0x0060 7098007Ssaidi@eecs.umich.edu .quad 0 7108007Ssaidi@eecs.umich.edupal_enter_cns_address: 7118007Ssaidi@eecs.umich.edu .quad 0 //0x0070 -- address to jump to from enter_console 7128007Ssaidi@eecs.umich.edu .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit) 7138007Ssaidi@eecs.umich.edu#endif 7148007Ssaidi@eecs.umich.edu 7158007Ssaidi@eecs.umich.edu 7168007Ssaidi@eecs.umich.edu 7178007Ssaidi@eecs.umich.edu 7188007Ssaidi@eecs.umich.edu// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point" 7198007Ssaidi@eecs.umich.edu 7208007Ssaidi@eecs.umich.edu//+ 7218007Ssaidi@eecs.umich.edu// IACCVIO - offset 0080 7228007Ssaidi@eecs.umich.edu// Entry: 7238007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Istream access violation or sign check error on PC. 7248007Ssaidi@eecs.umich.edu// 7258007Ssaidi@eecs.umich.edu// Function: 7268007Ssaidi@eecs.umich.edu// Build stack frame 7278007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 7288007Ssaidi@eecs.umich.edu// a1 <- MMCSR (1 for ACV) 7298007Ssaidi@eecs.umich.edu// a2 <- -1 (for ifetch fault) 7308007Ssaidi@eecs.umich.edu// vector via entMM 7318007Ssaidi@eecs.umich.edu//- 7328007Ssaidi@eecs.umich.edu 7338007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_IACCVIO_ENTRY) 7348007Ssaidi@eecs.umich.eduTrap_Iaccvio: 7358007Ssaidi@eecs.umich.edu DEBUGSTORE(0x42) 7368007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 7378007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 7388007Ssaidi@eecs.umich.edu 7398007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 7408007Ssaidi@eecs.umich.edu bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern 7418007Ssaidi@eecs.umich.edu 7428007Ssaidi@eecs.umich.edu 7438007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 7448007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 7458007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 7468007Ssaidi@eecs.umich.edu 7478007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 7488007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 7498007Ssaidi@eecs.umich.edu 7508007Ssaidi@eecs.umich.eduTRAP_IACCVIO_10_: 7518007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 7528007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 7538007Ssaidi@eecs.umich.edu 7548007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 7558007Ssaidi@eecs.umich.edu bic r14, 3, r16 // pass pc/va as a0 7568007Ssaidi@eecs.umich.edu 7578007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 7588007Ssaidi@eecs.umich.edu or r31, mmcsr_c_acv, r17 // pass mm_csr as a1 7598007Ssaidi@eecs.umich.edu 7608007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 7618007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 7628007Ssaidi@eecs.umich.edu 7638007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 7648007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 7658007Ssaidi@eecs.umich.edu 7668007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 7678007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 7688007Ssaidi@eecs.umich.edu 7698007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entMM 7708007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 7718007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 7728007Ssaidi@eecs.umich.edu 7738007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream, as a2 7748007Ssaidi@eecs.umich.edu hw_rei_spe 7758007Ssaidi@eecs.umich.edu 7768007Ssaidi@eecs.umich.edu 7778007Ssaidi@eecs.umich.edu// .sbttl "INTERRUPT- Interrupt Trap Entry Point" 7788007Ssaidi@eecs.umich.edu 7798007Ssaidi@eecs.umich.edu//+ 7808007Ssaidi@eecs.umich.edu// INTERRUPT - offset 0100 7818007Ssaidi@eecs.umich.edu// Entry: 7828007Ssaidi@eecs.umich.edu// Vectored into via trap on hardware interrupt 7838007Ssaidi@eecs.umich.edu// 7848007Ssaidi@eecs.umich.edu// Function: 7858007Ssaidi@eecs.umich.edu// check for halt interrupt 7868007Ssaidi@eecs.umich.edu// check for passive release (current ipl geq requestor) 7878007Ssaidi@eecs.umich.edu// if necessary, switch to kernel mode 7888007Ssaidi@eecs.umich.edu// push stack frame, update ps (including current mode and ipl copies), sp, and gp 7898007Ssaidi@eecs.umich.edu// pass the interrupt info to the system module 7908007Ssaidi@eecs.umich.edu// 7918007Ssaidi@eecs.umich.edu//- 7928007Ssaidi@eecs.umich.edu 7938007Ssaidi@eecs.umich.edu 7948007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_INTERRUPT_ENTRY) 7958007Ssaidi@eecs.umich.eduTrap_Interrupt: 7968007Ssaidi@eecs.umich.edu mfpr r13, ev5__intid // Fetch level of interruptor 7978007Ssaidi@eecs.umich.edu mfpr r25, ev5__isr // Fetch interrupt summary register 7988007Ssaidi@eecs.umich.edu 7998007Ssaidi@eecs.umich.edu srl r25, isr_v_hlt, r9 // Get HLT bit 8008007Ssaidi@eecs.umich.edu mfpr r14, ev5__ipl 8018007Ssaidi@eecs.umich.edu 8028007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern 8038007Ssaidi@eecs.umich.edu blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set 8048007Ssaidi@eecs.umich.edu 8058007Ssaidi@eecs.umich.edu cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl 8068007Ssaidi@eecs.umich.edu bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl 8078007Ssaidi@eecs.umich.edu 8088007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r10 // get mode bit 8098007Ssaidi@eecs.umich.edu beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel 8108007Ssaidi@eecs.umich.edu 8118007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 8128007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp // get kern stack 8138007Ssaidi@eecs.umich.edu 8148007Ssaidi@eecs.umich.eduTRAP_INTERRUPT_10_: 8158007Ssaidi@eecs.umich.edu lda sp, (0-osfsf_c_size)(sp)// allocate stack space 8168007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 8178007Ssaidi@eecs.umich.edu 8188007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save ps 8198007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 8208007Ssaidi@eecs.umich.edu 8218007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // push gp 8228007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 8238007Ssaidi@eecs.umich.edu 8248007Ssaidi@eecs.umich.edu// pvc_violate 354 // ps is cleared anyway, if store to stack faults. 8258007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 8268007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 8278007Ssaidi@eecs.umich.edu 8288007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 8298007Ssaidi@eecs.umich.edu subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL 8308007Ssaidi@eecs.umich.edu 8318007Ssaidi@eecs.umich.edu srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7. 8328007Ssaidi@eecs.umich.edu subq r13, 0x1d, r9 // Check for 1d, 1e, 1f 8338007Ssaidi@eecs.umich.edu 8348007Ssaidi@eecs.umich.edu cmovge r9, r8, r12 // if .ge. 1d, then take shifted value 8358007Ssaidi@eecs.umich.edu bis r12, r31, r11 // set new ps 8368007Ssaidi@eecs.umich.edu 8378007Ssaidi@eecs.umich.edu mfpr r12, pt_intmask 8388007Ssaidi@eecs.umich.edu and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) 8398007Ssaidi@eecs.umich.edu 8408007Ssaidi@eecs.umich.edu#ifdef SIMOS 8418007Ssaidi@eecs.umich.edu /* 8428007Ssaidi@eecs.umich.edu * Lance had space problems. We don't. 8438007Ssaidi@eecs.umich.edu */ 8448007Ssaidi@eecs.umich.edu extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 8458007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // update gp 8468007Ssaidi@eecs.umich.edu mtpr r14, ev5__ipl // load the new IPL into Ibox 8478007Ssaidi@eecs.umich.edu#else 8488007Ssaidi@eecs.umich.edu// Moved the following three lines to sys_interrupt to make room for debug 8498007Ssaidi@eecs.umich.edu// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 8508007Ssaidi@eecs.umich.edu// mfpr r29, pt_kgp // update gp 8518007Ssaidi@eecs.umich.edu 8528007Ssaidi@eecs.umich.edu// mtpr r14, ev5__ipl // load the new IPL into Ibox 8538007Ssaidi@eecs.umich.edu#endif 8548007Ssaidi@eecs.umich.edu br r31, sys_interrupt // Go handle interrupt 8558007Ssaidi@eecs.umich.edu 8568007Ssaidi@eecs.umich.edu 8578007Ssaidi@eecs.umich.edu 8588007Ssaidi@eecs.umich.edu// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point" 8598007Ssaidi@eecs.umich.edu 8608007Ssaidi@eecs.umich.edu//+ 8618007Ssaidi@eecs.umich.edu// ITBMISS - offset 0180 8628007Ssaidi@eecs.umich.edu// Entry: 8638007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Istream translation buffer miss. 8648007Ssaidi@eecs.umich.edu// 8658007Ssaidi@eecs.umich.edu// Function: 8668007Ssaidi@eecs.umich.edu// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. 8678007Ssaidi@eecs.umich.edu// Can trap into DTBMISS_DOUBLE. 8688007Ssaidi@eecs.umich.edu// This routine can use the PALshadow registers r8, r9, and r10 8698007Ssaidi@eecs.umich.edu// 8708007Ssaidi@eecs.umich.edu//- 8718007Ssaidi@eecs.umich.edu 8728007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_ITB_MISS_ENTRY) 8738007Ssaidi@eecs.umich.eduTrap_Itbmiss: 8748007Ssaidi@eecs.umich.edu#if real_mm == 0 8758007Ssaidi@eecs.umich.edu 8768007Ssaidi@eecs.umich.edu 8778007Ssaidi@eecs.umich.edu // Simple 1-1 va->pa mapping 8788007Ssaidi@eecs.umich.edu 8798007Ssaidi@eecs.umich.edu nop // Pad to align to E1 8808007Ssaidi@eecs.umich.edu mfpr r8, exc_addr 8818007Ssaidi@eecs.umich.edu 8828007Ssaidi@eecs.umich.edu srl r8, page_offset_size_bits, r9 8838007Ssaidi@eecs.umich.edu sll r9, 32, r9 8848007Ssaidi@eecs.umich.edu 8858007Ssaidi@eecs.umich.edu lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE 8868007Ssaidi@eecs.umich.edu mtpr r9, itb_pte // E1 8878007Ssaidi@eecs.umich.edu 8888007Ssaidi@eecs.umich.edu hw_rei_stall // Nital says I don't have to obey shadow wait rule here. 8898007Ssaidi@eecs.umich.edu#else 8908007Ssaidi@eecs.umich.edu 8918007Ssaidi@eecs.umich.edu // Real MM mapping 8928007Ssaidi@eecs.umich.edu nop 8938007Ssaidi@eecs.umich.edu mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. 8948007Ssaidi@eecs.umich.edu 8958007Ssaidi@eecs.umich.edu nop 8968007Ssaidi@eecs.umich.edu mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. 8978007Ssaidi@eecs.umich.edu 8988007Ssaidi@eecs.umich.edupal_itb_ldq: 8998007Ssaidi@eecs.umich.edu ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss 9008007Ssaidi@eecs.umich.edu mtpr r10, exc_addr // Restore exc_address if there was a trap. 9018007Ssaidi@eecs.umich.edu 9028007Ssaidi@eecs.umich.edu mfpr r31, ev5__va // Unlock VA in case there was a double miss 9038007Ssaidi@eecs.umich.edu nop 9048007Ssaidi@eecs.umich.edu 9058007Ssaidi@eecs.umich.edu and r8, osfpte_m_foe, r25 // Look for FOE set. 9068007Ssaidi@eecs.umich.edu blbc r8, invalid_ipte_handler // PTE not valid. 9078007Ssaidi@eecs.umich.edu 9088007Ssaidi@eecs.umich.edu nop 9098007Ssaidi@eecs.umich.edu bne r25, foe_ipte_handler // FOE is set 9108007Ssaidi@eecs.umich.edu 9118007Ssaidi@eecs.umich.edu nop 9128007Ssaidi@eecs.umich.edu mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. 9138007Ssaidi@eecs.umich.edu 9148007Ssaidi@eecs.umich.edu hw_rei_stall // 9158007Ssaidi@eecs.umich.edu 9168007Ssaidi@eecs.umich.edu#endif 9178007Ssaidi@eecs.umich.edu 9188007Ssaidi@eecs.umich.edu 9198007Ssaidi@eecs.umich.edu 9208007Ssaidi@eecs.umich.edu 9218007Ssaidi@eecs.umich.edu// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point" 9228007Ssaidi@eecs.umich.edu 9238007Ssaidi@eecs.umich.edu//+ 9248007Ssaidi@eecs.umich.edu// DTBMISS_SINGLE - offset 0200 9258007Ssaidi@eecs.umich.edu// Entry: 9268007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Dstream single translation buffer miss. 9278007Ssaidi@eecs.umich.edu// 9288007Ssaidi@eecs.umich.edu// Function: 9298007Ssaidi@eecs.umich.edu// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. 9308007Ssaidi@eecs.umich.edu// Can trap into DTBMISS_DOUBLE. 9318007Ssaidi@eecs.umich.edu// This routine can use the PALshadow registers r8, r9, and r10 9328007Ssaidi@eecs.umich.edu//- 9338007Ssaidi@eecs.umich.edu 9348007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_DTB_MISS_ENTRY) 9358007Ssaidi@eecs.umich.eduTrap_Dtbmiss_Single: 9368007Ssaidi@eecs.umich.edu#if real_mm == 0 9378007Ssaidi@eecs.umich.edu // Simple 1-1 va->pa mapping 9388007Ssaidi@eecs.umich.edu mfpr r8, va // E0 9398007Ssaidi@eecs.umich.edu srl r8, page_offset_size_bits, r9 9408007Ssaidi@eecs.umich.edu 9418007Ssaidi@eecs.umich.edu sll r9, 32, r9 9428007Ssaidi@eecs.umich.edu lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE 9438007Ssaidi@eecs.umich.edu 9448007Ssaidi@eecs.umich.edu mtpr r9, dtb_pte // E0 9458007Ssaidi@eecs.umich.edu nop // Pad to align to E0 9468007Ssaidi@eecs.umich.edu 9478007Ssaidi@eecs.umich.edu 9488007Ssaidi@eecs.umich.edu 9498007Ssaidi@eecs.umich.edu mtpr r8, dtb_tag // E0 9508007Ssaidi@eecs.umich.edu nop 9518007Ssaidi@eecs.umich.edu 9528007Ssaidi@eecs.umich.edu nop // Pad tag write 9538007Ssaidi@eecs.umich.edu nop 9548007Ssaidi@eecs.umich.edu 9558007Ssaidi@eecs.umich.edu nop // Pad tag write 9568007Ssaidi@eecs.umich.edu nop 9578007Ssaidi@eecs.umich.edu 9588007Ssaidi@eecs.umich.edu hw_rei 9598007Ssaidi@eecs.umich.edu#else 9608007Ssaidi@eecs.umich.edu mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. 9618007Ssaidi@eecs.umich.edu mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. 9628007Ssaidi@eecs.umich.edu 9638007Ssaidi@eecs.umich.edu// DEBUGSTORE(0x45) 9648007Ssaidi@eecs.umich.edu// DEBUG_EXC_ADDR() 9658007Ssaidi@eecs.umich.edu // Real MM mapping 9668007Ssaidi@eecs.umich.edu mfpr r9, ev5__mm_stat // Get read/write bit. E0. 9678007Ssaidi@eecs.umich.edu mtpr r10, pt6 // Stash exc_addr away 9688007Ssaidi@eecs.umich.edu 9698007Ssaidi@eecs.umich.edupal_dtb_ldq: 9708007Ssaidi@eecs.umich.edu ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss 9718007Ssaidi@eecs.umich.edu nop // Pad MF VA 9728007Ssaidi@eecs.umich.edu 9738007Ssaidi@eecs.umich.edu mfpr r10, ev5__va // Get original faulting VA for TB load. E0. 9748007Ssaidi@eecs.umich.edu nop 9758007Ssaidi@eecs.umich.edu 9768007Ssaidi@eecs.umich.edu mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0. 9778007Ssaidi@eecs.umich.edu blbc r8, invalid_dpte_handler // Handle invalid PTE 9788007Ssaidi@eecs.umich.edu 9798007Ssaidi@eecs.umich.edu mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. 9808007Ssaidi@eecs.umich.edu mfpr r10, pt6 9818007Ssaidi@eecs.umich.edu 9828007Ssaidi@eecs.umich.edu // Following 2 instructions take 2 cycles 9838007Ssaidi@eecs.umich.edu mtpr r10, exc_addr // Return linkage in case we trapped. E1. 9848007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad the write to dtb_tag 9858007Ssaidi@eecs.umich.edu 9868007Ssaidi@eecs.umich.edu hw_rei // Done, return 9878007Ssaidi@eecs.umich.edu#endif 9888007Ssaidi@eecs.umich.edu 9898007Ssaidi@eecs.umich.edu 9908007Ssaidi@eecs.umich.edu 9918007Ssaidi@eecs.umich.edu 9928007Ssaidi@eecs.umich.edu// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point" 9938007Ssaidi@eecs.umich.edu 9948007Ssaidi@eecs.umich.edu//+ 9958007Ssaidi@eecs.umich.edu// DTBMISS_DOUBLE - offset 0280 9968007Ssaidi@eecs.umich.edu// Entry: 9978007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Double TBmiss from single miss flows. 9988007Ssaidi@eecs.umich.edu// 9998007Ssaidi@eecs.umich.edu// r8 - faulting VA 10008007Ssaidi@eecs.umich.edu// r9 - original MMstat 10018007Ssaidi@eecs.umich.edu// r10 - original exc_addr (both itb,dtb miss) 10028007Ssaidi@eecs.umich.edu// pt6 - original exc_addr (dtb miss flow only) 10038007Ssaidi@eecs.umich.edu// VA IPR - locked with original faulting VA 10048007Ssaidi@eecs.umich.edu// 10058007Ssaidi@eecs.umich.edu// Function: 10068007Ssaidi@eecs.umich.edu// Get PTE, if valid load TB and return. 10078007Ssaidi@eecs.umich.edu// If not valid then take TNV/ACV exception. 10088007Ssaidi@eecs.umich.edu// 10098007Ssaidi@eecs.umich.edu// pt4 and pt5 are reserved for this flow. 10108007Ssaidi@eecs.umich.edu// 10118007Ssaidi@eecs.umich.edu// 10128007Ssaidi@eecs.umich.edu//- 10138007Ssaidi@eecs.umich.edu 10148007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) 10158007Ssaidi@eecs.umich.eduTrap_Dtbmiss_double: 10168007Ssaidi@eecs.umich.edu#if ldvpte_bug_fix != 0 10178007Ssaidi@eecs.umich.edu mtpr r8, pt4 // save r8 to do exc_addr check 10188007Ssaidi@eecs.umich.edu mfpr r8, exc_addr 10198007Ssaidi@eecs.umich.edu blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! 10208007Ssaidi@eecs.umich.edu mfpr r8, pt4 // restore r8 10218007Ssaidi@eecs.umich.edu#endif 10228007Ssaidi@eecs.umich.edu nop 10238007Ssaidi@eecs.umich.edu mtpr r22, pt5 // Get some scratch space. E1. 10248007Ssaidi@eecs.umich.edu // Due to virtual scheme, we can skip the first lookup and go 10258007Ssaidi@eecs.umich.edu // right to fetch of level 2 PTE 10268007Ssaidi@eecs.umich.edu sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 10278007Ssaidi@eecs.umich.edu mtpr r21, pt4 // Get some scratch space. E1. 10288007Ssaidi@eecs.umich.edu 10298007Ssaidi@eecs.umich.edu srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 10308007Ssaidi@eecs.umich.edu mfpr r21, pt_ptbr // Get physical address of the page table. 10318007Ssaidi@eecs.umich.edu 10328007Ssaidi@eecs.umich.edu nop 10338007Ssaidi@eecs.umich.edu addq r21, r22, r21 // Index into page table for level 2 PTE. 10348007Ssaidi@eecs.umich.edu 10358007Ssaidi@eecs.umich.edu sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 10368007Ssaidi@eecs.umich.edu ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) 10378007Ssaidi@eecs.umich.edu 10388007Ssaidi@eecs.umich.edu srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 10398007Ssaidi@eecs.umich.edu blbc r21, double_pte_inv // Check for Invalid PTE. 10408007Ssaidi@eecs.umich.edu 10418007Ssaidi@eecs.umich.edu srl r21, 32, r21 // extract PFN from PTE 10428007Ssaidi@eecs.umich.edu sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8 10438007Ssaidi@eecs.umich.edu 10448007Ssaidi@eecs.umich.edu addq r21, r22, r21 // Index into page table for level 3 PTE. 10458007Ssaidi@eecs.umich.edu nop 10468007Ssaidi@eecs.umich.edu 10478007Ssaidi@eecs.umich.edu ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) 10488007Ssaidi@eecs.umich.edu blbc r21, double_pte_inv // Check for invalid PTE. 10498007Ssaidi@eecs.umich.edu 10508007Ssaidi@eecs.umich.edu mtpr r21, ev5__dtb_pte // Write the PTE. E0. 10518007Ssaidi@eecs.umich.edu mfpr r22, pt5 // Restore scratch register 10528007Ssaidi@eecs.umich.edu 10538007Ssaidi@eecs.umich.edu mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. 10548007Ssaidi@eecs.umich.edu mfpr r21, pt4 // Restore scratch register 10558007Ssaidi@eecs.umich.edu 10568007Ssaidi@eecs.umich.edu nop // Pad write to tag. 10578007Ssaidi@eecs.umich.edu nop 10588007Ssaidi@eecs.umich.edu 10598007Ssaidi@eecs.umich.edu nop // Pad write to tag. 10608007Ssaidi@eecs.umich.edu nop 10618007Ssaidi@eecs.umich.edu 10628007Ssaidi@eecs.umich.edu hw_rei 10638007Ssaidi@eecs.umich.edu 10648007Ssaidi@eecs.umich.edu 10658007Ssaidi@eecs.umich.edu 10668007Ssaidi@eecs.umich.edu// .sbttl "UNALIGN -- Dstream unalign trap" 10678007Ssaidi@eecs.umich.edu//+ 10688007Ssaidi@eecs.umich.edu// UNALIGN - offset 0300 10698007Ssaidi@eecs.umich.edu// Entry: 10708007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on unaligned Dstream reference. 10718007Ssaidi@eecs.umich.edu// 10728007Ssaidi@eecs.umich.edu// Function: 10738007Ssaidi@eecs.umich.edu// Build stack frame 10748007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 10758007Ssaidi@eecs.umich.edu// a1 <- Opcode 10768007Ssaidi@eecs.umich.edu// a2 <- src/dst register number 10778007Ssaidi@eecs.umich.edu// vector via entUna 10788007Ssaidi@eecs.umich.edu//- 10798007Ssaidi@eecs.umich.edu 10808007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_UNALIGN_ENTRY) 10818007Ssaidi@eecs.umich.eduTrap_Unalign: 10828007Ssaidi@eecs.umich.edu/* DEBUGSTORE(0x47)*/ 10838007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 10848007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 10858007Ssaidi@eecs.umich.edu 10868007Ssaidi@eecs.umich.edu mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss 10878007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 10888007Ssaidi@eecs.umich.edu 10898007Ssaidi@eecs.umich.edu srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits 10908007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL 10918007Ssaidi@eecs.umich.edu 10928007Ssaidi@eecs.umich.edu blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m 10938007Ssaidi@eecs.umich.edu // not set, must be a load 10948007Ssaidi@eecs.umich.edu and r13, 0x1F, r8 // isolate ra 10958007Ssaidi@eecs.umich.edu 10968007Ssaidi@eecs.umich.edu cmpeq r8, 0x1F, r8 // check for r31/F31 10978007Ssaidi@eecs.umich.edu bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault 10988007Ssaidi@eecs.umich.edu 10998007Ssaidi@eecs.umich.eduUNALIGN_NO_DISMISS: 11008007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 11018007Ssaidi@eecs.umich.edu bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern 11028007Ssaidi@eecs.umich.edu 11038007Ssaidi@eecs.umich.edu 11048007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 11058007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 11068007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 11078007Ssaidi@eecs.umich.edu 11088007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 11098007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 11108007Ssaidi@eecs.umich.edu 11118007Ssaidi@eecs.umich.eduUNALIGN_NO_DISMISS_10_: 11128007Ssaidi@eecs.umich.edu mfpr r25, ev5__va // Unlock VA 11138007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 11148007Ssaidi@eecs.umich.edu 11158007Ssaidi@eecs.umich.edu mtpr r25, pt0 // Stash VA 11168007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 11178007Ssaidi@eecs.umich.edu 11188007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 11198007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode 11208007Ssaidi@eecs.umich.edu 11218007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 11228007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc PC past the ld/st 11238007Ssaidi@eecs.umich.edu 11248007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 11258007Ssaidi@eecs.umich.edu and r25, mm_stat_m_opcode, r17// Clean opocde for a1 11268007Ssaidi@eecs.umich.edu 11278007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 11288007Ssaidi@eecs.umich.edu mfpr r16, pt0 // a0 <- va/unlock 11298007Ssaidi@eecs.umich.edu 11308007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 11318007Ssaidi@eecs.umich.edu mfpr r25, pt_entuna // get entry point 11328007Ssaidi@eecs.umich.edu 11338007Ssaidi@eecs.umich.edu 11348007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 11358007Ssaidi@eecs.umich.edu br r31, unalign_trap_cont 11368007Ssaidi@eecs.umich.edu 11378007Ssaidi@eecs.umich.edu 11388007Ssaidi@eecs.umich.edu 11398007Ssaidi@eecs.umich.edu 11408007Ssaidi@eecs.umich.edu// .sbttl "DFAULT - Dstream Fault Trap Entry Point" 11418007Ssaidi@eecs.umich.edu 11428007Ssaidi@eecs.umich.edu//+ 11438007Ssaidi@eecs.umich.edu// DFAULT - offset 0380 11448007Ssaidi@eecs.umich.edu// Entry: 11458007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on dstream fault or sign check error on DVA. 11468007Ssaidi@eecs.umich.edu// 11478007Ssaidi@eecs.umich.edu// Function: 11488007Ssaidi@eecs.umich.edu// Ignore faults on FETCH/FETCH_M 11498007Ssaidi@eecs.umich.edu// Check for DFAULT in PAL 11508007Ssaidi@eecs.umich.edu// Build stack frame 11518007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 11528007Ssaidi@eecs.umich.edu// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) 11538007Ssaidi@eecs.umich.edu// a2 <- R/W 11548007Ssaidi@eecs.umich.edu// vector via entMM 11558007Ssaidi@eecs.umich.edu// 11568007Ssaidi@eecs.umich.edu//- 11578007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_D_FAULT_ENTRY) 11588007Ssaidi@eecs.umich.eduTrap_Dfault: 11598007Ssaidi@eecs.umich.edu// DEBUGSTORE(0x48) 11608007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 11618007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 11628007Ssaidi@eecs.umich.edu 11638007Ssaidi@eecs.umich.edu mfpr r13, ev5__mm_stat // Get mmstat 11648007Ssaidi@eecs.umich.edu mfpr r8, exc_addr // get pc, preserve r14 11658007Ssaidi@eecs.umich.edu 11668007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits 11678007Ssaidi@eecs.umich.edu blbs r8, dfault_in_pal 11688007Ssaidi@eecs.umich.edu 11698007Ssaidi@eecs.umich.edu bis r8, r31, r14 // move exc_addr to correct place 11708007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 11718007Ssaidi@eecs.umich.edu 11728007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 11738007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 11748007Ssaidi@eecs.umich.edu and r9, mm_stat_m_opcode, r9 // Clean all but opcode 11758007Ssaidi@eecs.umich.edu 11768007Ssaidi@eecs.umich.edu cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm? 11778007Ssaidi@eecs.umich.edu bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault 11788007Ssaidi@eecs.umich.edu 11798007Ssaidi@eecs.umich.edu //dismiss exception if load to r31/f31 11808007Ssaidi@eecs.umich.edu blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm 11818007Ssaidi@eecs.umich.edu 11828007Ssaidi@eecs.umich.edu // not a store or fetch, must be a load 11838007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits 11848007Ssaidi@eecs.umich.edu 11858007Ssaidi@eecs.umich.edu and r9, 0x1F, r9 // isolate rnum 11868007Ssaidi@eecs.umich.edu nop 11878007Ssaidi@eecs.umich.edu 11888007Ssaidi@eecs.umich.edu cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31? 11898007Ssaidi@eecs.umich.edu bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault 11908007Ssaidi@eecs.umich.edu 11918007Ssaidi@eecs.umich.edudfault_no_dismiss: 11928007Ssaidi@eecs.umich.edu and r13, 0xf, r13 // Clean extra bits in mm_stat 11938007Ssaidi@eecs.umich.edu bge r25, dfault_trap_cont // no stack swap needed if cm=kern 11948007Ssaidi@eecs.umich.edu 11958007Ssaidi@eecs.umich.edu 11968007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 11978007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 11988007Ssaidi@eecs.umich.edu 11998007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 12008007Ssaidi@eecs.umich.edu br r31, dfault_trap_cont 12018007Ssaidi@eecs.umich.edu 12028007Ssaidi@eecs.umich.edu 12038007Ssaidi@eecs.umich.edu 12048007Ssaidi@eecs.umich.edu 12058007Ssaidi@eecs.umich.edu 12068007Ssaidi@eecs.umich.edu// .sbttl "MCHK - Machine Check Trap Entry Point" 12078007Ssaidi@eecs.umich.edu 12088007Ssaidi@eecs.umich.edu//+ 12098007Ssaidi@eecs.umich.edu// MCHK - offset 0400 12108007Ssaidi@eecs.umich.edu// Entry: 12118007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on machine check. 12128007Ssaidi@eecs.umich.edu// 12138007Ssaidi@eecs.umich.edu// Function: 12148007Ssaidi@eecs.umich.edu// 12158007Ssaidi@eecs.umich.edu//- 12168007Ssaidi@eecs.umich.edu 12178007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_MCHK_ENTRY) 12188007Ssaidi@eecs.umich.eduTrap_Mchk: 12198007Ssaidi@eecs.umich.edu DEBUGSTORE(0x49) 12208007Ssaidi@eecs.umich.edu mtpr r31, ic_flush_ctl // Flush the Icache 12218007Ssaidi@eecs.umich.edu br r31, sys_machine_check 12228007Ssaidi@eecs.umich.edu 12238007Ssaidi@eecs.umich.edu 12248007Ssaidi@eecs.umich.edu 12258007Ssaidi@eecs.umich.edu 12268007Ssaidi@eecs.umich.edu// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point" 12278007Ssaidi@eecs.umich.edu 12288007Ssaidi@eecs.umich.edu//+ 12298007Ssaidi@eecs.umich.edu// OPCDEC - offset 0480 12308007Ssaidi@eecs.umich.edu// Entry: 12318007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on illegal opcode. 12328007Ssaidi@eecs.umich.edu// 12338007Ssaidi@eecs.umich.edu// Build stack frame 12348007Ssaidi@eecs.umich.edu// a0 <- code 12358007Ssaidi@eecs.umich.edu// a1 <- unpred 12368007Ssaidi@eecs.umich.edu// a2 <- unpred 12378007Ssaidi@eecs.umich.edu// vector via entIF 12388007Ssaidi@eecs.umich.edu// 12398007Ssaidi@eecs.umich.edu//- 12408007Ssaidi@eecs.umich.edu 12418007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_OPCDEC_ENTRY) 12428007Ssaidi@eecs.umich.eduTrap_Opcdec: 12438007Ssaidi@eecs.umich.edu DEBUGSTORE(0x4a) 12448007Ssaidi@eecs.umich.edu//simos DEBUG_EXC_ADDR() 12458007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 12468007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 12478007Ssaidi@eecs.umich.edu 12488007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 12498007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // check opcdec in palmode 12508007Ssaidi@eecs.umich.edu 12518007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 12528007Ssaidi@eecs.umich.edu bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern 12538007Ssaidi@eecs.umich.edu 12548007Ssaidi@eecs.umich.edu 12558007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 12568007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 12578007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 12588007Ssaidi@eecs.umich.edu 12598007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 12608007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 12618007Ssaidi@eecs.umich.edu 12628007Ssaidi@eecs.umich.eduTRAP_OPCDEC_10_: 12638007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 12648007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc pc 12658007Ssaidi@eecs.umich.edu 12668007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 12678007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 12688007Ssaidi@eecs.umich.edu 12698007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 12708007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 12718007Ssaidi@eecs.umich.edu 12728007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 12738007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 12748007Ssaidi@eecs.umich.edu 12758007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 12768007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 12778007Ssaidi@eecs.umich.edu 12788007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 12798007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 12808007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei, E1 12818007Ssaidi@eecs.umich.edu 12828007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp, E1 12838007Ssaidi@eecs.umich.edu 12848007Ssaidi@eecs.umich.edu hw_rei_spe // done, E1 12858007Ssaidi@eecs.umich.edu 12868007Ssaidi@eecs.umich.edu 12878007Ssaidi@eecs.umich.edu 12888007Ssaidi@eecs.umich.edu 12898007Ssaidi@eecs.umich.edu 12908007Ssaidi@eecs.umich.edu 12918007Ssaidi@eecs.umich.edu// .sbttl "ARITH - Arithmetic Exception Trap Entry Point" 12928007Ssaidi@eecs.umich.edu 12938007Ssaidi@eecs.umich.edu//+ 12948007Ssaidi@eecs.umich.edu// ARITH - offset 0500 12958007Ssaidi@eecs.umich.edu// Entry: 12968007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on arithmetic excpetion. 12978007Ssaidi@eecs.umich.edu// 12988007Ssaidi@eecs.umich.edu// Function: 12998007Ssaidi@eecs.umich.edu// Build stack frame 13008007Ssaidi@eecs.umich.edu// a0 <- exc_sum 13018007Ssaidi@eecs.umich.edu// a1 <- exc_mask 13028007Ssaidi@eecs.umich.edu// a2 <- unpred 13038007Ssaidi@eecs.umich.edu// vector via entArith 13048007Ssaidi@eecs.umich.edu// 13058007Ssaidi@eecs.umich.edu//- 13068007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_ARITH_ENTRY) 13078007Ssaidi@eecs.umich.eduTrap_Arith: 13088007Ssaidi@eecs.umich.edu DEBUGSTORE(0x4b) 13098007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r12 // get mode bit 13108007Ssaidi@eecs.umich.edu mfpr r31, ev5__va // unlock mbox 13118007Ssaidi@eecs.umich.edu 13128007Ssaidi@eecs.umich.edu bis r11, r31, r25 // save ps 13138007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 13148007Ssaidi@eecs.umich.edu 13158007Ssaidi@eecs.umich.edu nop 13168007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // arith trap from PAL 13178007Ssaidi@eecs.umich.edu 13188007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 13198007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 13208007Ssaidi@eecs.umich.edu beq r12, TRAP_ARITH_10_ // if zero we are in kern now 13218007Ssaidi@eecs.umich.edu 13228007Ssaidi@eecs.umich.edu bis r31, r31, r25 // set the new ps 13238007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 13248007Ssaidi@eecs.umich.edu 13258007Ssaidi@eecs.umich.edu nop 13268007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp // get kern stack 13278007Ssaidi@eecs.umich.edu 13288007Ssaidi@eecs.umich.eduTRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space 13298007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 13308007Ssaidi@eecs.umich.edu 13318007Ssaidi@eecs.umich.edu nop // Pad current mode write and stq 13328007Ssaidi@eecs.umich.edu mfpr r13, ev5__exc_sum // get the exc_sum 13338007Ssaidi@eecs.umich.edu 13348007Ssaidi@eecs.umich.edu mfpr r12, pt_entarith 13358007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 13368007Ssaidi@eecs.umich.edu 13378007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) 13388007Ssaidi@eecs.umich.edu mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 13398007Ssaidi@eecs.umich.edu 13408007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save ps 13418007Ssaidi@eecs.umich.edu bis r25, r31, r11 // set new ps 13428007Ssaidi@eecs.umich.edu 13438007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 13448007Ssaidi@eecs.umich.edu srl r13, exc_sum_v_swc, r16// shift data to correct position 13458007Ssaidi@eecs.umich.edu 13468007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) 13478007Ssaidi@eecs.umich.edu// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow 13488007Ssaidi@eecs.umich.edu mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask 13498007Ssaidi@eecs.umich.edu 13508007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 13518007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 13528007Ssaidi@eecs.umich.edu 13538007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kern gp - E1 13548007Ssaidi@eecs.umich.edu hw_rei_spe // done - E1 13558007Ssaidi@eecs.umich.edu 13568007Ssaidi@eecs.umich.edu 13578007Ssaidi@eecs.umich.edu 13588007Ssaidi@eecs.umich.edu 13598007Ssaidi@eecs.umich.edu 13608007Ssaidi@eecs.umich.edu 13618007Ssaidi@eecs.umich.edu// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point" 13628007Ssaidi@eecs.umich.edu 13638007Ssaidi@eecs.umich.edu//+ 13648007Ssaidi@eecs.umich.edu// FEN - offset 0580 13658007Ssaidi@eecs.umich.edu// Entry: 13668007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on illegal FP op. 13678007Ssaidi@eecs.umich.edu// 13688007Ssaidi@eecs.umich.edu// Function: 13698007Ssaidi@eecs.umich.edu// Build stack frame 13708007Ssaidi@eecs.umich.edu// a0 <- code 13718007Ssaidi@eecs.umich.edu// a1 <- unpred 13728007Ssaidi@eecs.umich.edu// a2 <- unpred 13738007Ssaidi@eecs.umich.edu// vector via entIF 13748007Ssaidi@eecs.umich.edu// 13758007Ssaidi@eecs.umich.edu//- 13768007Ssaidi@eecs.umich.edu 13778007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_FEN_ENTRY) 13788007Ssaidi@eecs.umich.eduTrap_Fen: 13798007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 13808007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 13818007Ssaidi@eecs.umich.edu 13828007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 13838007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // check opcdec in palmode 13848007Ssaidi@eecs.umich.edu 13858007Ssaidi@eecs.umich.edu mfpr r13, ev5__icsr 13868007Ssaidi@eecs.umich.edu nop 13878007Ssaidi@eecs.umich.edu 13888007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 13898007Ssaidi@eecs.umich.edu bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern 13908007Ssaidi@eecs.umich.edu 13918007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 13928007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 13938007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 13948007Ssaidi@eecs.umich.edu 13958007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 13968007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 13978007Ssaidi@eecs.umich.edu 13988007Ssaidi@eecs.umich.eduTRAP_FEN_10_: 13998007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 14008007Ssaidi@eecs.umich.edu srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0 14018007Ssaidi@eecs.umich.edu 14028007Ssaidi@eecs.umich.edu 14038007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 14048007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 14058007Ssaidi@eecs.umich.edu 14068007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 14078007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 14088007Ssaidi@eecs.umich.edu 14098007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 14108007Ssaidi@eecs.umich.edu bis r12, r31, r11 // set new ps 14118007Ssaidi@eecs.umich.edu 14128007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 14138007Ssaidi@eecs.umich.edu blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC. 14148007Ssaidi@eecs.umich.edu 14158007Ssaidi@eecs.umich.edu bis r31, osf_a0_fen, r16 // set a0 14168007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 14178007Ssaidi@eecs.umich.edu 14188007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 14198007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei -E1 14208007Ssaidi@eecs.umich.edu 14218007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp -E1 14228007Ssaidi@eecs.umich.edu 14238007Ssaidi@eecs.umich.edu hw_rei_spe // done -E1 14248007Ssaidi@eecs.umich.edu 14258007Ssaidi@eecs.umich.edu// FEN trap was taken, but the fault is really opcdec. 14268007Ssaidi@eecs.umich.edu ALIGN_BRANCH 14278007Ssaidi@eecs.umich.edufen_to_opcdec: 14288007Ssaidi@eecs.umich.edu addq r14, 4, r14 // save PC+4 14298007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 14308007Ssaidi@eecs.umich.edu 14318007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 14328007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 14338007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 14348007Ssaidi@eecs.umich.edu 14358007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 14368007Ssaidi@eecs.umich.edu hw_rei_spe // done 14378007Ssaidi@eecs.umich.edu 14388007Ssaidi@eecs.umich.edu 14398007Ssaidi@eecs.umich.edu 14408007Ssaidi@eecs.umich.edu// .sbttl "Misc handlers" 14418007Ssaidi@eecs.umich.edu // Start area for misc code. 14428007Ssaidi@eecs.umich.edu//+ 14438007Ssaidi@eecs.umich.edu//dfault_trap_cont 14448007Ssaidi@eecs.umich.edu// A dfault trap has been taken. The sp has been updated if necessary. 14458007Ssaidi@eecs.umich.edu// Push a stack frame a vector via entMM. 14468007Ssaidi@eecs.umich.edu// 14478007Ssaidi@eecs.umich.edu// Current state: 14488007Ssaidi@eecs.umich.edu// r12 - new PS 14498007Ssaidi@eecs.umich.edu// r13 - MMstat 14508007Ssaidi@eecs.umich.edu// VA - locked 14518007Ssaidi@eecs.umich.edu// 14528007Ssaidi@eecs.umich.edu//- 14538007Ssaidi@eecs.umich.edu ALIGN_BLOCK 14548007Ssaidi@eecs.umich.edudfault_trap_cont: 14558007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 14568007Ssaidi@eecs.umich.edu mfpr r25, ev5__va // Fetch VA/unlock 14578007Ssaidi@eecs.umich.edu 14588007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 14598007Ssaidi@eecs.umich.edu and r13, 1, r18 // Clean r/w bit for a2 14608007Ssaidi@eecs.umich.edu 14618007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 14628007Ssaidi@eecs.umich.edu bis r25, r31, r16 // a0 <- va 14638007Ssaidi@eecs.umich.edu 14648007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 14658007Ssaidi@eecs.umich.edu srl r13, 1, r17 // shift fault bits to right position 14668007Ssaidi@eecs.umich.edu 14678007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 14688007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 14698007Ssaidi@eecs.umich.edu 14708007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 14718007Ssaidi@eecs.umich.edu mfpr r25, pt_entmm // get entry point 14728007Ssaidi@eecs.umich.edu 14738007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 14748007Ssaidi@eecs.umich.edu cmovlbs r17, 1, r17 // a2. acv overrides fox. 14758007Ssaidi@eecs.umich.edu 14768007Ssaidi@eecs.umich.edu mtpr r25, exc_addr // load exc_addr with entMM 14778007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 14788007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 14798007Ssaidi@eecs.umich.edu 14808007Ssaidi@eecs.umich.edu hw_rei_spe // done 14818007Ssaidi@eecs.umich.edu 14828007Ssaidi@eecs.umich.edu//+ 14838007Ssaidi@eecs.umich.edu//unalign_trap_cont 14848007Ssaidi@eecs.umich.edu// An unalign trap has been taken. Just need to finish up a few things. 14858007Ssaidi@eecs.umich.edu// 14868007Ssaidi@eecs.umich.edu// Current state: 14878007Ssaidi@eecs.umich.edu// r25 - entUna 14888007Ssaidi@eecs.umich.edu// r13 - shifted MMstat 14898007Ssaidi@eecs.umich.edu// 14908007Ssaidi@eecs.umich.edu//- 14918007Ssaidi@eecs.umich.edu ALIGN_BLOCK 14928007Ssaidi@eecs.umich.eduunalign_trap_cont: 14938007Ssaidi@eecs.umich.edu mtpr r25, exc_addr // load exc_addr with entUna 14948007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 14958007Ssaidi@eecs.umich.edu 14968007Ssaidi@eecs.umich.edu 14978007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 14988007Ssaidi@eecs.umich.edu and r13, mm_stat_m_ra, r18 // Clean Ra for a2 14998007Ssaidi@eecs.umich.edu 15008007Ssaidi@eecs.umich.edu hw_rei_spe // done 15018007Ssaidi@eecs.umich.edu 15028007Ssaidi@eecs.umich.edu 15038007Ssaidi@eecs.umich.edu 15048007Ssaidi@eecs.umich.edu//+ 15058007Ssaidi@eecs.umich.edu// dfault_in_pal 15068007Ssaidi@eecs.umich.edu// Dfault trap was taken, exc_addr points to a PAL PC. 15078007Ssaidi@eecs.umich.edu// r9 - mmstat<opcode> right justified 15088007Ssaidi@eecs.umich.edu// r8 - exception address 15098007Ssaidi@eecs.umich.edu// 15108007Ssaidi@eecs.umich.edu// These are the cases: 15118007Ssaidi@eecs.umich.edu// opcode was STQ -- from a stack builder, KSP not valid halt 15128007Ssaidi@eecs.umich.edu// r14 - original exc_addr 15138007Ssaidi@eecs.umich.edu// r11 - original PS 15148007Ssaidi@eecs.umich.edu// opcode was STL_C -- rti or retsys clear lock_flag by stack write, 15158007Ssaidi@eecs.umich.edu// KSP not valid halt 15168007Ssaidi@eecs.umich.edu// r11 - original PS 15178007Ssaidi@eecs.umich.edu// r14 - original exc_addr 15188007Ssaidi@eecs.umich.edu// opcode was LDQ -- retsys or rti stack read, KSP not valid halt 15198007Ssaidi@eecs.umich.edu// r11 - original PS 15208007Ssaidi@eecs.umich.edu// r14 - original exc_addr 15218007Ssaidi@eecs.umich.edu// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables 15228007Ssaidi@eecs.umich.edu// r10 - original exc_addr 15238007Ssaidi@eecs.umich.edu// r11 - original PS 15248007Ssaidi@eecs.umich.edu// 15258007Ssaidi@eecs.umich.edu// 15268007Ssaidi@eecs.umich.edu//- 15278007Ssaidi@eecs.umich.edu ALIGN_BLOCK 15288007Ssaidi@eecs.umich.edudfault_in_pal: 15298007Ssaidi@eecs.umich.edu DEBUGSTORE(0x50) 15308007Ssaidi@eecs.umich.edu bic r8, 3, r8 // Clean PC 15318007Ssaidi@eecs.umich.edu mfpr r9, pal_base 15328007Ssaidi@eecs.umich.edu 15338007Ssaidi@eecs.umich.edu mfpr r31, va // unlock VA 15348007Ssaidi@eecs.umich.edu#if real_mm != 0 15358007Ssaidi@eecs.umich.edu // if not real_mm, should never get here from miss flows 15368007Ssaidi@eecs.umich.edu 15378007Ssaidi@eecs.umich.edu subq r9, r8, r8 // pal_base - offset 15388007Ssaidi@eecs.umich.edu 15398007Ssaidi@eecs.umich.edu lda r9, pal_itb_ldq-pal_base(r8) 15408007Ssaidi@eecs.umich.edu nop 15418007Ssaidi@eecs.umich.edu 15428007Ssaidi@eecs.umich.edu beq r9, dfault_do_bugcheck 15438007Ssaidi@eecs.umich.edu lda r9, pal_dtb_ldq-pal_base(r8) 15448007Ssaidi@eecs.umich.edu 15458007Ssaidi@eecs.umich.edu beq r9, dfault_do_bugcheck 15468007Ssaidi@eecs.umich.edu#endif 15478007Ssaidi@eecs.umich.edu 15488007Ssaidi@eecs.umich.edu// 15498007Ssaidi@eecs.umich.edu// KSP invalid halt case -- 15508007Ssaidi@eecs.umich.eduksp_inval_halt: 15518007Ssaidi@eecs.umich.edu DEBUGSTORE(76) 15528007Ssaidi@eecs.umich.edu bic r11, osfps_m_mode, r11 // set ps to kernel mode 15538007Ssaidi@eecs.umich.edu mtpr r0, pt0 15548007Ssaidi@eecs.umich.edu 15558007Ssaidi@eecs.umich.edu mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode 15568007Ssaidi@eecs.umich.edu mtpr r31, ips 15578007Ssaidi@eecs.umich.edu 15588007Ssaidi@eecs.umich.edu mtpr r14, exc_addr // Set PC to instruction that caused trouble 15598007Ssaidi@eecs.umich.edu//orig pvc_jsr updpcb, bsr=1 15608007Ssaidi@eecs.umich.edu bsr r0, pal_update_pcb // update the pcb 15618007Ssaidi@eecs.umich.edu 15628007Ssaidi@eecs.umich.edu lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt 15638007Ssaidi@eecs.umich.edu br r31, sys_enter_console // enter the console 15648007Ssaidi@eecs.umich.edu 15658007Ssaidi@eecs.umich.edu ALIGN_BRANCH 15668007Ssaidi@eecs.umich.edudfault_do_bugcheck: 15678007Ssaidi@eecs.umich.edu bis r10, r31, r14 // bugcheck expects exc_addr in r14 15688007Ssaidi@eecs.umich.edu br r31, pal_pal_bug_check 15698007Ssaidi@eecs.umich.edu 15708007Ssaidi@eecs.umich.edu 15718007Ssaidi@eecs.umich.edu ALIGN_BLOCK 15728007Ssaidi@eecs.umich.edu//+ 15738007Ssaidi@eecs.umich.edu// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 15748007Ssaidi@eecs.umich.edu// On entry - 15758007Ssaidi@eecs.umich.edu// r14 - exc_addr 15768007Ssaidi@eecs.umich.edu// VA is locked 15778007Ssaidi@eecs.umich.edu// 15788007Ssaidi@eecs.umich.edu//- 15798007Ssaidi@eecs.umich.edudfault_fetch_ldr31_err: 15808007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm 15818007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // Make sure ps hasn't changed 15828007Ssaidi@eecs.umich.edu 15838007Ssaidi@eecs.umich.edu mfpr r31, va // unlock the mbox 15848007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc the pc to skip the fetch 15858007Ssaidi@eecs.umich.edu 15868007Ssaidi@eecs.umich.edu mtpr r14, exc_addr // give ibox new PC 15878007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad exc_addr write 15888007Ssaidi@eecs.umich.edu 15898007Ssaidi@eecs.umich.edu hw_rei 15908007Ssaidi@eecs.umich.edu 15918007Ssaidi@eecs.umich.edu 15928007Ssaidi@eecs.umich.edu 15938007Ssaidi@eecs.umich.edu ALIGN_BLOCK 15948007Ssaidi@eecs.umich.edu//+ 15958007Ssaidi@eecs.umich.edu// sys_from_kern 15968007Ssaidi@eecs.umich.edu// callsys from kernel mode - OS bugcheck machine check 15978007Ssaidi@eecs.umich.edu// 15988007Ssaidi@eecs.umich.edu//- 15998007Ssaidi@eecs.umich.edusys_from_kern: 16008007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // PC points to call_pal 16018007Ssaidi@eecs.umich.edu subq r14, 4, r14 16028007Ssaidi@eecs.umich.edu 16038007Ssaidi@eecs.umich.edu lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code 16048007Ssaidi@eecs.umich.edu br r31, pal_pal_mchk 16058007Ssaidi@eecs.umich.edu 16068007Ssaidi@eecs.umich.edu 16078007Ssaidi@eecs.umich.edu// .sbttl "Continuation of long call_pal flows" 16088007Ssaidi@eecs.umich.edu ALIGN_BLOCK 16098007Ssaidi@eecs.umich.edu//+ 16108007Ssaidi@eecs.umich.edu// wrent_tbl 16118007Ssaidi@eecs.umich.edu// Table to write *int in paltemps. 16128007Ssaidi@eecs.umich.edu// 4 instructions/entry 16138007Ssaidi@eecs.umich.edu// r16 has new value 16148007Ssaidi@eecs.umich.edu// 16158007Ssaidi@eecs.umich.edu//- 16168007Ssaidi@eecs.umich.eduwrent_tbl: 16178007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16188007Ssaidi@eecs.umich.edu nop 16198007Ssaidi@eecs.umich.edu mtpr r16, pt_entint 16208007Ssaidi@eecs.umich.edu 16218007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16228007Ssaidi@eecs.umich.edu hw_rei 16238007Ssaidi@eecs.umich.edu 16248007Ssaidi@eecs.umich.edu 16258007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16268007Ssaidi@eecs.umich.edu nop 16278007Ssaidi@eecs.umich.edu mtpr r16, pt_entarith 16288007Ssaidi@eecs.umich.edu 16298007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16308007Ssaidi@eecs.umich.edu hw_rei 16318007Ssaidi@eecs.umich.edu 16328007Ssaidi@eecs.umich.edu 16338007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16348007Ssaidi@eecs.umich.edu nop 16358007Ssaidi@eecs.umich.edu mtpr r16, pt_entmm 16368007Ssaidi@eecs.umich.edu 16378007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16388007Ssaidi@eecs.umich.edu hw_rei 16398007Ssaidi@eecs.umich.edu 16408007Ssaidi@eecs.umich.edu 16418007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16428007Ssaidi@eecs.umich.edu nop 16438007Ssaidi@eecs.umich.edu mtpr r16, pt_entif 16448007Ssaidi@eecs.umich.edu 16458007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16468007Ssaidi@eecs.umich.edu hw_rei 16478007Ssaidi@eecs.umich.edu 16488007Ssaidi@eecs.umich.edu 16498007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16508007Ssaidi@eecs.umich.edu nop 16518007Ssaidi@eecs.umich.edu mtpr r16, pt_entuna 16528007Ssaidi@eecs.umich.edu 16538007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16548007Ssaidi@eecs.umich.edu hw_rei 16558007Ssaidi@eecs.umich.edu 16568007Ssaidi@eecs.umich.edu 16578007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 16588007Ssaidi@eecs.umich.edu nop 16598007Ssaidi@eecs.umich.edu mtpr r16, pt_entsys 16608007Ssaidi@eecs.umich.edu 16618007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 16628007Ssaidi@eecs.umich.edu hw_rei 16638007Ssaidi@eecs.umich.edu 16648007Ssaidi@eecs.umich.edu ALIGN_BLOCK 16658007Ssaidi@eecs.umich.edu//+ 16668007Ssaidi@eecs.umich.edu// tbi_tbl 16678007Ssaidi@eecs.umich.edu// Table to do tbi instructions 16688007Ssaidi@eecs.umich.edu// 4 instructions per entry 16698007Ssaidi@eecs.umich.edu//- 16708007Ssaidi@eecs.umich.edutbi_tbl: 16718007Ssaidi@eecs.umich.edu // -2 tbia 16728007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 16738007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_ia // Flush DTB 16748007Ssaidi@eecs.umich.edu mtpr r31, ev5__itb_ia // Flush ITB 16758007Ssaidi@eecs.umich.edu 16768007Ssaidi@eecs.umich.edu#if icflush_on_tbix != 0 16778007Ssaidi@eecs.umich.edu 16788007Ssaidi@eecs.umich.edu 16798007Ssaidi@eecs.umich.edu br r31, pal_ic_flush // Flush Icache 16808007Ssaidi@eecs.umich.edu#else 16818007Ssaidi@eecs.umich.edu 16828007Ssaidi@eecs.umich.edu hw_rei_stall 16838007Ssaidi@eecs.umich.edu#endif 16848007Ssaidi@eecs.umich.edu 16858007Ssaidi@eecs.umich.edu nop // Pad table 16868007Ssaidi@eecs.umich.edu 16878007Ssaidi@eecs.umich.edu // -1 tbiap 16888007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 16898007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_iap // Flush DTB 16908007Ssaidi@eecs.umich.edu mtpr r31, ev5__itb_iap // Flush ITB 16918007Ssaidi@eecs.umich.edu 16928007Ssaidi@eecs.umich.edu#if icflush_on_tbix != 0 16938007Ssaidi@eecs.umich.edu 16948007Ssaidi@eecs.umich.edu 16958007Ssaidi@eecs.umich.edu br r31, pal_ic_flush // Flush Icache 16968007Ssaidi@eecs.umich.edu#else 16978007Ssaidi@eecs.umich.edu 16988007Ssaidi@eecs.umich.edu hw_rei_stall 16998007Ssaidi@eecs.umich.edu#endif 17008007Ssaidi@eecs.umich.edu 17018007Ssaidi@eecs.umich.edu nop // Pad table 17028007Ssaidi@eecs.umich.edu 17038007Ssaidi@eecs.umich.edu 17048007Ssaidi@eecs.umich.edu // 0 unused 17058007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 17068007Ssaidi@eecs.umich.edu hw_rei // Pad table 17078007Ssaidi@eecs.umich.edu nop 17088007Ssaidi@eecs.umich.edu nop 17098007Ssaidi@eecs.umich.edu nop 17108007Ssaidi@eecs.umich.edu 17118007Ssaidi@eecs.umich.edu 17128007Ssaidi@eecs.umich.edu // 1 tbisi 17138007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 17148007Ssaidi@eecs.umich.edu#if icflush_on_tbix != 0 17158007Ssaidi@eecs.umich.edu 17168007Ssaidi@eecs.umich.edu 17178007Ssaidi@eecs.umich.edu 17188007Ssaidi@eecs.umich.edu nop 17198007Ssaidi@eecs.umich.edu br r31, pal_ic_flush_and_tbisi // Flush Icache 17208007Ssaidi@eecs.umich.edu nop 17218007Ssaidi@eecs.umich.edu nop // Pad table 17228007Ssaidi@eecs.umich.edu#else 17238007Ssaidi@eecs.umich.edu 17248007Ssaidi@eecs.umich.edu nop 17258007Ssaidi@eecs.umich.edu nop 17268007Ssaidi@eecs.umich.edu mtpr r17, ev5__itb_is // Flush ITB 17278007Ssaidi@eecs.umich.edu hw_rei_stall 17288007Ssaidi@eecs.umich.edu#endif 17298007Ssaidi@eecs.umich.edu 17308007Ssaidi@eecs.umich.edu 17318007Ssaidi@eecs.umich.edu 17328007Ssaidi@eecs.umich.edu // 2 tbisd 17338007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 17348007Ssaidi@eecs.umich.edu mtpr r17, ev5__dtb_is // Flush DTB. 17358007Ssaidi@eecs.umich.edu nop 17368007Ssaidi@eecs.umich.edu 17378007Ssaidi@eecs.umich.edu nop 17388007Ssaidi@eecs.umich.edu hw_rei_stall 17398007Ssaidi@eecs.umich.edu 17408007Ssaidi@eecs.umich.edu 17418007Ssaidi@eecs.umich.edu // 3 tbis 17428007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 17438007Ssaidi@eecs.umich.edu mtpr r17, ev5__dtb_is // Flush DTB 17448007Ssaidi@eecs.umich.edu#if icflush_on_tbix != 0 17458007Ssaidi@eecs.umich.edu 17468007Ssaidi@eecs.umich.edu 17478007Ssaidi@eecs.umich.edu br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB 17488007Ssaidi@eecs.umich.edu#else 17498007Ssaidi@eecs.umich.edu br r31, tbi_finish 17508007Ssaidi@eecs.umich.edu ALIGN_BRANCH 17518007Ssaidi@eecs.umich.edutbi_finish: 17528007Ssaidi@eecs.umich.edu mtpr r17, ev5__itb_is // Flush ITB 17538007Ssaidi@eecs.umich.edu hw_rei_stall 17548007Ssaidi@eecs.umich.edu#endif 17558007Ssaidi@eecs.umich.edu 17568007Ssaidi@eecs.umich.edu 17578007Ssaidi@eecs.umich.edu 17588007Ssaidi@eecs.umich.edu ALIGN_BLOCK 17598007Ssaidi@eecs.umich.edu//+ 17608007Ssaidi@eecs.umich.edu// bpt_bchk_common: 17618007Ssaidi@eecs.umich.edu// Finish up the bpt/bchk instructions 17628007Ssaidi@eecs.umich.edu//- 17638007Ssaidi@eecs.umich.edubpt_bchk_common: 17648007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 17658007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 17668007Ssaidi@eecs.umich.edu 17678007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save old ps 17688007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 17698007Ssaidi@eecs.umich.edu 17708007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 17718007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 17728007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 17738007Ssaidi@eecs.umich.edu 17748007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 17758007Ssaidi@eecs.umich.edu 17768007Ssaidi@eecs.umich.edu 17778007Ssaidi@eecs.umich.edu hw_rei_spe // done 17788007Ssaidi@eecs.umich.edu 17798007Ssaidi@eecs.umich.edu 17808007Ssaidi@eecs.umich.edu ALIGN_BLOCK 17818007Ssaidi@eecs.umich.edu//+ 17828007Ssaidi@eecs.umich.edu// rti_to_user 17838007Ssaidi@eecs.umich.edu// Finish up the rti instruction 17848007Ssaidi@eecs.umich.edu//- 17858007Ssaidi@eecs.umich.edurti_to_user: 17868007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 17878007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 17888007Ssaidi@eecs.umich.edu 17898007Ssaidi@eecs.umich.edu mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles 17908007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save off incase RTI to user 17918007Ssaidi@eecs.umich.edu 17928007Ssaidi@eecs.umich.edu mfpr r30, pt_usp 17938007Ssaidi@eecs.umich.edu hw_rei_spe // and back 17948007Ssaidi@eecs.umich.edu 17958007Ssaidi@eecs.umich.edu 17968007Ssaidi@eecs.umich.edu ALIGN_BLOCK 17978007Ssaidi@eecs.umich.edu//+ 17988007Ssaidi@eecs.umich.edu// rti_to_kern 17998007Ssaidi@eecs.umich.edu// Finish up the rti instruction 18008007Ssaidi@eecs.umich.edu//- 18018007Ssaidi@eecs.umich.edurti_to_kern: 18028007Ssaidi@eecs.umich.edu and r12, osfps_m_ipl, r11 // clean ps 18038007Ssaidi@eecs.umich.edu mfpr r12, pt_intmask // get int mask 18048007Ssaidi@eecs.umich.edu 18058007Ssaidi@eecs.umich.edu extbl r12, r11, r12 // get mask for this ipl 18068007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save off incase RTI to user 18078007Ssaidi@eecs.umich.edu 18088007Ssaidi@eecs.umich.edu mtpr r12, ev5__ipl // set the new ipl. 18098007Ssaidi@eecs.umich.edu or r25, r31, sp // sp 18108007Ssaidi@eecs.umich.edu 18118007Ssaidi@eecs.umich.edu// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals 18128007Ssaidi@eecs.umich.edu hw_rei 18138007Ssaidi@eecs.umich.edu 18148007Ssaidi@eecs.umich.edu ALIGN_BLOCK 18158007Ssaidi@eecs.umich.edu//+ 18168007Ssaidi@eecs.umich.edu// swpctx_cont 18178007Ssaidi@eecs.umich.edu// Finish up the swpctx instruction 18188007Ssaidi@eecs.umich.edu//- 18198007Ssaidi@eecs.umich.edu 18208007Ssaidi@eecs.umich.eduswpctx_cont: 18218007Ssaidi@eecs.umich.edu#if ev5_p1 != 0 18228007Ssaidi@eecs.umich.edu 18238007Ssaidi@eecs.umich.edu 18248007Ssaidi@eecs.umich.edu bic r25, r24, r25 // clean icsr<FPE> 18258007Ssaidi@eecs.umich.edu get_impure r8 // get impure pointer 18268007Ssaidi@eecs.umich.edu 18278007Ssaidi@eecs.umich.edu sll r12, icsr_v_fpe, r12 // shift new fen to pos 18288007Ssaidi@eecs.umich.edu fix_impure_ipr r8 // adjust impure pointer 18298007Ssaidi@eecs.umich.edu 18308007Ssaidi@eecs.umich.edu restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits 18318007Ssaidi@eecs.umich.edu srl r23, 32, r24 // move asn to low asn pos 18328007Ssaidi@eecs.umich.edu 18338007Ssaidi@eecs.umich.edu ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr 18348007Ssaidi@eecs.umich.edu srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 18358007Ssaidi@eecs.umich.edu 18368007Ssaidi@eecs.umich.edu or r25, r12, r25 // icsr with new fen 18378007Ssaidi@eecs.umich.edu sll r24, itb_asn_v_asn, r12 18388007Ssaidi@eecs.umich.edu 18398007Ssaidi@eecs.umich.edu#else 18408007Ssaidi@eecs.umich.edu 18418007Ssaidi@eecs.umich.edu bic r25, r24, r25 // clean icsr<FPE,PMP> 18428007Ssaidi@eecs.umich.edu sll r12, icsr_v_fpe, r12 // shift new fen to pos 18438007Ssaidi@eecs.umich.edu 18448007Ssaidi@eecs.umich.edu ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr 18458007Ssaidi@eecs.umich.edu srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 18468007Ssaidi@eecs.umich.edu 18478007Ssaidi@eecs.umich.edu or r25, r12, r25 // icsr with new fen 18488007Ssaidi@eecs.umich.edu srl r23, 32, r24 // move asn to low asn pos 18498007Ssaidi@eecs.umich.edu 18508007Ssaidi@eecs.umich.edu and r22, 1, r22 18518007Ssaidi@eecs.umich.edu sll r24, itb_asn_v_asn, r12 18528007Ssaidi@eecs.umich.edu 18538007Ssaidi@eecs.umich.edu sll r22, icsr_v_pmp, r22 18548007Ssaidi@eecs.umich.edu nop 18558007Ssaidi@eecs.umich.edu 18568007Ssaidi@eecs.umich.edu or r25, r22, r25 // icsr with new pme 18578007Ssaidi@eecs.umich.edu#endif 18588007Ssaidi@eecs.umich.edu 18598007Ssaidi@eecs.umich.edu sll r24, dtb_asn_v_asn, r24 18608007Ssaidi@eecs.umich.edu 18618007Ssaidi@eecs.umich.edu subl r23, r13, r13 // gen new cc offset 18628007Ssaidi@eecs.umich.edu mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 18638007Ssaidi@eecs.umich.edu 18648007Ssaidi@eecs.umich.edu mtpr r24, dtb_asn // Load up new ASN 18658007Ssaidi@eecs.umich.edu mtpr r25, icsr // write the icsr 18668007Ssaidi@eecs.umich.edu 18678007Ssaidi@eecs.umich.edu sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. 18688007Ssaidi@eecs.umich.edu ldqp r25, osfpcb_q_usp(r16) // get new usp 18698007Ssaidi@eecs.umich.edu 18708007Ssaidi@eecs.umich.edu insll r13, 4, r13 // >> 32 18718007Ssaidi@eecs.umich.edu// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow 18728007Ssaidi@eecs.umich.edu mtpr r14, pt_ptbr // load the new ptbr 18738007Ssaidi@eecs.umich.edu 18748007Ssaidi@eecs.umich.edu mtpr r13, cc // set new offset 18758007Ssaidi@eecs.umich.edu ldqp r30, osfpcb_q_ksp(r16) // get new ksp 18768007Ssaidi@eecs.umich.edu 18778007Ssaidi@eecs.umich.edu// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow 18788007Ssaidi@eecs.umich.edu mtpr r25, pt_usp // save usp 18798007Ssaidi@eecs.umich.edu 18808007Ssaidi@eecs.umich.edu#if ev5_p1 != 0 18818007Ssaidi@eecs.umich.edu 18828007Ssaidi@eecs.umich.edu 18838007Ssaidi@eecs.umich.edu blbc r8, no_pm_change // if monitoring all processes -- no need to change pm 18848007Ssaidi@eecs.umich.edu 18858007Ssaidi@eecs.umich.edu // otherwise, monitoring select processes - update pm 18868007Ssaidi@eecs.umich.edu lda r25, 0x3F(r31) 18878007Ssaidi@eecs.umich.edu cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings 18888007Ssaidi@eecs.umich.edu 18898007Ssaidi@eecs.umich.edu sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask 18908007Ssaidi@eecs.umich.edu mfpr r22, ev5__pmctr 18918007Ssaidi@eecs.umich.edu 18928007Ssaidi@eecs.umich.edu and r8, r25, r8 // mask new ctl value 18938007Ssaidi@eecs.umich.edu bic r22, r25, r22 // clear ctl field in pmctr 18948007Ssaidi@eecs.umich.edu 18958007Ssaidi@eecs.umich.edu or r8, r22, r8 18968007Ssaidi@eecs.umich.edu mtpr r8, ev5__pmctr 18978007Ssaidi@eecs.umich.edu 18988007Ssaidi@eecs.umich.eduno_pm_change: 18998007Ssaidi@eecs.umich.edu#endif 19008007Ssaidi@eecs.umich.edu 19018007Ssaidi@eecs.umich.edu 19028007Ssaidi@eecs.umich.edu#if osf_chm_fix != 0 19038007Ssaidi@eecs.umich.edu 19048007Ssaidi@eecs.umich.edu 19058007Ssaidi@eecs.umich.edu p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here 19068007Ssaidi@eecs.umich.edu 19078007Ssaidi@eecs.umich.edu#if build_fixed_image != 0 19088007Ssaidi@eecs.umich.edu 19098007Ssaidi@eecs.umich.edu 19108007Ssaidi@eecs.umich.edu hw_rei_stall 19118007Ssaidi@eecs.umich.edu#else 19128007Ssaidi@eecs.umich.edu 19138007Ssaidi@eecs.umich.edu mfpr r9, pt_pcbb // get FEN 19148007Ssaidi@eecs.umich.edu#endif 19158007Ssaidi@eecs.umich.edu 19168007Ssaidi@eecs.umich.edu ldqp r9, osfpcb_q_fen(r9) 19178007Ssaidi@eecs.umich.edu blbc r9, no_pm_change_10_ // skip if FEN disabled 19188007Ssaidi@eecs.umich.edu 19198007Ssaidi@eecs.umich.edu mb // ensure no outstanding fills 19208007Ssaidi@eecs.umich.edu lda r12, 1<<dc_mode_v_dc_ena(r31) 19218007Ssaidi@eecs.umich.edu mtpr r12, dc_mode // turn dcache on so we can flush it 19228007Ssaidi@eecs.umich.edu nop // force correct slotting 19238007Ssaidi@eecs.umich.edu mfpr r31, pt0 // no mbox instructions in 1,2,3,4 19248007Ssaidi@eecs.umich.edu mfpr r31, pt0 // no mbox instructions in 1,2,3,4 19258007Ssaidi@eecs.umich.edu mfpr r31, pt0 // no mbox instructions in 1,2,3,4 19268007Ssaidi@eecs.umich.edu mfpr r31, pt0 // no mbox instructions in 1,2,3,4 19278007Ssaidi@eecs.umich.edu 19288007Ssaidi@eecs.umich.edu lda r8, 0(r31) // flood the dcache with junk data 19298007Ssaidi@eecs.umich.eduno_pm_change_5_: ldqp r31, 0(r8) 19308007Ssaidi@eecs.umich.edu lda r8, 0x20(r8) // touch each cache block 19318007Ssaidi@eecs.umich.edu srl r8, 13, r9 19328007Ssaidi@eecs.umich.edu blbc r9, no_pm_change_5_ 19338007Ssaidi@eecs.umich.edu 19348007Ssaidi@eecs.umich.edu mb // ensure no outstanding fills 19358007Ssaidi@eecs.umich.edu mtpr r31, dc_mode // turn the dcache back off 19368007Ssaidi@eecs.umich.edu nop // force correct slotting 19378007Ssaidi@eecs.umich.edu mfpr r31, pt0 // no hw_rei_stall in 0,1 19388007Ssaidi@eecs.umich.edu#endif 19398007Ssaidi@eecs.umich.edu 19408007Ssaidi@eecs.umich.edu 19418007Ssaidi@eecs.umich.eduno_pm_change_10_: hw_rei_stall // back we go 19428007Ssaidi@eecs.umich.edu 19438007Ssaidi@eecs.umich.edu ALIGN_BLOCK 19448007Ssaidi@eecs.umich.edu//+ 19458007Ssaidi@eecs.umich.edu// swppal_cont - finish up the swppal call_pal 19468007Ssaidi@eecs.umich.edu//- 19478007Ssaidi@eecs.umich.edu 19488007Ssaidi@eecs.umich.eduswppal_cont: 19498007Ssaidi@eecs.umich.edu mfpr r2, pt_misc // get misc bits 19508007Ssaidi@eecs.umich.edu sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit 19518007Ssaidi@eecs.umich.edu or r2, r0, r2 // set the bit 19528007Ssaidi@eecs.umich.edu mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) 19538007Ssaidi@eecs.umich.edu mtpr r2, pt_misc // update the chip 19548007Ssaidi@eecs.umich.edu 19558007Ssaidi@eecs.umich.edu or r3, r31, r4 19568007Ssaidi@eecs.umich.edu mfpr r3, pt_impure // pass pointer to the impure area in r3 19578007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r3 // adjust impure pointer for ipr read 19588007Ssaidi@eecs.umich.edu//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1 19598007Ssaidi@eecs.umich.edu//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2 19608007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r3 // restore impure pointer 19618007Ssaidi@eecs.umich.edu lda r3, CNS_Q_IPR(r3) 19628007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3); 19638007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3); 19648007Ssaidi@eecs.umich.edu lda r3, -CNS_Q_IPR(r3) 19658007Ssaidi@eecs.umich.edu 19668007Ssaidi@eecs.umich.edu or r31, r31, r0 // set status to success 19678007Ssaidi@eecs.umich.edu// pvc_violate 1007 19688007Ssaidi@eecs.umich.edu jmp r31, (r4) // and call our friend, it's her problem now 19698007Ssaidi@eecs.umich.edu 19708007Ssaidi@eecs.umich.edu 19718007Ssaidi@eecs.umich.eduswppal_fail: 19728007Ssaidi@eecs.umich.edu addq r0, 1, r0 // set unknown pal or not loaded 19738007Ssaidi@eecs.umich.edu hw_rei // and return 19748007Ssaidi@eecs.umich.edu 19758007Ssaidi@eecs.umich.edu 19768007Ssaidi@eecs.umich.edu// .sbttl "Memory management" 19778007Ssaidi@eecs.umich.edu 19788007Ssaidi@eecs.umich.edu ALIGN_BLOCK 19798007Ssaidi@eecs.umich.edu//+ 19808007Ssaidi@eecs.umich.edu//foe_ipte_handler 19818007Ssaidi@eecs.umich.edu// IFOE detected on level 3 pte, sort out FOE vs ACV 19828007Ssaidi@eecs.umich.edu// 19838007Ssaidi@eecs.umich.edu// on entry: 19848007Ssaidi@eecs.umich.edu// with 19858007Ssaidi@eecs.umich.edu// R8 = pte 19868007Ssaidi@eecs.umich.edu// R10 = pc 19878007Ssaidi@eecs.umich.edu// 19888007Ssaidi@eecs.umich.edu// Function 19898007Ssaidi@eecs.umich.edu// Determine TNV vs ACV vs FOE. Build stack and dispatch 19908007Ssaidi@eecs.umich.edu// Will not be here if TNV. 19918007Ssaidi@eecs.umich.edu//- 19928007Ssaidi@eecs.umich.edu 19938007Ssaidi@eecs.umich.edufoe_ipte_handler: 19948007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 19958007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 19968007Ssaidi@eecs.umich.edu 19978007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 19988007Ssaidi@eecs.umich.edu bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern 19998007Ssaidi@eecs.umich.edu 20008007Ssaidi@eecs.umich.edu 20018007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 20028007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 20038007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 20048007Ssaidi@eecs.umich.edu 20058007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 20068007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 20078007Ssaidi@eecs.umich.edu 20088007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 20098007Ssaidi@eecs.umich.edu nop 20108007Ssaidi@eecs.umich.edu 20118007Ssaidi@eecs.umich.edufoe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> 20128007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 20138007Ssaidi@eecs.umich.edu 20148007Ssaidi@eecs.umich.edu or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack 20158007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 20168007Ssaidi@eecs.umich.edu 20178007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 20188007Ssaidi@eecs.umich.edu or r14, r31, r16 // pass pc/va as a0 20198007Ssaidi@eecs.umich.edu 20208007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 20218007Ssaidi@eecs.umich.edu nop 20228007Ssaidi@eecs.umich.edu 20238007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 20248007Ssaidi@eecs.umich.edu lda r17, mmcsr_c_acv(r31) // assume ACV 20258007Ssaidi@eecs.umich.edu 20268007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 20278007Ssaidi@eecs.umich.edu cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE 20288007Ssaidi@eecs.umich.edu 20298007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save ps 20308007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream as a2 20318007Ssaidi@eecs.umich.edu 20328007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 20338007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 20348007Ssaidi@eecs.umich.edu 20358007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 20368007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 20378007Ssaidi@eecs.umich.edu 20388007Ssaidi@eecs.umich.edu ALIGN_BLOCK 20398007Ssaidi@eecs.umich.edu//+ 20408007Ssaidi@eecs.umich.edu//invalid_ipte_handler 20418007Ssaidi@eecs.umich.edu// TNV detected on level 3 pte, sort out TNV vs ACV 20428007Ssaidi@eecs.umich.edu// 20438007Ssaidi@eecs.umich.edu// on entry: 20448007Ssaidi@eecs.umich.edu// with 20458007Ssaidi@eecs.umich.edu// R8 = pte 20468007Ssaidi@eecs.umich.edu// R10 = pc 20478007Ssaidi@eecs.umich.edu// 20488007Ssaidi@eecs.umich.edu// Function 20498007Ssaidi@eecs.umich.edu// Determine TNV vs ACV. Build stack and dispatch. 20508007Ssaidi@eecs.umich.edu//- 20518007Ssaidi@eecs.umich.edu 20528007Ssaidi@eecs.umich.eduinvalid_ipte_handler: 20538007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 20548007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 20558007Ssaidi@eecs.umich.edu 20568007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 20578007Ssaidi@eecs.umich.edu bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern 20588007Ssaidi@eecs.umich.edu 20598007Ssaidi@eecs.umich.edu 20608007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 20618007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 20628007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 20638007Ssaidi@eecs.umich.edu 20648007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 20658007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 20668007Ssaidi@eecs.umich.edu 20678007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 20688007Ssaidi@eecs.umich.edu nop 20698007Ssaidi@eecs.umich.edu 20708007Ssaidi@eecs.umich.eduinvalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> 20718007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 20728007Ssaidi@eecs.umich.edu 20738007Ssaidi@eecs.umich.edu or r10, r31, r14 // Save pc/va in case TBmiss on stack 20748007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 20758007Ssaidi@eecs.umich.edu 20768007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 20778007Ssaidi@eecs.umich.edu or r14, r31, r16 // pass pc/va as a0 20788007Ssaidi@eecs.umich.edu 20798007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 20808007Ssaidi@eecs.umich.edu nop 20818007Ssaidi@eecs.umich.edu 20828007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 20838007Ssaidi@eecs.umich.edu and r25, 1, r17 // Isolate kre 20848007Ssaidi@eecs.umich.edu 20858007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 20868007Ssaidi@eecs.umich.edu xor r17, 1, r17 // map to acv/tnv as a1 20878007Ssaidi@eecs.umich.edu 20888007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save ps 20898007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream as a2 20908007Ssaidi@eecs.umich.edu 20918007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 20928007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 20938007Ssaidi@eecs.umich.edu 20948007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 20958007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 20968007Ssaidi@eecs.umich.edu 20978007Ssaidi@eecs.umich.edu 20988007Ssaidi@eecs.umich.edu 20998007Ssaidi@eecs.umich.edu 21008007Ssaidi@eecs.umich.edu ALIGN_BLOCK 21018007Ssaidi@eecs.umich.edu//+ 21028007Ssaidi@eecs.umich.edu//invalid_dpte_handler 21038007Ssaidi@eecs.umich.edu// INVALID detected on level 3 pte, sort out TNV vs ACV 21048007Ssaidi@eecs.umich.edu// 21058007Ssaidi@eecs.umich.edu// on entry: 21068007Ssaidi@eecs.umich.edu// with 21078007Ssaidi@eecs.umich.edu// R10 = va 21088007Ssaidi@eecs.umich.edu// R8 = pte 21098007Ssaidi@eecs.umich.edu// R9 = mm_stat 21108007Ssaidi@eecs.umich.edu// PT6 = pc 21118007Ssaidi@eecs.umich.edu// 21128007Ssaidi@eecs.umich.edu// Function 21138007Ssaidi@eecs.umich.edu// Determine TNV vs ACV. Build stack and dispatch 21148007Ssaidi@eecs.umich.edu//- 21158007Ssaidi@eecs.umich.edu 21168007Ssaidi@eecs.umich.edu 21178007Ssaidi@eecs.umich.eduinvalid_dpte_handler: 21188007Ssaidi@eecs.umich.edu mfpr r12, pt6 21198007Ssaidi@eecs.umich.edu blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode 21208007Ssaidi@eecs.umich.edu 21218007Ssaidi@eecs.umich.edu bis r12, r31, r14 // save PC in case of tbmiss or fault 21228007Ssaidi@eecs.umich.edu srl r9, mm_stat_v_opcode, r25 // shift opc to <0> 21238007Ssaidi@eecs.umich.edu 21248007Ssaidi@eecs.umich.edu mtpr r11, pt0 // Save PS for stack write 21258007Ssaidi@eecs.umich.edu and r25, mm_stat_m_opcode, r25 // isolate opcode 21268007Ssaidi@eecs.umich.edu 21278007Ssaidi@eecs.umich.edu cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M? 21288007Ssaidi@eecs.umich.edu blbs r25, nmiss_fetch_ldr31_err // yes 21298007Ssaidi@eecs.umich.edu 21308007Ssaidi@eecs.umich.edu //dismiss exception if load to r31/f31 21318007Ssaidi@eecs.umich.edu blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm 21328007Ssaidi@eecs.umich.edu 21338007Ssaidi@eecs.umich.edu // not a store or fetch, must be a load 21348007Ssaidi@eecs.umich.edu srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits 21358007Ssaidi@eecs.umich.edu 21368007Ssaidi@eecs.umich.edu and r25, 0x1F, r25 // isolate rnum 21378007Ssaidi@eecs.umich.edu nop 21388007Ssaidi@eecs.umich.edu 21398007Ssaidi@eecs.umich.edu cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31? 21408007Ssaidi@eecs.umich.edu bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault 21418007Ssaidi@eecs.umich.edu 21428007Ssaidi@eecs.umich.eduinvalid_dpte_no_dismiss: 21438007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 21448007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 21458007Ssaidi@eecs.umich.edu 21468007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 21478007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 21488007Ssaidi@eecs.umich.edu bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern 21498007Ssaidi@eecs.umich.edu 21508007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 21518007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 21528007Ssaidi@eecs.umich.edu 21538007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 21548007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 21558007Ssaidi@eecs.umich.edu 21568007Ssaidi@eecs.umich.eduinvalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0> 21578007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 21588007Ssaidi@eecs.umich.edu 21598007Ssaidi@eecs.umich.edu or r10, r31, r25 // Save va in case TBmiss on stack 21608007Ssaidi@eecs.umich.edu and r9, 1, r13 // save r/w flag 21618007Ssaidi@eecs.umich.edu 21628007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 21638007Ssaidi@eecs.umich.edu or r25, r31, r16 // pass va as a0 21648007Ssaidi@eecs.umich.edu 21658007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 21668007Ssaidi@eecs.umich.edu or r31, mmcsr_c_acv, r17 // assume acv 21678007Ssaidi@eecs.umich.edu 21688007Ssaidi@eecs.umich.edu srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0> 21698007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 21708007Ssaidi@eecs.umich.edu 21718007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 21728007Ssaidi@eecs.umich.edu cmovlbs r13, r25, r12 // if write access move acv based on write enable 21738007Ssaidi@eecs.umich.edu 21748007Ssaidi@eecs.umich.edu or r13, r31, r18 // pass flag of dstream access and read vs write 21758007Ssaidi@eecs.umich.edu mfpr r25, pt0 // get ps 21768007Ssaidi@eecs.umich.edu 21778007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 21788007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 21798007Ssaidi@eecs.umich.edu 21808007Ssaidi@eecs.umich.edu stq r25, osfsf_ps(sp) // save ps 21818007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 21828007Ssaidi@eecs.umich.edu 21838007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 21848007Ssaidi@eecs.umich.edu cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv 21858007Ssaidi@eecs.umich.edu 21868007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 21878007Ssaidi@eecs.umich.edu 21888007Ssaidi@eecs.umich.edu//+ 21898007Ssaidi@eecs.umich.edu// 21908007Ssaidi@eecs.umich.edu// We come here if we are erring on a dtb_miss, and the instr is a 21918007Ssaidi@eecs.umich.edu// fetch, fetch_m, of load to r31/f31. 21928007Ssaidi@eecs.umich.edu// The PC is incremented, and we return to the program. 21938007Ssaidi@eecs.umich.edu// essentially ignoring the instruction and error. 21948007Ssaidi@eecs.umich.edu// 21958007Ssaidi@eecs.umich.edu//- 21968007Ssaidi@eecs.umich.edu ALIGN_BLOCK 21978007Ssaidi@eecs.umich.edunmiss_fetch_ldr31_err: 21988007Ssaidi@eecs.umich.edu mfpr r12, pt6 21998007Ssaidi@eecs.umich.edu addq r12, 4, r12 // bump pc to pc+4 22008007Ssaidi@eecs.umich.edu 22018007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // and set entry point 22028007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad exc_addr write 22038007Ssaidi@eecs.umich.edu 22048007Ssaidi@eecs.umich.edu hw_rei // 22058007Ssaidi@eecs.umich.edu 22068007Ssaidi@eecs.umich.edu ALIGN_BLOCK 22078007Ssaidi@eecs.umich.edu//+ 22088007Ssaidi@eecs.umich.edu// double_pte_inv 22098007Ssaidi@eecs.umich.edu// We had a single tbmiss which turned into a double tbmiss which found 22108007Ssaidi@eecs.umich.edu// an invalid PTE. Return to single miss with a fake pte, and the invalid 22118007Ssaidi@eecs.umich.edu// single miss flow will report the error. 22128007Ssaidi@eecs.umich.edu// 22138007Ssaidi@eecs.umich.edu// on entry: 22148007Ssaidi@eecs.umich.edu// r21 PTE 22158007Ssaidi@eecs.umich.edu// r22 available 22168007Ssaidi@eecs.umich.edu// VA IPR locked with original fault VA 22178007Ssaidi@eecs.umich.edu// pt4 saved r21 22188007Ssaidi@eecs.umich.edu// pt5 saved r22 22198007Ssaidi@eecs.umich.edu// pt6 original exc_addr 22208007Ssaidi@eecs.umich.edu// 22218007Ssaidi@eecs.umich.edu// on return to tbmiss flow: 22228007Ssaidi@eecs.umich.edu// r8 fake PTE 22238007Ssaidi@eecs.umich.edu// 22248007Ssaidi@eecs.umich.edu// 22258007Ssaidi@eecs.umich.edu//- 22268007Ssaidi@eecs.umich.edudouble_pte_inv: 22278007Ssaidi@eecs.umich.edu srl r21, osfpte_v_kre, r21 // get the kre bit to <0> 22288007Ssaidi@eecs.umich.edu mfpr r22, exc_addr // get the pc 22298007Ssaidi@eecs.umich.edu 22308007Ssaidi@eecs.umich.edu lda r22, 4(r22) // inc the pc 22318007Ssaidi@eecs.umich.edu lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set 22328007Ssaidi@eecs.umich.edu 22338007Ssaidi@eecs.umich.edu cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0 22348007Ssaidi@eecs.umich.edu mtpr r22, exc_addr // set for rei 22358007Ssaidi@eecs.umich.edu 22368007Ssaidi@eecs.umich.edu mfpr r21, pt4 // restore regs 22378007Ssaidi@eecs.umich.edu mfpr r22, pt5 // restore regs 22388007Ssaidi@eecs.umich.edu 22398007Ssaidi@eecs.umich.edu hw_rei // back to tb miss 22408007Ssaidi@eecs.umich.edu 22418007Ssaidi@eecs.umich.edu ALIGN_BLOCK 22428007Ssaidi@eecs.umich.edu//+ 22438007Ssaidi@eecs.umich.edu//tnv_in_pal 22448007Ssaidi@eecs.umich.edu// The only places in pal that ld or store are the 22458007Ssaidi@eecs.umich.edu// stack builders, rti or retsys. Any of these mean we 22468007Ssaidi@eecs.umich.edu// need to take a ksp not valid halt. 22478007Ssaidi@eecs.umich.edu// 22488007Ssaidi@eecs.umich.edu//- 22498007Ssaidi@eecs.umich.edutnv_in_pal: 22508007Ssaidi@eecs.umich.edu 22518007Ssaidi@eecs.umich.edu 22528007Ssaidi@eecs.umich.edu br r31, ksp_inval_halt 22538007Ssaidi@eecs.umich.edu 22548007Ssaidi@eecs.umich.edu 22558007Ssaidi@eecs.umich.edu// .sbttl "Icache flush routines" 22568007Ssaidi@eecs.umich.edu 22578007Ssaidi@eecs.umich.edu ALIGN_BLOCK 22588007Ssaidi@eecs.umich.edu//+ 22598007Ssaidi@eecs.umich.edu// Common Icache flush routine. 22608007Ssaidi@eecs.umich.edu// 22618007Ssaidi@eecs.umich.edu// 22628007Ssaidi@eecs.umich.edu//- 22638007Ssaidi@eecs.umich.edupal_ic_flush: 22648007Ssaidi@eecs.umich.edu nop 22658007Ssaidi@eecs.umich.edu mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 22668007Ssaidi@eecs.umich.edu nop 22678007Ssaidi@eecs.umich.edu nop 22688007Ssaidi@eecs.umich.edu 22698007Ssaidi@eecs.umich.edu// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 22708007Ssaidi@eecs.umich.edu nop 22718007Ssaidi@eecs.umich.edu nop 22728007Ssaidi@eecs.umich.edu nop 22738007Ssaidi@eecs.umich.edu nop 22748007Ssaidi@eecs.umich.edu 22758007Ssaidi@eecs.umich.edu nop 22768007Ssaidi@eecs.umich.edu nop 22778007Ssaidi@eecs.umich.edu nop 22788007Ssaidi@eecs.umich.edu nop 22798007Ssaidi@eecs.umich.edu 22808007Ssaidi@eecs.umich.edu nop 22818007Ssaidi@eecs.umich.edu nop // 10 22828007Ssaidi@eecs.umich.edu 22838007Ssaidi@eecs.umich.edu nop 22848007Ssaidi@eecs.umich.edu nop 22858007Ssaidi@eecs.umich.edu nop 22868007Ssaidi@eecs.umich.edu nop 22878007Ssaidi@eecs.umich.edu 22888007Ssaidi@eecs.umich.edu nop 22898007Ssaidi@eecs.umich.edu nop 22908007Ssaidi@eecs.umich.edu nop 22918007Ssaidi@eecs.umich.edu nop 22928007Ssaidi@eecs.umich.edu 22938007Ssaidi@eecs.umich.edu nop 22948007Ssaidi@eecs.umich.edu nop // 20 22958007Ssaidi@eecs.umich.edu 22968007Ssaidi@eecs.umich.edu nop 22978007Ssaidi@eecs.umich.edu nop 22988007Ssaidi@eecs.umich.edu nop 22998007Ssaidi@eecs.umich.edu nop 23008007Ssaidi@eecs.umich.edu 23018007Ssaidi@eecs.umich.edu nop 23028007Ssaidi@eecs.umich.edu nop 23038007Ssaidi@eecs.umich.edu nop 23048007Ssaidi@eecs.umich.edu nop 23058007Ssaidi@eecs.umich.edu 23068007Ssaidi@eecs.umich.edu nop 23078007Ssaidi@eecs.umich.edu nop // 30 23088007Ssaidi@eecs.umich.edu nop 23098007Ssaidi@eecs.umich.edu nop 23108007Ssaidi@eecs.umich.edu nop 23118007Ssaidi@eecs.umich.edu nop 23128007Ssaidi@eecs.umich.edu 23138007Ssaidi@eecs.umich.edu nop 23148007Ssaidi@eecs.umich.edu nop 23158007Ssaidi@eecs.umich.edu nop 23168007Ssaidi@eecs.umich.edu nop 23178007Ssaidi@eecs.umich.edu 23188007Ssaidi@eecs.umich.edu nop 23198007Ssaidi@eecs.umich.edu nop // 40 23208007Ssaidi@eecs.umich.edu 23218007Ssaidi@eecs.umich.edu nop 23228007Ssaidi@eecs.umich.edu nop 23238007Ssaidi@eecs.umich.edu 23248007Ssaidi@eecs.umich.eduone_cycle_and_hw_rei: 23258007Ssaidi@eecs.umich.edu nop 23268007Ssaidi@eecs.umich.edu nop 23278007Ssaidi@eecs.umich.edu 23288007Ssaidi@eecs.umich.edu hw_rei_stall 23298007Ssaidi@eecs.umich.edu 23308007Ssaidi@eecs.umich.edu#if icflush_on_tbix != 0 23318007Ssaidi@eecs.umich.edu 23328007Ssaidi@eecs.umich.edu 23338007Ssaidi@eecs.umich.edu ALIGN_BLOCK 23348007Ssaidi@eecs.umich.edu 23358007Ssaidi@eecs.umich.edu//+ 23368007Ssaidi@eecs.umich.edu// Common Icache flush and ITB invalidate single routine. 23378007Ssaidi@eecs.umich.edu// ITBIS and hw_rei_stall must be in same octaword. 23388007Ssaidi@eecs.umich.edu// r17 - has address to invalidate 23398007Ssaidi@eecs.umich.edu// 23408007Ssaidi@eecs.umich.edu//- 23418007Ssaidi@eecs.umich.eduPAL_IC_FLUSH_AND_TBISI: 23428007Ssaidi@eecs.umich.edu nop 23438007Ssaidi@eecs.umich.edu mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 23448007Ssaidi@eecs.umich.edu nop 23458007Ssaidi@eecs.umich.edu nop 23468007Ssaidi@eecs.umich.edu 23478007Ssaidi@eecs.umich.edu// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 23488007Ssaidi@eecs.umich.edu nop 23498007Ssaidi@eecs.umich.edu nop 23508007Ssaidi@eecs.umich.edu nop 23518007Ssaidi@eecs.umich.edu nop 23528007Ssaidi@eecs.umich.edu 23538007Ssaidi@eecs.umich.edu nop 23548007Ssaidi@eecs.umich.edu nop 23558007Ssaidi@eecs.umich.edu nop 23568007Ssaidi@eecs.umich.edu nop 23578007Ssaidi@eecs.umich.edu 23588007Ssaidi@eecs.umich.edu nop 23598007Ssaidi@eecs.umich.edu nop // 10 23608007Ssaidi@eecs.umich.edu 23618007Ssaidi@eecs.umich.edu nop 23628007Ssaidi@eecs.umich.edu nop 23638007Ssaidi@eecs.umich.edu nop 23648007Ssaidi@eecs.umich.edu nop 23658007Ssaidi@eecs.umich.edu 23668007Ssaidi@eecs.umich.edu nop 23678007Ssaidi@eecs.umich.edu nop 23688007Ssaidi@eecs.umich.edu nop 23698007Ssaidi@eecs.umich.edu nop 23708007Ssaidi@eecs.umich.edu 23718007Ssaidi@eecs.umich.edu nop 23728007Ssaidi@eecs.umich.edu nop // 20 23738007Ssaidi@eecs.umich.edu 23748007Ssaidi@eecs.umich.edu nop 23758007Ssaidi@eecs.umich.edu nop 23768007Ssaidi@eecs.umich.edu nop 23778007Ssaidi@eecs.umich.edu nop 23788007Ssaidi@eecs.umich.edu 23798007Ssaidi@eecs.umich.edu nop 23808007Ssaidi@eecs.umich.edu nop 23818007Ssaidi@eecs.umich.edu nop 23828007Ssaidi@eecs.umich.edu nop 23838007Ssaidi@eecs.umich.edu 23848007Ssaidi@eecs.umich.edu nop 23858007Ssaidi@eecs.umich.edu nop // 30 23868007Ssaidi@eecs.umich.edu nop 23878007Ssaidi@eecs.umich.edu nop 23888007Ssaidi@eecs.umich.edu nop 23898007Ssaidi@eecs.umich.edu nop 23908007Ssaidi@eecs.umich.edu 23918007Ssaidi@eecs.umich.edu nop 23928007Ssaidi@eecs.umich.edu nop 23938007Ssaidi@eecs.umich.edu nop 23948007Ssaidi@eecs.umich.edu nop 23958007Ssaidi@eecs.umich.edu 23968007Ssaidi@eecs.umich.edu nop 23978007Ssaidi@eecs.umich.edu nop // 40 23988007Ssaidi@eecs.umich.edu 23998007Ssaidi@eecs.umich.edu 24008007Ssaidi@eecs.umich.edu nop 24018007Ssaidi@eecs.umich.edu nop 24028007Ssaidi@eecs.umich.edu 24038007Ssaidi@eecs.umich.edu nop 24048007Ssaidi@eecs.umich.edu nop 24058007Ssaidi@eecs.umich.edu 24068007Ssaidi@eecs.umich.edu // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions 24078007Ssaidi@eecs.umich.edu // 44 nops plus 4 instructions before it is 48 instructions. 24088007Ssaidi@eecs.umich.edu // Since this routine started on a 32-byte (8 instruction) boundary, 24098007Ssaidi@eecs.umich.edu // the following 2 instructions will be in the same octword as required. 24108007Ssaidi@eecs.umich.edu// ALIGN_BRANCH 24118007Ssaidi@eecs.umich.edu mtpr r17, ev5__itb_is // Flush ITB 24128007Ssaidi@eecs.umich.edu hw_rei_stall 24138007Ssaidi@eecs.umich.edu 24148007Ssaidi@eecs.umich.edu#endif 24158007Ssaidi@eecs.umich.edu 24168007Ssaidi@eecs.umich.edu ALIGN_BLOCK 24178007Ssaidi@eecs.umich.edu//+ 24188007Ssaidi@eecs.umich.edu//osfpal_calpal_opcdec 24198007Ssaidi@eecs.umich.edu// Here for all opcdec CALL_PALs 24208007Ssaidi@eecs.umich.edu// 24218007Ssaidi@eecs.umich.edu// Build stack frame 24228007Ssaidi@eecs.umich.edu// a0 <- code 24238007Ssaidi@eecs.umich.edu// a1 <- unpred 24248007Ssaidi@eecs.umich.edu// a2 <- unpred 24258007Ssaidi@eecs.umich.edu// vector via entIF 24268007Ssaidi@eecs.umich.edu// 24278007Ssaidi@eecs.umich.edu//- 24288007Ssaidi@eecs.umich.edu 24298007Ssaidi@eecs.umich.eduosfpal_calpal_opcdec: 24308007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 24318007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 24328007Ssaidi@eecs.umich.edu 24338007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 24348007Ssaidi@eecs.umich.edu nop 24358007Ssaidi@eecs.umich.edu 24368007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 24378007Ssaidi@eecs.umich.edu bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern 24388007Ssaidi@eecs.umich.edu 24398007Ssaidi@eecs.umich.edu 24408007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 24418007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 24428007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 24438007Ssaidi@eecs.umich.edu 24448007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 24458007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 24468007Ssaidi@eecs.umich.edu 24478007Ssaidi@eecs.umich.eduosfpal_calpal_opcdec_10_: 24488007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 24498007Ssaidi@eecs.umich.edu nop 24508007Ssaidi@eecs.umich.edu 24518007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 24528007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 24538007Ssaidi@eecs.umich.edu 24548007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 24558007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 24568007Ssaidi@eecs.umich.edu 24578007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save old ps 24588007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 24598007Ssaidi@eecs.umich.edu 24608007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 24618007Ssaidi@eecs.umich.edu nop 24628007Ssaidi@eecs.umich.edu 24638007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 24648007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 24658007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 24668007Ssaidi@eecs.umich.edu 24678007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 24688007Ssaidi@eecs.umich.edu 24698007Ssaidi@eecs.umich.edu 24708007Ssaidi@eecs.umich.edu hw_rei_spe // done 24718007Ssaidi@eecs.umich.edu 24728007Ssaidi@eecs.umich.edu 24738007Ssaidi@eecs.umich.edu 24748007Ssaidi@eecs.umich.edu 24758007Ssaidi@eecs.umich.edu 24768007Ssaidi@eecs.umich.edu//+ 24778007Ssaidi@eecs.umich.edu//pal_update_pcb 24788007Ssaidi@eecs.umich.edu// Update the PCB with the current SP, AST, and CC info 24798007Ssaidi@eecs.umich.edu// 24808007Ssaidi@eecs.umich.edu// r0 - return linkage 24818007Ssaidi@eecs.umich.edu//- 24828007Ssaidi@eecs.umich.edu ALIGN_BLOCK 24838007Ssaidi@eecs.umich.edu 24848007Ssaidi@eecs.umich.edupal_update_pcb: 24858007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // get pcbb 24868007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r25 // get mode 24878007Ssaidi@eecs.umich.edu beq r25, pal_update_pcb_10_ // in kern? no need to update user sp 24888007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 24898007Ssaidi@eecs.umich.edu stqp r30, osfpcb_q_usp(r12) // store usp 24908007Ssaidi@eecs.umich.edu br r31, pal_update_pcb_20_ // join common 24918007Ssaidi@eecs.umich.edupal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp 24928007Ssaidi@eecs.umich.edupal_update_pcb_20_: rpcc r13 // get cyccounter 24938007Ssaidi@eecs.umich.edu srl r13, 32, r14 // move offset 24948007Ssaidi@eecs.umich.edu addl r13, r14, r14 // merge for new time 24958007Ssaidi@eecs.umich.edu stlp r14, osfpcb_l_cc(r12) // save time 24968007Ssaidi@eecs.umich.edu 24978007Ssaidi@eecs.umich.edu//orig pvc_jsr updpcb, bsr=1, dest=1 24988007Ssaidi@eecs.umich.edu ret r31, (r0) 24998007Ssaidi@eecs.umich.edu 25008007Ssaidi@eecs.umich.edu 25018007Ssaidi@eecs.umich.edu 25028007Ssaidi@eecs.umich.edu#if remove_save_state == 0 25038007Ssaidi@eecs.umich.edu 25048007Ssaidi@eecs.umich.edu// .sbttl "PAL_SAVE_STATE" 25058007Ssaidi@eecs.umich.edu//+ 25068007Ssaidi@eecs.umich.edu// 25078007Ssaidi@eecs.umich.edu// Pal_save_state 25088007Ssaidi@eecs.umich.edu// 25098007Ssaidi@eecs.umich.edu// Function 25108007Ssaidi@eecs.umich.edu// All chip state saved, all PT's, SR's FR's, IPR's 25118007Ssaidi@eecs.umich.edu// 25128007Ssaidi@eecs.umich.edu// 25138007Ssaidi@eecs.umich.edu// Regs' on entry... 25148007Ssaidi@eecs.umich.edu// 25158007Ssaidi@eecs.umich.edu// R0 = halt code 25168007Ssaidi@eecs.umich.edu// pt0 = r0 25178007Ssaidi@eecs.umich.edu// R1 = pointer to impure 25188007Ssaidi@eecs.umich.edu// pt4 = r1 25198007Ssaidi@eecs.umich.edu// R3 = return addr 25208007Ssaidi@eecs.umich.edu// pt5 = r3 25218007Ssaidi@eecs.umich.edu// 25228007Ssaidi@eecs.umich.edu// register usage: 25238007Ssaidi@eecs.umich.edu// r0 = halt_code 25248007Ssaidi@eecs.umich.edu// r1 = addr of impure area 25258007Ssaidi@eecs.umich.edu// r3 = return_address 25268007Ssaidi@eecs.umich.edu// r4 = scratch 25278007Ssaidi@eecs.umich.edu// 25288007Ssaidi@eecs.umich.edu//- 25298007Ssaidi@eecs.umich.edu 25308007Ssaidi@eecs.umich.edu 25318007Ssaidi@eecs.umich.edu ALIGN_BLOCK 25328007Ssaidi@eecs.umich.edu .globl pal_save_state 25338007Ssaidi@eecs.umich.edupal_save_state: 25348007Ssaidi@eecs.umich.edu// 25358007Ssaidi@eecs.umich.edu// 25368007Ssaidi@eecs.umich.edu// start of implementation independent save routine 25378007Ssaidi@eecs.umich.edu// 25388007Ssaidi@eecs.umich.edu// the impure area is larger than the addressibility of hw_ld and hw_st 25398007Ssaidi@eecs.umich.edu// therefore, we need to play some games: The impure area 25408007Ssaidi@eecs.umich.edu// is informally divided into the "machine independent" part and the 25418007Ssaidi@eecs.umich.edu// "machine dependent" part. The state that will be saved in the 25428007Ssaidi@eecs.umich.edu// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros). 25438007Ssaidi@eecs.umich.edu// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros). 25448007Ssaidi@eecs.umich.edu// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg 25458007Ssaidi@eecs.umich.edu// macros will automagically adjust the offset correctly. 25468007Ssaidi@eecs.umich.edu// 25478007Ssaidi@eecs.umich.edu 25488007Ssaidi@eecs.umich.edu// The distributed code is commented out and followed by corresponding SRC code. 25498007Ssaidi@eecs.umich.edu// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0) 25508007Ssaidi@eecs.umich.edu 25518007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area 25528007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 25538007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag 25548007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag 25558007Ssaidi@eecs.umich.edu//orig store_reg1 hlt, r0, r1, ipr=1 25568007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code 25578007Ssaidi@eecs.umich.edu 25588007Ssaidi@eecs.umich.edu mfpr r0, pt0 // get r0 back //orig 25598007Ssaidi@eecs.umich.edu//orig store_reg1 0, r0, r1 // save r0 25608007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0 25618007Ssaidi@eecs.umich.edu 25628007Ssaidi@eecs.umich.edu mfpr r0, pt4 // get r1 back //orig 25638007Ssaidi@eecs.umich.edu//orig store_reg1 1, r0, r1 // save r1 25648007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1 25658007Ssaidi@eecs.umich.edu 25668007Ssaidi@eecs.umich.edu//orig store_reg 2 // save r2 25678007Ssaidi@eecs.umich.edu SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2 25688007Ssaidi@eecs.umich.edu 25698007Ssaidi@eecs.umich.edu mfpr r0, pt5 // get r3 back //orig 25708007Ssaidi@eecs.umich.edu//orig store_reg1 3, r0, r1 // save r3 25718007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3 25728007Ssaidi@eecs.umich.edu 25738007Ssaidi@eecs.umich.edu // reason code has been saved 25748007Ssaidi@eecs.umich.edu // r0 has been saved 25758007Ssaidi@eecs.umich.edu // r1 has been saved 25768007Ssaidi@eecs.umich.edu // r2 has been saved 25778007Ssaidi@eecs.umich.edu // r3 has been saved 25788007Ssaidi@eecs.umich.edu // pt0, pt4, pt5 have been lost 25798007Ssaidi@eecs.umich.edu 25808007Ssaidi@eecs.umich.edu // 25818007Ssaidi@eecs.umich.edu // Get out of shadow mode 25828007Ssaidi@eecs.umich.edu // 25838007Ssaidi@eecs.umich.edu 25848007Ssaidi@eecs.umich.edu mfpr r2, icsr // Get icsr //orig 25858007Ssaidi@eecs.umich.edu//orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location 25868007Ssaidi@eecs.umich.edu ldah r0, (1<<(icsr_v_sde-16))(r31) 25878007Ssaidi@eecs.umich.edu bic r2, r0, r0 // ICSR with SDE clear //orig 25888007Ssaidi@eecs.umich.edu mtpr r0, icsr // Turn off SDE //orig 25898007Ssaidi@eecs.umich.edu 25908007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 1 //orig 25918007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 2 //orig 25928007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 3 //orig 25938007Ssaidi@eecs.umich.edu nop //orig 25948007Ssaidi@eecs.umich.edu 25958007Ssaidi@eecs.umich.edu 25968007Ssaidi@eecs.umich.edu // save integer regs R4-r31 25978007Ssaidi@eecs.umich.edu//orig #define t 4 25988007Ssaidi@eecs.umich.edu//orig .repeat 28 25998007Ssaidi@eecs.umich.edu//orig store_reg \t 26008007Ssaidi@eecs.umich.edu//orig #define t t + 1 26018007Ssaidi@eecs.umich.edu//orig .endr 26028007Ssaidi@eecs.umich.edu SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) 26038007Ssaidi@eecs.umich.edu SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) 26048007Ssaidi@eecs.umich.edu SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) 26058007Ssaidi@eecs.umich.edu SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) 26068007Ssaidi@eecs.umich.edu SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) 26078007Ssaidi@eecs.umich.edu SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) 26088007Ssaidi@eecs.umich.edu SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) 26098007Ssaidi@eecs.umich.edu SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) 26108007Ssaidi@eecs.umich.edu SAVE_GPR(r12,CNS_Q_GPR+0x60,r1) 26118007Ssaidi@eecs.umich.edu SAVE_GPR(r13,CNS_Q_GPR+0x68,r1) 26128007Ssaidi@eecs.umich.edu SAVE_GPR(r14,CNS_Q_GPR+0x70,r1) 26138007Ssaidi@eecs.umich.edu SAVE_GPR(r15,CNS_Q_GPR+0x78,r1) 26148007Ssaidi@eecs.umich.edu SAVE_GPR(r16,CNS_Q_GPR+0x80,r1) 26158007Ssaidi@eecs.umich.edu SAVE_GPR(r17,CNS_Q_GPR+0x88,r1) 26168007Ssaidi@eecs.umich.edu SAVE_GPR(r18,CNS_Q_GPR+0x90,r1) 26178007Ssaidi@eecs.umich.edu SAVE_GPR(r19,CNS_Q_GPR+0x98,r1) 26188007Ssaidi@eecs.umich.edu SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1) 26198007Ssaidi@eecs.umich.edu SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1) 26208007Ssaidi@eecs.umich.edu SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1) 26218007Ssaidi@eecs.umich.edu SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1) 26228007Ssaidi@eecs.umich.edu SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1) 26238007Ssaidi@eecs.umich.edu SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1) 26248007Ssaidi@eecs.umich.edu SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1) 26258007Ssaidi@eecs.umich.edu SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1) 26268007Ssaidi@eecs.umich.edu SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1) 26278007Ssaidi@eecs.umich.edu SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) 26288007Ssaidi@eecs.umich.edu SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) 26298007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) 26308007Ssaidi@eecs.umich.edu 26318007Ssaidi@eecs.umich.edu // save all paltemp regs except pt0 26328007Ssaidi@eecs.umich.edu 26338007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores 26348007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores 26358007Ssaidi@eecs.umich.edu//orig #define t 1 26368007Ssaidi@eecs.umich.edu//orig .repeat 23 26378007Ssaidi@eecs.umich.edu//orig store_reg \t , pal=1 26388007Ssaidi@eecs.umich.edu//orig #define t t + 1 26398007Ssaidi@eecs.umich.edu//orig .endr 26408007Ssaidi@eecs.umich.edu 26418007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore the impure base address. 26428007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. 26438007Ssaidi@eecs.umich.edu SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 26448007Ssaidi@eecs.umich.edu SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) 26458007Ssaidi@eecs.umich.edu SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) 26468007Ssaidi@eecs.umich.edu SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) 26478007Ssaidi@eecs.umich.edu SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) 26488007Ssaidi@eecs.umich.edu SAVE_IPR(pt5,CNS_Q_PT+0x28,r1) 26498007Ssaidi@eecs.umich.edu SAVE_IPR(pt6,CNS_Q_PT+0x30,r1) 26508007Ssaidi@eecs.umich.edu SAVE_IPR(pt7,CNS_Q_PT+0x38,r1) 26518007Ssaidi@eecs.umich.edu SAVE_IPR(pt8,CNS_Q_PT+0x40,r1) 26528007Ssaidi@eecs.umich.edu SAVE_IPR(pt9,CNS_Q_PT+0x48,r1) 26538007Ssaidi@eecs.umich.edu SAVE_IPR(pt10,CNS_Q_PT+0x50,r1) 26548007Ssaidi@eecs.umich.edu SAVE_IPR(pt11,CNS_Q_PT+0x58,r1) 26558007Ssaidi@eecs.umich.edu SAVE_IPR(pt12,CNS_Q_PT+0x60,r1) 26568007Ssaidi@eecs.umich.edu SAVE_IPR(pt13,CNS_Q_PT+0x68,r1) 26578007Ssaidi@eecs.umich.edu SAVE_IPR(pt14,CNS_Q_PT+0x70,r1) 26588007Ssaidi@eecs.umich.edu SAVE_IPR(pt15,CNS_Q_PT+0x78,r1) 26598007Ssaidi@eecs.umich.edu SAVE_IPR(pt16,CNS_Q_PT+0x80,r1) 26608007Ssaidi@eecs.umich.edu SAVE_IPR(pt17,CNS_Q_PT+0x88,r1) 26618007Ssaidi@eecs.umich.edu SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) 26628007Ssaidi@eecs.umich.edu SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) 26638007Ssaidi@eecs.umich.edu SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) 26648007Ssaidi@eecs.umich.edu SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) 26658007Ssaidi@eecs.umich.edu SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) 26668007Ssaidi@eecs.umich.edu SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) 26678007Ssaidi@eecs.umich.edu 26688007Ssaidi@eecs.umich.edu // Restore shadow mode 26698007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig 26708007Ssaidi@eecs.umich.edu mfpr r31, pt0 //orig 26718007Ssaidi@eecs.umich.edu mtpr r2, icsr // Restore original ICSR //orig 26728007Ssaidi@eecs.umich.edu 26738007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 1 //orig 26748007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 2 //orig 26758007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 3 //orig 26768007Ssaidi@eecs.umich.edu nop //orig 26778007Ssaidi@eecs.umich.edu 26788007Ssaidi@eecs.umich.edu // save all integer shadow regs 26798007Ssaidi@eecs.umich.edu 26808007Ssaidi@eecs.umich.edu//orig #define t 8 26818007Ssaidi@eecs.umich.edu//orig .repeat 7 26828007Ssaidi@eecs.umich.edu//orig store_reg \t, shadow=1 26838007Ssaidi@eecs.umich.edu//orig #define t t + 1 26848007Ssaidi@eecs.umich.edu//orig .endr 26858007Ssaidi@eecs.umich.edu//orig store_reg 25, shadow=1 26868007Ssaidi@eecs.umich.edu 26878007Ssaidi@eecs.umich.edu SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 26888007Ssaidi@eecs.umich.edu SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 26898007Ssaidi@eecs.umich.edu SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 26908007Ssaidi@eecs.umich.edu SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 26918007Ssaidi@eecs.umich.edu SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 26928007Ssaidi@eecs.umich.edu SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 26938007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 26948007Ssaidi@eecs.umich.edu SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 26958007Ssaidi@eecs.umich.edu 26968007Ssaidi@eecs.umich.edu//orig store_reg exc_addr, ipr=1 // save ipr 26978007Ssaidi@eecs.umich.edu//orig store_reg pal_base, ipr=1 // save ipr 26988007Ssaidi@eecs.umich.edu//orig store_reg mm_stat, ipr=1 // save ipr 26998007Ssaidi@eecs.umich.edu//orig store_reg va, ipr=1 // save ipr 27008007Ssaidi@eecs.umich.edu//orig store_reg icsr, ipr=1 // save ipr 27018007Ssaidi@eecs.umich.edu//orig store_reg ipl, ipr=1 // save ipr 27028007Ssaidi@eecs.umich.edu//orig store_reg ps, ipr=1 // save ipr 27038007Ssaidi@eecs.umich.edu//orig store_reg itb_asn, ipr=1 // save ipr 27048007Ssaidi@eecs.umich.edu//orig store_reg aster, ipr=1 // save ipr 27058007Ssaidi@eecs.umich.edu//orig store_reg astrr, ipr=1 // save ipr 27068007Ssaidi@eecs.umich.edu//orig store_reg sirr, ipr=1 // save ipr 27078007Ssaidi@eecs.umich.edu//orig store_reg isr, ipr=1 // save ipr 27088007Ssaidi@eecs.umich.edu//orig store_reg ivptbr, ipr=1 // save ipr 27098007Ssaidi@eecs.umich.edu//orig store_reg mcsr, ipr=1 // save ipr 27108007Ssaidi@eecs.umich.edu//orig store_reg dc_mode, ipr=1 // save ipr 27118007Ssaidi@eecs.umich.edu 27128007Ssaidi@eecs.umich.edu SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 27138007Ssaidi@eecs.umich.edu SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) 27148007Ssaidi@eecs.umich.edu SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) 27158007Ssaidi@eecs.umich.edu SAVE_IPR(va,CNS_Q_VA,r1) 27168007Ssaidi@eecs.umich.edu SAVE_IPR(icsr,CNS_Q_ICSR,r1) 27178007Ssaidi@eecs.umich.edu SAVE_IPR(ipl,CNS_Q_IPL,r1) 27188007Ssaidi@eecs.umich.edu SAVE_IPR(ips,CNS_Q_IPS,r1) 27198007Ssaidi@eecs.umich.edu SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) 27208007Ssaidi@eecs.umich.edu SAVE_IPR(aster,CNS_Q_ASTER,r1) 27218007Ssaidi@eecs.umich.edu SAVE_IPR(astrr,CNS_Q_ASTRR,r1) 27228007Ssaidi@eecs.umich.edu SAVE_IPR(sirr,CNS_Q_SIRR,r1) 27238007Ssaidi@eecs.umich.edu SAVE_IPR(isr,CNS_Q_ISR,r1) 27248007Ssaidi@eecs.umich.edu SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1) 27258007Ssaidi@eecs.umich.edu SAVE_IPR(mcsr,CNS_Q_MCSR,r1) 27268007Ssaidi@eecs.umich.edu SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1) 27278007Ssaidi@eecs.umich.edu 27288007Ssaidi@eecs.umich.edu//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st) 27298007Ssaidi@eecs.umich.edu//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for 27308007Ssaidi@eecs.umich.edu//orig // PVC violation applies only to 27318007Ssaidi@eecs.umich.edupvc$osf35$379: // loads. HW_ST ok here, so ignore 27328007Ssaidi@eecs.umich.edu SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 27338007Ssaidi@eecs.umich.edu 27348007Ssaidi@eecs.umich.edu 27358007Ssaidi@eecs.umich.edu //the following iprs are informational only -- will not be restored 27368007Ssaidi@eecs.umich.edu 27378007Ssaidi@eecs.umich.edu//orig store_reg icperr_stat, ipr=1 27388007Ssaidi@eecs.umich.edu//orig store_reg pmctr, ipr=1 27398007Ssaidi@eecs.umich.edu//orig store_reg intid, ipr=1 27408007Ssaidi@eecs.umich.edu//orig store_reg exc_sum, ipr=1 27418007Ssaidi@eecs.umich.edu//orig store_reg exc_mask, ipr=1 27428007Ssaidi@eecs.umich.edu//orig ldah r14, 0xfff0(r31) 27438007Ssaidi@eecs.umich.edu//orig zap r14, 0xE0, r14 // Get Cbox IPR base 27448007Ssaidi@eecs.umich.edu//orig nop // pad mf dcperr_stat out of shadow of last store 27458007Ssaidi@eecs.umich.edu//orig nop 27468007Ssaidi@eecs.umich.edu//orig nop 27478007Ssaidi@eecs.umich.edu//orig store_reg dcperr_stat, ipr=1 27488007Ssaidi@eecs.umich.edu 27498007Ssaidi@eecs.umich.edu SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) 27508007Ssaidi@eecs.umich.edu SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) 27518007Ssaidi@eecs.umich.edu SAVE_IPR(intId,CNS_Q_INT_ID,r1) 27528007Ssaidi@eecs.umich.edu SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) 27538007Ssaidi@eecs.umich.edu SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) 27548007Ssaidi@eecs.umich.edu ldah r14, 0xFFF0(zero) 27558007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get base address of CBOX IPRs 27568007Ssaidi@eecs.umich.edu NOP // Pad mfpr dcPerr out of shadow of 27578007Ssaidi@eecs.umich.edu NOP // last store 27588007Ssaidi@eecs.umich.edu NOP 27598007Ssaidi@eecs.umich.edu SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) 27608007Ssaidi@eecs.umich.edu 27618007Ssaidi@eecs.umich.edu // read cbox ipr state 27628007Ssaidi@eecs.umich.edu 27638007Ssaidi@eecs.umich.edu//orig mb 27648007Ssaidi@eecs.umich.edu//orig ldqp r2, ev5__sc_ctl(r14) 27658007Ssaidi@eecs.umich.edu//orig ldqp r13, ld_lock(r14) 27668007Ssaidi@eecs.umich.edu//orig ldqp r4, ev5__sc_addr(r14) 27678007Ssaidi@eecs.umich.edu//orig ldqp r5, ev5__ei_addr(r14) 27688007Ssaidi@eecs.umich.edu//orig ldqp r6, ev5__bc_tag_addr(r14) 27698007Ssaidi@eecs.umich.edu//orig ldqp r7, ev5__fill_syn(r14) 27708007Ssaidi@eecs.umich.edu//orig bis r5, r4, r31 27718007Ssaidi@eecs.umich.edu//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them 27728007Ssaidi@eecs.umich.edu//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr 27738007Ssaidi@eecs.umich.edu//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn 27748007Ssaidi@eecs.umich.edu//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked 27758007Ssaidi@eecs.umich.edu//orig mb 27768007Ssaidi@eecs.umich.edu 27778007Ssaidi@eecs.umich.edu#ifndef SIMOS 27788007Ssaidi@eecs.umich.edu mb 27798007Ssaidi@eecs.umich.edu ldq_p r2, scCtl(r14) 27808007Ssaidi@eecs.umich.edu ldq_p r13, ldLock(r14) 27818007Ssaidi@eecs.umich.edu ldq_p r4, scAddr(r14) 27828007Ssaidi@eecs.umich.edu ldq_p r5, eiAddr(r14) 27838007Ssaidi@eecs.umich.edu ldq_p r6, bcTagAddr(r14) 27848007Ssaidi@eecs.umich.edu ldq_p r7, fillSyn(r14) 27858007Ssaidi@eecs.umich.edu bis r5, r4, zero // Make sure all loads complete before 27868007Ssaidi@eecs.umich.edu bis r7, r6, zero // reading registers that unlock them. 27878007Ssaidi@eecs.umich.edu ldq_p r8, scStat(r14) // Unlocks scAddr. 27888007Ssaidi@eecs.umich.edu ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. 27898007Ssaidi@eecs.umich.edu ldq_p zero, eiStat(r14) // Make sure it is really unlocked. 27908007Ssaidi@eecs.umich.edu mb 27918007Ssaidi@eecs.umich.edu#endif 27928007Ssaidi@eecs.umich.edu//orig // save cbox ipr state 27938007Ssaidi@eecs.umich.edu//orig store_reg1 sc_ctl, r2, r1, ipr=1 27948007Ssaidi@eecs.umich.edu//orig store_reg1 ld_lock, r13, r1, ipr=1 27958007Ssaidi@eecs.umich.edu//orig store_reg1 sc_addr, r4, r1, ipr=1 27968007Ssaidi@eecs.umich.edu//orig store_reg1 ei_addr, r5, r1, ipr=1 27978007Ssaidi@eecs.umich.edu//orig store_reg1 bc_tag_addr, r6, r1, ipr=1 27988007Ssaidi@eecs.umich.edu//orig store_reg1 fill_syn, r7, r1, ipr=1 27998007Ssaidi@eecs.umich.edu//orig store_reg1 sc_stat, r8, r1, ipr=1 28008007Ssaidi@eecs.umich.edu//orig store_reg1 ei_stat, r9, r1, ipr=1 28018007Ssaidi@eecs.umich.edu//orig //bc_config? sl_rcv? 28028007Ssaidi@eecs.umich.edu 28038007Ssaidi@eecs.umich.edu SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); 28048007Ssaidi@eecs.umich.edu SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); 28058007Ssaidi@eecs.umich.edu SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); 28068007Ssaidi@eecs.umich.edu SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); 28078007Ssaidi@eecs.umich.edu SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); 28088007Ssaidi@eecs.umich.edu SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); 28098007Ssaidi@eecs.umich.edu SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); 28108007Ssaidi@eecs.umich.edu SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); 28118007Ssaidi@eecs.umich.edu 28128007Ssaidi@eecs.umich.edu// restore impure base //orig 28138007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 28148007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) 28158007Ssaidi@eecs.umich.edu 28168007Ssaidi@eecs.umich.edu// save all floating regs //orig 28178007Ssaidi@eecs.umich.edu mfpr r0, icsr // get icsr //orig 28188007Ssaidi@eecs.umich.edu or r31, 1, r2 // get a one //orig 28198007Ssaidi@eecs.umich.edu//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig 28208007Ssaidi@eecs.umich.edu sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position 28218007Ssaidi@eecs.umich.edu or r2, r0, r0 // set FEN on //orig 28228007Ssaidi@eecs.umich.edu mtpr r0, icsr // write to icsr, enabling FEN //orig 28238007Ssaidi@eecs.umich.edu 28248007Ssaidi@eecs.umich.edu// map the save area virtually 28258007Ssaidi@eecs.umich.edu// orig mtpr r31, dtb_ia // clear the dtb 28268007Ssaidi@eecs.umich.edu// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA 28278007Ssaidi@eecs.umich.edu// orig sll r0, 32, r0 // shift to PFN field 28288007Ssaidi@eecs.umich.edu// orig lda r2, 0xff(r31) // all read enable and write enable bits set 28298007Ssaidi@eecs.umich.edu// orig sll r2, 8, r2 // move to PTE location 28308007Ssaidi@eecs.umich.edu// orig addq r0, r2, r0 // combine with PFN 28318007Ssaidi@eecs.umich.edu// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 28328007Ssaidi@eecs.umich.edu// orig mtpr r1, dtb_tag // write TB tag 28338007Ssaidi@eecs.umich.edu 28348007Ssaidi@eecs.umich.edu mtpr r31, dtbIa // Clear all DTB entries 28358007Ssaidi@eecs.umich.edu srl r1, va_s_off, r0 // Clean off byte-within-page offset 28368007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 28378007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 28388007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 28398007Ssaidi@eecs.umich.edu mtpr r1, dtbTag // Write the PTE and tag into the DTB 28408007Ssaidi@eecs.umich.edu 28418007Ssaidi@eecs.umich.edu 28428007Ssaidi@eecs.umich.edu//orig // map the next page too - in case the impure area crosses a page boundary 28438007Ssaidi@eecs.umich.edu//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page 28448007Ssaidi@eecs.umich.edu//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA 28458007Ssaidi@eecs.umich.edu//orig sll r0, 32, r0 // shift to PFN field 28468007Ssaidi@eecs.umich.edu//orig lda r2, 0xff(r31) // all read enable and write enable bits set 28478007Ssaidi@eecs.umich.edu//orig sll r2, 8, r2 // move to PTE location 28488007Ssaidi@eecs.umich.edu//orig addq r0, r2, r0 // combine with PFN 28498007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 28508007Ssaidi@eecs.umich.edu//orig mtpr r4, dtb_tag // write TB tag 28518007Ssaidi@eecs.umich.edu 28528007Ssaidi@eecs.umich.edu lda r4, (1<<va_s_off)(r1) // Generate address for next page 28538007Ssaidi@eecs.umich.edu srl r4, va_s_off, r0 // Clean off byte-within-page offset 28548007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 28558007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 28568007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 28578007Ssaidi@eecs.umich.edu mtpr r4, dtbTag // Write the PTE and tag into the DTB 28588007Ssaidi@eecs.umich.edu 28598007Ssaidi@eecs.umich.edu sll r31, 0, r31 // stall cycle 1 // orig 28608007Ssaidi@eecs.umich.edu sll r31, 0, r31 // stall cycle 2 // orig 28618007Ssaidi@eecs.umich.edu sll r31, 0, r31 // stall cycle 3 // orig 28628007Ssaidi@eecs.umich.edu nop // orig 28638007Ssaidi@eecs.umich.edu 28648007Ssaidi@eecs.umich.edu//orig // add offset for saving fpr regs 28658007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 28668007Ssaidi@eecs.umich.edu 28678007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 28688007Ssaidi@eecs.umich.edu 28698007Ssaidi@eecs.umich.edu// now save the regs - F0-F31 28708007Ssaidi@eecs.umich.edu 28718007Ssaidi@eecs.umich.edu//orig #define t 0 28728007Ssaidi@eecs.umich.edu//orig .repeat 32 28738007Ssaidi@eecs.umich.edu//orig store_reg \t , fpu=1 28748007Ssaidi@eecs.umich.edu//orig #define t t + 1 28758007Ssaidi@eecs.umich.edu//orig .endr 28768007Ssaidi@eecs.umich.edu 28778007Ssaidi@eecs.umich.edu mf_fpcr f0 // original 28788007Ssaidi@eecs.umich.edu 28798007Ssaidi@eecs.umich.edu SAVE_FPR(f0,CNS_Q_FPR+0x00,r1) 28808007Ssaidi@eecs.umich.edu SAVE_FPR(f1,CNS_Q_FPR+0x08,r1) 28818007Ssaidi@eecs.umich.edu SAVE_FPR(f2,CNS_Q_FPR+0x10,r1) 28828007Ssaidi@eecs.umich.edu SAVE_FPR(f3,CNS_Q_FPR+0x18,r1) 28838007Ssaidi@eecs.umich.edu SAVE_FPR(f4,CNS_Q_FPR+0x20,r1) 28848007Ssaidi@eecs.umich.edu SAVE_FPR(f5,CNS_Q_FPR+0x28,r1) 28858007Ssaidi@eecs.umich.edu SAVE_FPR(f6,CNS_Q_FPR+0x30,r1) 28868007Ssaidi@eecs.umich.edu SAVE_FPR(f7,CNS_Q_FPR+0x38,r1) 28878007Ssaidi@eecs.umich.edu SAVE_FPR(f8,CNS_Q_FPR+0x40,r1) 28888007Ssaidi@eecs.umich.edu SAVE_FPR(f9,CNS_Q_FPR+0x48,r1) 28898007Ssaidi@eecs.umich.edu SAVE_FPR(f10,CNS_Q_FPR+0x50,r1) 28908007Ssaidi@eecs.umich.edu SAVE_FPR(f11,CNS_Q_FPR+0x58,r1) 28918007Ssaidi@eecs.umich.edu SAVE_FPR(f12,CNS_Q_FPR+0x60,r1) 28928007Ssaidi@eecs.umich.edu SAVE_FPR(f13,CNS_Q_FPR+0x68,r1) 28938007Ssaidi@eecs.umich.edu SAVE_FPR(f14,CNS_Q_FPR+0x70,r1) 28948007Ssaidi@eecs.umich.edu SAVE_FPR(f15,CNS_Q_FPR+0x78,r1) 28958007Ssaidi@eecs.umich.edu SAVE_FPR(f16,CNS_Q_FPR+0x80,r1) 28968007Ssaidi@eecs.umich.edu SAVE_FPR(f17,CNS_Q_FPR+0x88,r1) 28978007Ssaidi@eecs.umich.edu SAVE_FPR(f18,CNS_Q_FPR+0x90,r1) 28988007Ssaidi@eecs.umich.edu SAVE_FPR(f19,CNS_Q_FPR+0x98,r1) 28998007Ssaidi@eecs.umich.edu SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1) 29008007Ssaidi@eecs.umich.edu SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1) 29018007Ssaidi@eecs.umich.edu SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1) 29028007Ssaidi@eecs.umich.edu SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1) 29038007Ssaidi@eecs.umich.edu SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1) 29048007Ssaidi@eecs.umich.edu SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1) 29058007Ssaidi@eecs.umich.edu SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1) 29068007Ssaidi@eecs.umich.edu SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1) 29078007Ssaidi@eecs.umich.edu SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1) 29088007Ssaidi@eecs.umich.edu SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1) 29098007Ssaidi@eecs.umich.edu SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1) 29108007Ssaidi@eecs.umich.edu SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1) 29118007Ssaidi@eecs.umich.edu 29128007Ssaidi@eecs.umich.edu//orig //switch impure offset from gpr to ipr--- 29138007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 29148007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 29158007Ssaidi@eecs.umich.edu//orig store_reg1 fpcsr, f0, r1, fpcsr=1 29168007Ssaidi@eecs.umich.edu 29178007Ssaidi@eecs.umich.edu SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb 29188007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore the impure base address 29198007Ssaidi@eecs.umich.edu 29208007Ssaidi@eecs.umich.edu//orig // and back to gpr --- 29218007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 29228007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 29238007Ssaidi@eecs.umich.edu 29248007Ssaidi@eecs.umich.edu//orig lda r0, cns_mchksize(r31) // get size of mchk area 29258007Ssaidi@eecs.umich.edu//orig store_reg1 mchkflag, r0, r1, ipr=1 29268007Ssaidi@eecs.umich.edu//orig mb 29278007Ssaidi@eecs.umich.edu 29288007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again 29298007Ssaidi@eecs.umich.edu // save this using the IPR base (it is closer) not the GRP base as they used...pb 29308007Ssaidi@eecs.umich.edu lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area 29318007Ssaidi@eecs.umich.edu SAVE_SHADOW(r0,CNS_Q_MCHK,r1); 29328007Ssaidi@eecs.umich.edu mb 29338007Ssaidi@eecs.umich.edu 29348007Ssaidi@eecs.umich.edu//orig or r31, 1, r0 // get a one 29358007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag 29368007Ssaidi@eecs.umich.edu//orig mb 29378007Ssaidi@eecs.umich.edu 29388007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) // back to the base 29398007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 29408007Ssaidi@eecs.umich.edu or r31, 1, r0 // get a one 29418007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag 29428007Ssaidi@eecs.umich.edu mb 29438007Ssaidi@eecs.umich.edu 29448007Ssaidi@eecs.umich.edu//orig // restore impure area base 29458007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 29468007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Point to center of CPU segment 29478007Ssaidi@eecs.umich.edu 29488007Ssaidi@eecs.umich.edu mtpr r31, dtb_ia // clear the dtb //orig 29498007Ssaidi@eecs.umich.edu mtpr r31, itb_ia // clear the itb //orig 29508007Ssaidi@eecs.umich.edu 29518007Ssaidi@eecs.umich.edu//orig pvc_jsr savsta, bsr=1, dest=1 29528007Ssaidi@eecs.umich.edu ret r31, (r3) // and back we go 29538007Ssaidi@eecs.umich.edu#endif 29548007Ssaidi@eecs.umich.edu 29558007Ssaidi@eecs.umich.edu 29568007Ssaidi@eecs.umich.edu#if remove_restore_state == 0 29578007Ssaidi@eecs.umich.edu 29588007Ssaidi@eecs.umich.edu 29598007Ssaidi@eecs.umich.edu// .sbttl "PAL_RESTORE_STATE" 29608007Ssaidi@eecs.umich.edu//+ 29618007Ssaidi@eecs.umich.edu// 29628007Ssaidi@eecs.umich.edu// Pal_restore_state 29638007Ssaidi@eecs.umich.edu// 29648007Ssaidi@eecs.umich.edu// 29658007Ssaidi@eecs.umich.edu// register usage: 29668007Ssaidi@eecs.umich.edu// r1 = addr of impure area 29678007Ssaidi@eecs.umich.edu// r3 = return_address 29688007Ssaidi@eecs.umich.edu// all other regs are scratchable, as they are about to 29698007Ssaidi@eecs.umich.edu// be reloaded from ram. 29708007Ssaidi@eecs.umich.edu// 29718007Ssaidi@eecs.umich.edu// Function: 29728007Ssaidi@eecs.umich.edu// All chip state restored, all SRs, FRs, PTs, IPRs 29738007Ssaidi@eecs.umich.edu// *** except R1, R3, PT0, PT4, PT5 *** 29748007Ssaidi@eecs.umich.edu// 29758007Ssaidi@eecs.umich.edu//- 29768007Ssaidi@eecs.umich.edu ALIGN_BLOCK 29778007Ssaidi@eecs.umich.edupal_restore_state: 29788007Ssaidi@eecs.umich.edu 29798007Ssaidi@eecs.umich.edu//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so. 29808007Ssaidi@eecs.umich.edu 29818007Ssaidi@eecs.umich.edu//orig // map the console io area virtually 29828007Ssaidi@eecs.umich.edu//orig mtpr r31, dtb_ia // clear the dtb 29838007Ssaidi@eecs.umich.edu//orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA 29848007Ssaidi@eecs.umich.edu//orig sll r0, 32, r0 // shift to PFN field 29858007Ssaidi@eecs.umich.edu//orig lda r2, 0xff(r31) // all read enable and write enable bits set 29868007Ssaidi@eecs.umich.edu//orig sll r2, 8, r2 // move to PTE location 29878007Ssaidi@eecs.umich.edu//orig addq r0, r2, r0 // combine with PFN 29888007Ssaidi@eecs.umich.edu//orig 29898007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 29908007Ssaidi@eecs.umich.edu//orig mtpr r1, dtb_tag // write TB tag 29918007Ssaidi@eecs.umich.edu//orig 29928007Ssaidi@eecs.umich.edu 29938007Ssaidi@eecs.umich.edu mtpr r31, dtbIa // Clear all DTB entries 29948007Ssaidi@eecs.umich.edu srl r1, va_s_off, r0 // Clean off byte-within-page offset 29958007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 29968007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 29978007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 29988007Ssaidi@eecs.umich.edu mtpr r1, dtbTag // Write the PTE and tag into the DTB 29998007Ssaidi@eecs.umich.edu 30008007Ssaidi@eecs.umich.edu 30018007Ssaidi@eecs.umich.edu//orig // map the next page too, in case impure area crosses page boundary 30028007Ssaidi@eecs.umich.edu//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page 30038007Ssaidi@eecs.umich.edu//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA 30048007Ssaidi@eecs.umich.edu//orig sll r0, 32, r0 // shift to PFN field 30058007Ssaidi@eecs.umich.edu//orig lda r2, 0xff(r31) // all read enable and write enable bits set 30068007Ssaidi@eecs.umich.edu//orig sll r2, 8, r2 // move to PTE location 30078007Ssaidi@eecs.umich.edu//orig addq r0, r2, r0 // combine with PFN 30088007Ssaidi@eecs.umich.edu//orig 30098007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit 30108007Ssaidi@eecs.umich.edu//orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles 30118007Ssaidi@eecs.umich.edu 30128007Ssaidi@eecs.umich.edu lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page 30138007Ssaidi@eecs.umich.edu srl r4, va_s_off, r0 // Clean off byte-within-page offset 30148007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 30158007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 30168007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 30178007Ssaidi@eecs.umich.edu mtpr r4, dtbTag // Write the PTE and tag into the DTB 30188007Ssaidi@eecs.umich.edu 30198007Ssaidi@eecs.umich.edu//orig // save all floating regs 30208007Ssaidi@eecs.umich.edu//orig mfpr r0, icsr // get icsr 30218007Ssaidi@eecs.umich.edu//orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker 30228007Ssaidi@eecs.umich.edu//orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE 30238007Ssaidi@eecs.umich.edu//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot 30248007Ssaidi@eecs.umich.edu//orig or r2, r0, r0 // set FEN on 30258007Ssaidi@eecs.umich.edu//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr. 30268007Ssaidi@eecs.umich.edu 30278007Ssaidi@eecs.umich.edu mfpr r0, icsr // Get current ICSR 30288007Ssaidi@eecs.umich.edu bis zero, 1, r2 // Get a '1' 30298007Ssaidi@eecs.umich.edu or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 30308007Ssaidi@eecs.umich.edu sll r2, icsr_v_fpe, r2 // Shift bits into position 30318007Ssaidi@eecs.umich.edu bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE> 30328007Ssaidi@eecs.umich.edu mtpr r0, icsr // Update the chip 30338007Ssaidi@eecs.umich.edu 30348007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 1 //orig 30358007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 2 //orig 30368007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 3 //orig 30378007Ssaidi@eecs.umich.edu 30388007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 30398007Ssaidi@eecs.umich.edu//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 30408007Ssaidi@eecs.umich.edu//orig mt_fpcr f0 30418007Ssaidi@eecs.umich.edu//orig 30428007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 30438007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access 30448007Ssaidi@eecs.umich.edu//orig 30458007Ssaidi@eecs.umich.edu//orig // restore all floating regs 30468007Ssaidi@eecs.umich.edu//orig#define t 0 30478007Ssaidi@eecs.umich.edu//orig .repeat 32 30488007Ssaidi@eecs.umich.edu//orig restore_reg \t , fpu=1 30498007Ssaidi@eecs.umich.edu//orig#define t t + 1 30508007Ssaidi@eecs.umich.edu//orig .endr 30518007Ssaidi@eecs.umich.edu 30528007Ssaidi@eecs.umich.edu lda r1, 200(r1) // Point to base of IPR area again 30538007Ssaidi@eecs.umich.edu RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb 30548007Ssaidi@eecs.umich.edu mt_fpcr f0 // original 30558007Ssaidi@eecs.umich.edu 30568007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // point to center of CPU segment 30578007Ssaidi@eecs.umich.edu RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) 30588007Ssaidi@eecs.umich.edu RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) 30598007Ssaidi@eecs.umich.edu RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) 30608007Ssaidi@eecs.umich.edu RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) 30618007Ssaidi@eecs.umich.edu RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) 30628007Ssaidi@eecs.umich.edu RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) 30638007Ssaidi@eecs.umich.edu RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) 30648007Ssaidi@eecs.umich.edu RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) 30658007Ssaidi@eecs.umich.edu RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1) 30668007Ssaidi@eecs.umich.edu RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1) 30678007Ssaidi@eecs.umich.edu RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1) 30688007Ssaidi@eecs.umich.edu RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1) 30698007Ssaidi@eecs.umich.edu RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1) 30708007Ssaidi@eecs.umich.edu RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1) 30718007Ssaidi@eecs.umich.edu RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1) 30728007Ssaidi@eecs.umich.edu RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1) 30738007Ssaidi@eecs.umich.edu RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1) 30748007Ssaidi@eecs.umich.edu RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1) 30758007Ssaidi@eecs.umich.edu RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1) 30768007Ssaidi@eecs.umich.edu RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1) 30778007Ssaidi@eecs.umich.edu RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1) 30788007Ssaidi@eecs.umich.edu RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1) 30798007Ssaidi@eecs.umich.edu RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1) 30808007Ssaidi@eecs.umich.edu RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1) 30818007Ssaidi@eecs.umich.edu RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1) 30828007Ssaidi@eecs.umich.edu RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) 30838007Ssaidi@eecs.umich.edu RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) 30848007Ssaidi@eecs.umich.edu RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) 30858007Ssaidi@eecs.umich.edu RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) 30868007Ssaidi@eecs.umich.edu RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) 30878007Ssaidi@eecs.umich.edu RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) 30888007Ssaidi@eecs.umich.edu RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) 30898007Ssaidi@eecs.umich.edu 30908007Ssaidi@eecs.umich.edu//orig // switch impure pointer from gpr to ipr area -- 30918007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 30928007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 30938007Ssaidi@eecs.umich.edu//orig 30948007Ssaidi@eecs.umich.edu//orig // restore all pal regs 30958007Ssaidi@eecs.umich.edu//orig#define t 1 30968007Ssaidi@eecs.umich.edu//orig .repeat 23 30978007Ssaidi@eecs.umich.edu//orig restore_reg \t , pal=1 30988007Ssaidi@eecs.umich.edu//orig#define t t + 1 30998007Ssaidi@eecs.umich.edu//orig .endr 31008007Ssaidi@eecs.umich.edu 31018007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore base address of impure area. 31028007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. 31038007Ssaidi@eecs.umich.edu RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 31048007Ssaidi@eecs.umich.edu RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) 31058007Ssaidi@eecs.umich.edu RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) 31068007Ssaidi@eecs.umich.edu RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) 31078007Ssaidi@eecs.umich.edu RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) 31088007Ssaidi@eecs.umich.edu RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) 31098007Ssaidi@eecs.umich.edu RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) 31108007Ssaidi@eecs.umich.edu RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) 31118007Ssaidi@eecs.umich.edu RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1) 31128007Ssaidi@eecs.umich.edu RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1) 31138007Ssaidi@eecs.umich.edu RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1) 31148007Ssaidi@eecs.umich.edu RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1) 31158007Ssaidi@eecs.umich.edu RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1) 31168007Ssaidi@eecs.umich.edu RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1) 31178007Ssaidi@eecs.umich.edu RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1) 31188007Ssaidi@eecs.umich.edu RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1) 31198007Ssaidi@eecs.umich.edu RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1) 31208007Ssaidi@eecs.umich.edu RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1) 31218007Ssaidi@eecs.umich.edu RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1) 31228007Ssaidi@eecs.umich.edu RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1) 31238007Ssaidi@eecs.umich.edu RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1) 31248007Ssaidi@eecs.umich.edu RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1) 31258007Ssaidi@eecs.umich.edu RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1) 31268007Ssaidi@eecs.umich.edu RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1) 31278007Ssaidi@eecs.umich.edu 31288007Ssaidi@eecs.umich.edu 31298007Ssaidi@eecs.umich.edu//orig restore_reg exc_addr, ipr=1 // restore ipr 31308007Ssaidi@eecs.umich.edu//orig restore_reg pal_base, ipr=1 // restore ipr 31318007Ssaidi@eecs.umich.edu//orig restore_reg ipl, ipr=1 // restore ipr 31328007Ssaidi@eecs.umich.edu//orig restore_reg ps, ipr=1 // restore ipr 31338007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_cm // set current mode in mbox too 31348007Ssaidi@eecs.umich.edu//orig restore_reg itb_asn, ipr=1 31358007Ssaidi@eecs.umich.edu//orig srl r0, itb_asn_v_asn, r0 31368007Ssaidi@eecs.umich.edu//orig sll r0, dtb_asn_v_asn, r0 31378007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_asn // set ASN in Mbox too 31388007Ssaidi@eecs.umich.edu//orig restore_reg ivptbr, ipr=1 31398007Ssaidi@eecs.umich.edu//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr 31408007Ssaidi@eecs.umich.edu//orig restore_reg mcsr, ipr=1 31418007Ssaidi@eecs.umich.edu//orig restore_reg aster, ipr=1 31428007Ssaidi@eecs.umich.edu//orig restore_reg astrr, ipr=1 31438007Ssaidi@eecs.umich.edu//orig restore_reg sirr, ipr=1 31448007Ssaidi@eecs.umich.edu//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles 31458007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // (may issue with mt maf_mode) 31468007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 1 31478007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 2 31488007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 3 31498007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // (may issue with following ld) 31508007Ssaidi@eecs.umich.edu 31518007Ssaidi@eecs.umich.edu // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag) 31528007Ssaidi@eecs.umich.edu RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 31538007Ssaidi@eecs.umich.edu RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1) 31548007Ssaidi@eecs.umich.edu RESTORE_IPR(ipl,CNS_Q_IPL,r1) 31558007Ssaidi@eecs.umich.edu RESTORE_IPR(ips,CNS_Q_IPS,r1) 31568007Ssaidi@eecs.umich.edu mtpr r0, dtbCm // Set Mbox current mode too. 31578007Ssaidi@eecs.umich.edu RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) 31588007Ssaidi@eecs.umich.edu srl r0, 4, r0 31598007Ssaidi@eecs.umich.edu sll r0, 57, r0 31608007Ssaidi@eecs.umich.edu mtpr r0, dtbAsn // Set Mbox ASN too 31618007Ssaidi@eecs.umich.edu RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1) 31628007Ssaidi@eecs.umich.edu mtpr r0, mVptBr // Set Mbox VptBr too 31638007Ssaidi@eecs.umich.edu RESTORE_IPR(mcsr,CNS_Q_MCSR,r1) 31648007Ssaidi@eecs.umich.edu RESTORE_IPR(aster,CNS_Q_ASTER,r1) 31658007Ssaidi@eecs.umich.edu RESTORE_IPR(astrr,CNS_Q_ASTRR,r1) 31668007Ssaidi@eecs.umich.edu RESTORE_IPR(sirr,CNS_Q_SIRR,r1) 31678007Ssaidi@eecs.umich.edu RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1) 31688007Ssaidi@eecs.umich.edu STALL 31698007Ssaidi@eecs.umich.edu STALL 31708007Ssaidi@eecs.umich.edu STALL 31718007Ssaidi@eecs.umich.edu STALL 31728007Ssaidi@eecs.umich.edu STALL 31738007Ssaidi@eecs.umich.edu 31748007Ssaidi@eecs.umich.edu 31758007Ssaidi@eecs.umich.edu // restore all integer shadow regs 31768007Ssaidi@eecs.umich.edu//orig#define t 8 31778007Ssaidi@eecs.umich.edu//orig .repeat 7 31788007Ssaidi@eecs.umich.edu//orig restore_reg \t, shadow=1 31798007Ssaidi@eecs.umich.edu//orig#define t t + 1 31808007Ssaidi@eecs.umich.edu//orig .endr 31818007Ssaidi@eecs.umich.edu//orig restore_reg 25, shadow=1 31828007Ssaidi@eecs.umich.edu//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles 31838007Ssaidi@eecs.umich.edu 31848007Ssaidi@eecs.umich.edu RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 31858007Ssaidi@eecs.umich.edu RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 31868007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 31878007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 31888007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 31898007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 31908007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 31918007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 31928007Ssaidi@eecs.umich.edu RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) 31938007Ssaidi@eecs.umich.edu 31948007Ssaidi@eecs.umich.edu // 31958007Ssaidi@eecs.umich.edu // Get out of shadow mode 31968007Ssaidi@eecs.umich.edu // 31978007Ssaidi@eecs.umich.edu 31988007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig 31998007Ssaidi@eecs.umich.edu mfpr r31, pt0 // "" //orig 32008007Ssaidi@eecs.umich.edu mfpr r0, icsr // Get icsr //orig 32018007Ssaidi@eecs.umich.edu//orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location 32028007Ssaidi@eecs.umich.edu ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig 32038007Ssaidi@eecs.umich.edu bic r0, r2, r2 // ICSR with SDE clear //orig 32048007Ssaidi@eecs.umich.edu mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig 32058007Ssaidi@eecs.umich.edu 32068007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 1 //orig 32078007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 2 //orig 32088007Ssaidi@eecs.umich.edu mfpr r31, pt0 // SDE bubble cycle 3 //orig 32098007Ssaidi@eecs.umich.edu nop //orig 32108007Ssaidi@eecs.umich.edu 32118007Ssaidi@eecs.umich.edu//orig // switch impure pointer from ipr to gpr area -- 32128007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 32138007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 32148007Ssaidi@eecs.umich.edu//orig // restore all integer regs 32158007Ssaidi@eecs.umich.edu//orig#define t 4 32168007Ssaidi@eecs.umich.edu//orig .repeat 28 32178007Ssaidi@eecs.umich.edu//orig restore_reg \t 32188007Ssaidi@eecs.umich.edu//orig#define t t + 1 32198007Ssaidi@eecs.umich.edu//orig .endr 32208007Ssaidi@eecs.umich.edu 32218007Ssaidi@eecs.umich.edu// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... 32228007Ssaidi@eecs.umich.edu 32238007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area 32248007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 32258007Ssaidi@eecs.umich.edu 32268007Ssaidi@eecs.umich.edu RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) 32278007Ssaidi@eecs.umich.edu RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) 32288007Ssaidi@eecs.umich.edu RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) 32298007Ssaidi@eecs.umich.edu RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) 32308007Ssaidi@eecs.umich.edu RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) 32318007Ssaidi@eecs.umich.edu RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) 32328007Ssaidi@eecs.umich.edu RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) 32338007Ssaidi@eecs.umich.edu RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) 32348007Ssaidi@eecs.umich.edu RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1) 32358007Ssaidi@eecs.umich.edu RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1) 32368007Ssaidi@eecs.umich.edu RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1) 32378007Ssaidi@eecs.umich.edu RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1) 32388007Ssaidi@eecs.umich.edu RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1) 32398007Ssaidi@eecs.umich.edu RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1) 32408007Ssaidi@eecs.umich.edu RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1) 32418007Ssaidi@eecs.umich.edu RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1) 32428007Ssaidi@eecs.umich.edu RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1) 32438007Ssaidi@eecs.umich.edu RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1) 32448007Ssaidi@eecs.umich.edu RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1) 32458007Ssaidi@eecs.umich.edu RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1) 32468007Ssaidi@eecs.umich.edu RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1) 32478007Ssaidi@eecs.umich.edu RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1) 32488007Ssaidi@eecs.umich.edu RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1) 32498007Ssaidi@eecs.umich.edu RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1) 32508007Ssaidi@eecs.umich.edu RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1) 32518007Ssaidi@eecs.umich.edu RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1) 32528007Ssaidi@eecs.umich.edu RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1) 32538007Ssaidi@eecs.umich.edu RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1) 32548007Ssaidi@eecs.umich.edu 32558007Ssaidi@eecs.umich.edu//orig // switch impure pointer from gpr to ipr area -- 32568007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 32578007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 32588007Ssaidi@eecs.umich.edu//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei 32598007Ssaidi@eecs.umich.edu 32608007Ssaidi@eecs.umich.edu lda t0, -0x200(t0) // Restore base address of impure area. 32618007Ssaidi@eecs.umich.edu lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again. 32628007Ssaidi@eecs.umich.edu RESTORE_IPR(icsr,CNS_Q_ICSR,r1) 32638007Ssaidi@eecs.umich.edu 32648007Ssaidi@eecs.umich.edu//orig // and back again -- 32658007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 32668007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 32678007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag 32688007Ssaidi@eecs.umich.edu//orig mb 32698007Ssaidi@eecs.umich.edu 32708007Ssaidi@eecs.umich.edu lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again, 32718007Ssaidi@eecs.umich.edu lda t0, 0x200(t0) // and back to center of CPU segment 32728007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag 32738007Ssaidi@eecs.umich.edu mb 32748007Ssaidi@eecs.umich.edu 32758007Ssaidi@eecs.umich.edu//orig // and back we go 32768007Ssaidi@eecs.umich.edu//orig// restore_reg 3 32778007Ssaidi@eecs.umich.edu//orig restore_reg 2 32788007Ssaidi@eecs.umich.edu//orig// restore_reg 1 32798007Ssaidi@eecs.umich.edu//orig restore_reg 0 32808007Ssaidi@eecs.umich.edu//orig // restore impure area base 32818007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 32828007Ssaidi@eecs.umich.edu 32838007Ssaidi@eecs.umich.edu RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) 32848007Ssaidi@eecs.umich.edu RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) 32858007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore impure base address 32868007Ssaidi@eecs.umich.edu 32878007Ssaidi@eecs.umich.edu mfpr r31, pt0 // stall for ldqp above //orig 32888007Ssaidi@eecs.umich.edu 32898007Ssaidi@eecs.umich.edu mtpr r31, dtb_ia // clear the tb //orig 32908007Ssaidi@eecs.umich.edu mtpr r31, itb_ia // clear the itb //orig 32918007Ssaidi@eecs.umich.edu 32928007Ssaidi@eecs.umich.edu//orig pvc_jsr rststa, bsr=1, dest=1 32938007Ssaidi@eecs.umich.edu ret r31, (r3) // back we go //orig 32948007Ssaidi@eecs.umich.edu#endif 32958007Ssaidi@eecs.umich.edu 32968007Ssaidi@eecs.umich.edu 32978007Ssaidi@eecs.umich.edu//+ 32988007Ssaidi@eecs.umich.edu// pal_pal_bug_check -- code has found a bugcheck situation. 32998007Ssaidi@eecs.umich.edu// Set things up and join common machine check flow. 33008007Ssaidi@eecs.umich.edu// 33018007Ssaidi@eecs.umich.edu// Input: 33028007Ssaidi@eecs.umich.edu// r14 - exc_addr 33038007Ssaidi@eecs.umich.edu// 33048007Ssaidi@eecs.umich.edu// On exit: 33058007Ssaidi@eecs.umich.edu// pt0 - saved r0 33068007Ssaidi@eecs.umich.edu// pt1 - saved r1 33078007Ssaidi@eecs.umich.edu// pt4 - saved r4 33088007Ssaidi@eecs.umich.edu// pt5 - saved r5 33098007Ssaidi@eecs.umich.edu// pt6 - saved r6 33108007Ssaidi@eecs.umich.edu// pt10 - saved exc_addr 33118007Ssaidi@eecs.umich.edu// pt_misc<47:32> - mchk code 33128007Ssaidi@eecs.umich.edu// pt_misc<31:16> - scb vector 33138007Ssaidi@eecs.umich.edu// r14 - base of Cbox IPRs in IO space 33148007Ssaidi@eecs.umich.edu// MCES<mchk> is set 33158007Ssaidi@eecs.umich.edu//- 33168007Ssaidi@eecs.umich.edu 33178007Ssaidi@eecs.umich.edu ALIGN_BLOCK 33188007Ssaidi@eecs.umich.edu .globl pal_pal_bug_check_from_int 33198007Ssaidi@eecs.umich.edupal_pal_bug_check_from_int: 33208007Ssaidi@eecs.umich.edu DEBUGSTORE(0x79) 33218007Ssaidi@eecs.umich.edu//simos DEBUG_EXC_ADDR() 33228007Ssaidi@eecs.umich.edu DEBUGSTORE(0x20) 33238007Ssaidi@eecs.umich.edu//simos bsr r25, put_hex 33248007Ssaidi@eecs.umich.edu lda r25, mchk_c_bugcheck(r31) 33258007Ssaidi@eecs.umich.edu addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed 33268007Ssaidi@eecs.umich.edu br r31, pal_pal_mchk 33278007Ssaidi@eecs.umich.edu nop 33288007Ssaidi@eecs.umich.edu 33298007Ssaidi@eecs.umich.edupal_pal_bug_check: 33308007Ssaidi@eecs.umich.edu lda r25, mchk_c_bugcheck(r31) 33318007Ssaidi@eecs.umich.edu 33328007Ssaidi@eecs.umich.edupal_pal_mchk: 33338007Ssaidi@eecs.umich.edu sll r25, 32, r25 // Move mchk code to position 33348007Ssaidi@eecs.umich.edu 33358007Ssaidi@eecs.umich.edu mtpr r14, pt10 // Stash exc_addr 33368007Ssaidi@eecs.umich.edu mtpr r14, exc_addr 33378007Ssaidi@eecs.umich.edu 33388007Ssaidi@eecs.umich.edu mfpr r12, pt_misc // Get MCES and scratch 33398007Ssaidi@eecs.umich.edu zap r12, 0x3c, r12 33408007Ssaidi@eecs.umich.edu 33418007Ssaidi@eecs.umich.edu or r12, r25, r12 // Combine mchk code 33428007Ssaidi@eecs.umich.edu lda r25, scb_v_procmchk(r31) // Get SCB vector 33438007Ssaidi@eecs.umich.edu 33448007Ssaidi@eecs.umich.edu sll r25, 16, r25 // Move SCBv to position 33458007Ssaidi@eecs.umich.edu or r12, r25, r25 // Combine SCBv 33468007Ssaidi@eecs.umich.edu 33478007Ssaidi@eecs.umich.edu mtpr r0, pt0 // Stash for scratch 33488007Ssaidi@eecs.umich.edu bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit 33498007Ssaidi@eecs.umich.edu 33508007Ssaidi@eecs.umich.edu mtpr r25, pt_misc // Save mchk code!scbv!whami!mces 33518007Ssaidi@eecs.umich.edu ldah r14, 0xfff0(r31) 33528007Ssaidi@eecs.umich.edu 33538007Ssaidi@eecs.umich.edu mtpr r1, pt1 // Stash for scratch 33548007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 33558007Ssaidi@eecs.umich.edu 33568007Ssaidi@eecs.umich.edu mtpr r4, pt4 33578007Ssaidi@eecs.umich.edu mtpr r5, pt5 33588007Ssaidi@eecs.umich.edu 33598007Ssaidi@eecs.umich.edu mtpr r6, pt6 33608007Ssaidi@eecs.umich.edu blbs r12, sys_double_machine_check // MCHK halt if double machine check 33618007Ssaidi@eecs.umich.edu 33628007Ssaidi@eecs.umich.edu br r31, sys_mchk_collect_iprs // Join common machine check flow 33638007Ssaidi@eecs.umich.edu 33648007Ssaidi@eecs.umich.edu// align_to_call_pal_section // Align to address of first call_pal entry point - 2000 33658007Ssaidi@eecs.umich.edu 33668007Ssaidi@eecs.umich.edu// .sbttl "HALT - PALcode for HALT instruction" 33678007Ssaidi@eecs.umich.edu 33688007Ssaidi@eecs.umich.edu//+ 33698007Ssaidi@eecs.umich.edu// 33708007Ssaidi@eecs.umich.edu// Entry: 33718007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 33728007Ssaidi@eecs.umich.edu// 33738007Ssaidi@eecs.umich.edu// Function: 33748007Ssaidi@eecs.umich.edu// GO to console code 33758007Ssaidi@eecs.umich.edu// 33768007Ssaidi@eecs.umich.edu//- 33778007Ssaidi@eecs.umich.edu 33788007Ssaidi@eecs.umich.edu .text 1 33798007Ssaidi@eecs.umich.edu// . = 0x2000 33808007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_HALT_ENTRY) 33818007Ssaidi@eecs.umich.educall_pal_halt: 33828007Ssaidi@eecs.umich.edu#if rax_mode == 0 33838007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad exc_addr read 33848007Ssaidi@eecs.umich.edu mfpr r31, pt0 33858007Ssaidi@eecs.umich.edu 33868007Ssaidi@eecs.umich.edu mfpr r12, exc_addr // get PC 33878007Ssaidi@eecs.umich.edu subq r12, 4, r12 // Point to the HALT 33888007Ssaidi@eecs.umich.edu 33898007Ssaidi@eecs.umich.edu mtpr r12, exc_addr 33908007Ssaidi@eecs.umich.edu mtpr r0, pt0 33918007Ssaidi@eecs.umich.edu 33928007Ssaidi@eecs.umich.edu//orig pvc_jsr updpcb, bsr=1 33938007Ssaidi@eecs.umich.edu bsr r0, pal_update_pcb // update the pcb 33948007Ssaidi@eecs.umich.edu lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt 33958007Ssaidi@eecs.umich.edu br r31, sys_enter_console // enter the console 33968007Ssaidi@eecs.umich.edu 33978007Ssaidi@eecs.umich.edu#else // RAX mode 33988007Ssaidi@eecs.umich.edu mb 33998007Ssaidi@eecs.umich.edu mb 34008007Ssaidi@eecs.umich.edu mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles. 34018007Ssaidi@eecs.umich.edu mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles. 34028007Ssaidi@eecs.umich.edu mtpr r8, exc_addr // no HW_REI for 1 cycle. 34038007Ssaidi@eecs.umich.edu blbc r9, not_begin_case 34048007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles. 34058007Ssaidi@eecs.umich.edu mtpr r31, ev5__itb_ia // clear ITB. 34068007Ssaidi@eecs.umich.edu 34078007Ssaidi@eecs.umich.edunot_begin_case: 34088007Ssaidi@eecs.umich.edu nop 34098007Ssaidi@eecs.umich.edu nop 34108007Ssaidi@eecs.umich.edu 34118007Ssaidi@eecs.umich.edu nop 34128007Ssaidi@eecs.umich.edu nop // pad mt itb_asn ->hw_rei_stall 34138007Ssaidi@eecs.umich.edu 34148007Ssaidi@eecs.umich.edu hw_rei_stall 34158007Ssaidi@eecs.umich.edu#endif 34168007Ssaidi@eecs.umich.edu 34178007Ssaidi@eecs.umich.edu// .sbttl "CFLUSH- PALcode for CFLUSH instruction" 34188007Ssaidi@eecs.umich.edu 34198007Ssaidi@eecs.umich.edu//+ 34208007Ssaidi@eecs.umich.edu// 34218007Ssaidi@eecs.umich.edu// Entry: 34228007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 34238007Ssaidi@eecs.umich.edu// 34248007Ssaidi@eecs.umich.edu// R16 - contains the PFN of the page to be flushed 34258007Ssaidi@eecs.umich.edu// 34268007Ssaidi@eecs.umich.edu// Function: 34278007Ssaidi@eecs.umich.edu// Flush all Dstream caches of 1 entire page 34288007Ssaidi@eecs.umich.edu// The CFLUSH routine is in the system specific module. 34298007Ssaidi@eecs.umich.edu// 34308007Ssaidi@eecs.umich.edu//- 34318007Ssaidi@eecs.umich.edu 34328007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) 34338007Ssaidi@eecs.umich.eduCall_Pal_Cflush: 34348007Ssaidi@eecs.umich.edu br r31, sys_cflush 34358007Ssaidi@eecs.umich.edu 34368007Ssaidi@eecs.umich.edu// .sbttl "DRAINA - PALcode for DRAINA instruction" 34378007Ssaidi@eecs.umich.edu//+ 34388007Ssaidi@eecs.umich.edu// 34398007Ssaidi@eecs.umich.edu// Entry: 34408007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 34418007Ssaidi@eecs.umich.edu// Implicit TRAPB performed by hardware. 34428007Ssaidi@eecs.umich.edu// 34438007Ssaidi@eecs.umich.edu// Function: 34448007Ssaidi@eecs.umich.edu// Stall instruction issue until all prior instructions are guaranteed to 34458007Ssaidi@eecs.umich.edu// complete without incurring aborts. For the EV5 implementation, this 34468007Ssaidi@eecs.umich.edu// means waiting until all pending DREADS are returned. 34478007Ssaidi@eecs.umich.edu// 34488007Ssaidi@eecs.umich.edu//- 34498007Ssaidi@eecs.umich.edu 34508007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_DRAINA_ENTRY) 34518007Ssaidi@eecs.umich.eduCall_Pal_Draina: 34528007Ssaidi@eecs.umich.edu ldah r14, 0x100(r31) // Init counter. Value? 34538007Ssaidi@eecs.umich.edu nop 34548007Ssaidi@eecs.umich.edu 34558007Ssaidi@eecs.umich.eduDRAINA_LOOP: 34568007Ssaidi@eecs.umich.edu subq r14, 1, r14 // Decrement counter 34578007Ssaidi@eecs.umich.edu mfpr r13, ev5__maf_mode // Fetch status bit 34588007Ssaidi@eecs.umich.edu 34598007Ssaidi@eecs.umich.edu srl r13, maf_mode_v_dread_pending, r13 34608007Ssaidi@eecs.umich.edu ble r14, DRAINA_LOOP_TOO_LONG 34618007Ssaidi@eecs.umich.edu 34628007Ssaidi@eecs.umich.edu nop 34638007Ssaidi@eecs.umich.edu blbs r13, DRAINA_LOOP // Wait until all DREADS clear 34648007Ssaidi@eecs.umich.edu 34658007Ssaidi@eecs.umich.edu hw_rei 34668007Ssaidi@eecs.umich.edu 34678007Ssaidi@eecs.umich.eduDRAINA_LOOP_TOO_LONG: 34688007Ssaidi@eecs.umich.edu br r31, call_pal_halt 34698007Ssaidi@eecs.umich.edu 34708007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 34718007Ssaidi@eecs.umich.edu 34728007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0003) 34738007Ssaidi@eecs.umich.eduCallPal_OpcDec03: 34748007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34758007Ssaidi@eecs.umich.edu 34768007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0004) 34778007Ssaidi@eecs.umich.eduCallPal_OpcDec04: 34788007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34798007Ssaidi@eecs.umich.edu 34808007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0005) 34818007Ssaidi@eecs.umich.eduCallPal_OpcDec05: 34828007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34838007Ssaidi@eecs.umich.edu 34848007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0006) 34858007Ssaidi@eecs.umich.eduCallPal_OpcDec06: 34868007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34878007Ssaidi@eecs.umich.edu 34888007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0007) 34898007Ssaidi@eecs.umich.eduCallPal_OpcDec07: 34908007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34918007Ssaidi@eecs.umich.edu 34928007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0008) 34938007Ssaidi@eecs.umich.eduCallPal_OpcDec08: 34948007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34958007Ssaidi@eecs.umich.edu 34968007Ssaidi@eecs.umich.edu// .sbttl "CSERVE- PALcode for CSERVE instruction" 34978007Ssaidi@eecs.umich.edu//+ 34988007Ssaidi@eecs.umich.edu// 34998007Ssaidi@eecs.umich.edu// Entry: 35008007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35018007Ssaidi@eecs.umich.edu// 35028007Ssaidi@eecs.umich.edu// Function: 35038007Ssaidi@eecs.umich.edu// Various functions for private use of console software 35048007Ssaidi@eecs.umich.edu// 35058007Ssaidi@eecs.umich.edu// option selector in r0 35068007Ssaidi@eecs.umich.edu// arguments in r16.... 35078007Ssaidi@eecs.umich.edu// The CSERVE routine is in the system specific module. 35088007Ssaidi@eecs.umich.edu// 35098007Ssaidi@eecs.umich.edu//- 35108007Ssaidi@eecs.umich.edu 35118007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_CSERVE_ENTRY) 35128007Ssaidi@eecs.umich.eduCall_Pal_Cserve: 35138007Ssaidi@eecs.umich.edu br r31, sys_cserve 35148007Ssaidi@eecs.umich.edu 35158007Ssaidi@eecs.umich.edu// .sbttl "swppal - PALcode for swppal instruction" 35168007Ssaidi@eecs.umich.edu 35178007Ssaidi@eecs.umich.edu//+ 35188007Ssaidi@eecs.umich.edu// 35198007Ssaidi@eecs.umich.edu// Entry: 35208007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35218007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35228007Ssaidi@eecs.umich.edu// R16 contains the new PAL identifier 35238007Ssaidi@eecs.umich.edu// R17:R21 contain implementation-specific entry parameters 35248007Ssaidi@eecs.umich.edu// 35258007Ssaidi@eecs.umich.edu// R0 receives status: 35268007Ssaidi@eecs.umich.edu// 0 success (PAL was switched) 35278007Ssaidi@eecs.umich.edu// 1 unknown PAL variant 35288007Ssaidi@eecs.umich.edu// 2 known PAL variant, but PAL not loaded 35298007Ssaidi@eecs.umich.edu// 35308007Ssaidi@eecs.umich.edu// 35318007Ssaidi@eecs.umich.edu// Function: 35328007Ssaidi@eecs.umich.edu// Swap control to another PAL. 35338007Ssaidi@eecs.umich.edu//- 35348007Ssaidi@eecs.umich.edu 35358007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) 35368007Ssaidi@eecs.umich.eduCall_Pal_Swppal: 35378007Ssaidi@eecs.umich.edu cmpule r16, 255, r0 // see if a kibble was passed 35388007Ssaidi@eecs.umich.edu cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) 35398007Ssaidi@eecs.umich.edu 35408007Ssaidi@eecs.umich.edu or r16, r31, r3 // set r3 incase this is a address 35418007Ssaidi@eecs.umich.edu blbc r0, swppal_cont // nope, try it as an address 35428007Ssaidi@eecs.umich.edu 35438007Ssaidi@eecs.umich.edu cmpeq r16, 2, r0 // is it our friend OSF? 35448007Ssaidi@eecs.umich.edu blbc r0, swppal_fail // nope, don't know this fellow 35458007Ssaidi@eecs.umich.edu 35468007Ssaidi@eecs.umich.edu br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF 35478007Ssaidi@eecs.umich.edu 35488007Ssaidi@eecs.umich.edu// .global osfpal_hw_entry_reset 35498007Ssaidi@eecs.umich.edu// .weak osfpal_hw_entry_reset 35508007Ssaidi@eecs.umich.edu// .long <osfpal_hw_entry_reset-pal_start> 35518007Ssaidi@eecs.umich.edu//orig halt // don't know how to get the address here - kludge ok, load pal at 0 35528007Ssaidi@eecs.umich.edu .long 0 // ?? hack upon hack...pb 35538007Ssaidi@eecs.umich.edu 35548007Ssaidi@eecs.umich.eduCALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr 35558007Ssaidi@eecs.umich.edu// ble r3, swppal_fail ; if OSF not linked in say not loaded. 35568007Ssaidi@eecs.umich.edu mfpr r2, pal_base // fetch pal base 35578007Ssaidi@eecs.umich.edu 35588007Ssaidi@eecs.umich.edu addq r2, r3, r3 // add pal base 35598007Ssaidi@eecs.umich.edu lda r2, 0x3FFF(r31) // get pal base checker mask 35608007Ssaidi@eecs.umich.edu 35618007Ssaidi@eecs.umich.edu and r3, r2, r2 // any funky bits set? 35628007Ssaidi@eecs.umich.edu cmpeq r2, 0, r0 // 35638007Ssaidi@eecs.umich.edu 35648007Ssaidi@eecs.umich.edu blbc r0, swppal_fail // return unknown if bad bit set. 35658007Ssaidi@eecs.umich.edu br r31, swppal_cont 35668007Ssaidi@eecs.umich.edu 35678007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 35688007Ssaidi@eecs.umich.edu 35698007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000B) 35708007Ssaidi@eecs.umich.eduCallPal_OpcDec0B: 35718007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35728007Ssaidi@eecs.umich.edu 35738007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000C) 35748007Ssaidi@eecs.umich.eduCallPal_OpcDec0C: 35758007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35768007Ssaidi@eecs.umich.edu 35778007Ssaidi@eecs.umich.edu// .sbttl "wripir- PALcode for wripir instruction" 35788007Ssaidi@eecs.umich.edu//+ 35798007Ssaidi@eecs.umich.edu// 35808007Ssaidi@eecs.umich.edu// Entry: 35818007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35828007Ssaidi@eecs.umich.edu// r16 = processor number to interrupt 35838007Ssaidi@eecs.umich.edu// 35848007Ssaidi@eecs.umich.edu// Function: 35858007Ssaidi@eecs.umich.edu// IPIR <- R16 35868007Ssaidi@eecs.umich.edu// Handled in system-specific code 35878007Ssaidi@eecs.umich.edu// 35888007Ssaidi@eecs.umich.edu// Exit: 35898007Ssaidi@eecs.umich.edu// interprocessor interrupt is recorded on the target processor 35908007Ssaidi@eecs.umich.edu// and is initiated when the proper enabling conditions are present. 35918007Ssaidi@eecs.umich.edu//- 35928007Ssaidi@eecs.umich.edu 35938007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) 35948007Ssaidi@eecs.umich.eduCall_Pal_Wrpir: 35958007Ssaidi@eecs.umich.edu br r31, sys_wripir 35968007Ssaidi@eecs.umich.edu 35978007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 35988007Ssaidi@eecs.umich.edu 35998007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000E) 36008007Ssaidi@eecs.umich.eduCallPal_OpcDec0E: 36018007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36028007Ssaidi@eecs.umich.edu 36038007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000F) 36048007Ssaidi@eecs.umich.eduCallPal_OpcDec0F: 36058007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36068007Ssaidi@eecs.umich.edu 36078007Ssaidi@eecs.umich.edu// .sbttl "rdmces- PALcode for rdmces instruction" 36088007Ssaidi@eecs.umich.edu 36098007Ssaidi@eecs.umich.edu//+ 36108007Ssaidi@eecs.umich.edu// 36118007Ssaidi@eecs.umich.edu// Entry: 36128007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 36138007Ssaidi@eecs.umich.edu// 36148007Ssaidi@eecs.umich.edu// Function: 36158007Ssaidi@eecs.umich.edu// R0 <- ZEXT(MCES) 36168007Ssaidi@eecs.umich.edu//- 36178007Ssaidi@eecs.umich.edu 36188007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDMCES_ENTRY) 36198007Ssaidi@eecs.umich.eduCall_Pal_Rdmces: 36208007Ssaidi@eecs.umich.edu mfpr r0, pt_mces // Read from PALtemp 36218007Ssaidi@eecs.umich.edu and r0, mces_m_all, r0 // Clear other bits 36228007Ssaidi@eecs.umich.edu 36238007Ssaidi@eecs.umich.edu hw_rei 36248007Ssaidi@eecs.umich.edu 36258007Ssaidi@eecs.umich.edu// .sbttl "wrmces- PALcode for wrmces instruction" 36268007Ssaidi@eecs.umich.edu 36278007Ssaidi@eecs.umich.edu//+ 36288007Ssaidi@eecs.umich.edu// 36298007Ssaidi@eecs.umich.edu// Entry: 36308007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 36318007Ssaidi@eecs.umich.edu// 36328007Ssaidi@eecs.umich.edu// Function: 36338007Ssaidi@eecs.umich.edu// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) 36348007Ssaidi@eecs.umich.edu// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) 36358007Ssaidi@eecs.umich.edu// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) 36368007Ssaidi@eecs.umich.edu// MCES<3> <- R16<3> (DPC) 36378007Ssaidi@eecs.umich.edu// MCES<4> <- R16<4> (DSC) 36388007Ssaidi@eecs.umich.edu// 36398007Ssaidi@eecs.umich.edu//- 36408007Ssaidi@eecs.umich.edu 36418007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRMCES_ENTRY) 36428007Ssaidi@eecs.umich.eduCall_Pal_Wrmces: 36438007Ssaidi@eecs.umich.edu and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE 36448007Ssaidi@eecs.umich.edu mfpr r14, pt_mces // Get current value 36458007Ssaidi@eecs.umich.edu 36468007Ssaidi@eecs.umich.edu ornot r31, r13, r13 // Flip all the bits 36478007Ssaidi@eecs.umich.edu and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17 36488007Ssaidi@eecs.umich.edu 36498007Ssaidi@eecs.umich.edu and r14, r13, r1 // Update MCHK, SCE, PCE 36508007Ssaidi@eecs.umich.edu bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC 36518007Ssaidi@eecs.umich.edu 36528007Ssaidi@eecs.umich.edu or r1, r17, r1 // Update DPC and DSC 36538007Ssaidi@eecs.umich.edu mtpr r1, pt_mces // Write MCES back 36548007Ssaidi@eecs.umich.edu 36558007Ssaidi@eecs.umich.edu#if rawhide_system == 0 36568007Ssaidi@eecs.umich.edu nop // Pad to fix PT write->read restriction 36578007Ssaidi@eecs.umich.edu#else 36588007Ssaidi@eecs.umich.edu blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock 36598007Ssaidi@eecs.umich.edu#endif 36608007Ssaidi@eecs.umich.edu 36618007Ssaidi@eecs.umich.edu nop 36628007Ssaidi@eecs.umich.edu hw_rei 36638007Ssaidi@eecs.umich.edu 36648007Ssaidi@eecs.umich.edu 36658007Ssaidi@eecs.umich.edu 36668007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 36678007Ssaidi@eecs.umich.edu 36688007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0012) 36698007Ssaidi@eecs.umich.eduCallPal_OpcDec12: 36708007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36718007Ssaidi@eecs.umich.edu 36728007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0013) 36738007Ssaidi@eecs.umich.eduCallPal_OpcDec13: 36748007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36758007Ssaidi@eecs.umich.edu 36768007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0014) 36778007Ssaidi@eecs.umich.eduCallPal_OpcDec14: 36788007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36798007Ssaidi@eecs.umich.edu 36808007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0015) 36818007Ssaidi@eecs.umich.eduCallPal_OpcDec15: 36828007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36838007Ssaidi@eecs.umich.edu 36848007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0016) 36858007Ssaidi@eecs.umich.eduCallPal_OpcDec16: 36868007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36878007Ssaidi@eecs.umich.edu 36888007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0017) 36898007Ssaidi@eecs.umich.eduCallPal_OpcDec17: 36908007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36918007Ssaidi@eecs.umich.edu 36928007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0018) 36938007Ssaidi@eecs.umich.eduCallPal_OpcDec18: 36948007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36958007Ssaidi@eecs.umich.edu 36968007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0019) 36978007Ssaidi@eecs.umich.eduCallPal_OpcDec19: 36988007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36998007Ssaidi@eecs.umich.edu 37008007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001A) 37018007Ssaidi@eecs.umich.eduCallPal_OpcDec1A: 37028007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37038007Ssaidi@eecs.umich.edu 37048007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001B) 37058007Ssaidi@eecs.umich.eduCallPal_OpcDec1B: 37068007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37078007Ssaidi@eecs.umich.edu 37088007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001C) 37098007Ssaidi@eecs.umich.eduCallPal_OpcDec1C: 37108007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37118007Ssaidi@eecs.umich.edu 37128007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001D) 37138007Ssaidi@eecs.umich.eduCallPal_OpcDec1D: 37148007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37158007Ssaidi@eecs.umich.edu 37168007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001E) 37178007Ssaidi@eecs.umich.eduCallPal_OpcDec1E: 37188007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37198007Ssaidi@eecs.umich.edu 37208007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001F) 37218007Ssaidi@eecs.umich.eduCallPal_OpcDec1F: 37228007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37238007Ssaidi@eecs.umich.edu 37248007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0020) 37258007Ssaidi@eecs.umich.eduCallPal_OpcDec20: 37268007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37278007Ssaidi@eecs.umich.edu 37288007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0021) 37298007Ssaidi@eecs.umich.eduCallPal_OpcDec21: 37308007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37318007Ssaidi@eecs.umich.edu 37328007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0022) 37338007Ssaidi@eecs.umich.eduCallPal_OpcDec22: 37348007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37358007Ssaidi@eecs.umich.edu 37368007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0023) 37378007Ssaidi@eecs.umich.eduCallPal_OpcDec23: 37388007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37398007Ssaidi@eecs.umich.edu 37408007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0024) 37418007Ssaidi@eecs.umich.eduCallPal_OpcDec24: 37428007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37438007Ssaidi@eecs.umich.edu 37448007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0025) 37458007Ssaidi@eecs.umich.eduCallPal_OpcDec25: 37468007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37478007Ssaidi@eecs.umich.edu 37488007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0026) 37498007Ssaidi@eecs.umich.eduCallPal_OpcDec26: 37508007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37518007Ssaidi@eecs.umich.edu 37528007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0027) 37538007Ssaidi@eecs.umich.eduCallPal_OpcDec27: 37548007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37558007Ssaidi@eecs.umich.edu 37568007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0028) 37578007Ssaidi@eecs.umich.eduCallPal_OpcDec28: 37588007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37598007Ssaidi@eecs.umich.edu 37608007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0029) 37618007Ssaidi@eecs.umich.eduCallPal_OpcDec29: 37628007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37638007Ssaidi@eecs.umich.edu 37648007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002A) 37658007Ssaidi@eecs.umich.eduCallPal_OpcDec2A: 37668007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37678007Ssaidi@eecs.umich.edu 37688007Ssaidi@eecs.umich.edu// .sbttl "wrfen - PALcode for wrfen instruction" 37698007Ssaidi@eecs.umich.edu 37708007Ssaidi@eecs.umich.edu//+ 37718007Ssaidi@eecs.umich.edu// 37728007Ssaidi@eecs.umich.edu// Entry: 37738007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 37748007Ssaidi@eecs.umich.edu// 37758007Ssaidi@eecs.umich.edu// Function: 37768007Ssaidi@eecs.umich.edu// a0<0> -> ICSR<FPE> 37778007Ssaidi@eecs.umich.edu// Store new FEN in PCB 37788007Ssaidi@eecs.umich.edu// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE 37798007Ssaidi@eecs.umich.edu// 37808007Ssaidi@eecs.umich.edu// Issue: What about pending FP loads when FEN goes from on->off???? 37818007Ssaidi@eecs.umich.edu//- 37828007Ssaidi@eecs.umich.edu 37838007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRFEN_ENTRY) 37848007Ssaidi@eecs.umich.eduCall_Pal_Wrfen: 37858007Ssaidi@eecs.umich.edu or r31, 1, r13 // Get a one 37868007Ssaidi@eecs.umich.edu mfpr r1, ev5__icsr // Get current FPE 37878007Ssaidi@eecs.umich.edu 37888007Ssaidi@eecs.umich.edu sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0 37898007Ssaidi@eecs.umich.edu and r16, 1, r16 // clean new fen 37908007Ssaidi@eecs.umich.edu 37918007Ssaidi@eecs.umich.edu sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position 37928007Ssaidi@eecs.umich.edu bic r1, r13, r1 // zero icsr<fpe> 37938007Ssaidi@eecs.umich.edu 37948007Ssaidi@eecs.umich.edu or r1, r12, r1 // Or new FEN into ICSR 37958007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // Get PCBB - E1 37968007Ssaidi@eecs.umich.edu 37978007Ssaidi@eecs.umich.edu mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI 37988007Ssaidi@eecs.umich.edu stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB. 37998007Ssaidi@eecs.umich.edu 38008007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad ICSR<FPE> write. 38018007Ssaidi@eecs.umich.edu mfpr r31, pt0 38028007Ssaidi@eecs.umich.edu 38038007Ssaidi@eecs.umich.edu mfpr r31, pt0 38048007Ssaidi@eecs.umich.edu// pvc_violate 225 // cuz PVC can't distinguish which bits changed 38058007Ssaidi@eecs.umich.edu hw_rei 38068007Ssaidi@eecs.umich.edu 38078007Ssaidi@eecs.umich.edu 38088007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002C) 38098007Ssaidi@eecs.umich.eduCallPal_OpcDec2C: 38108007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 38118007Ssaidi@eecs.umich.edu 38128007Ssaidi@eecs.umich.edu// .sbttl "wrvptpr - PALcode for wrvptpr instruction" 38138007Ssaidi@eecs.umich.edu//+ 38148007Ssaidi@eecs.umich.edu// 38158007Ssaidi@eecs.umich.edu// Entry: 38168007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 38178007Ssaidi@eecs.umich.edu// 38188007Ssaidi@eecs.umich.edu// Function: 38198007Ssaidi@eecs.umich.edu// vptptr <- a0 (r16) 38208007Ssaidi@eecs.umich.edu//- 38218007Ssaidi@eecs.umich.edu 38228007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) 38238007Ssaidi@eecs.umich.eduCall_Pal_Wrvptptr: 38248007Ssaidi@eecs.umich.edu mtpr r16, ev5__mvptbr // Load Mbox copy 38258007Ssaidi@eecs.umich.edu mtpr r16, ev5__ivptbr // Load Ibox copy 38268007Ssaidi@eecs.umich.edu nop // Pad IPR write 38278007Ssaidi@eecs.umich.edu nop 38288007Ssaidi@eecs.umich.edu hw_rei 38298007Ssaidi@eecs.umich.edu 38308007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002E) 38318007Ssaidi@eecs.umich.eduCallPal_OpcDec2E: 38328007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 38338007Ssaidi@eecs.umich.edu 38348007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002F) 38358007Ssaidi@eecs.umich.eduCallPal_OpcDec2F: 38368007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 38378007Ssaidi@eecs.umich.edu 38388007Ssaidi@eecs.umich.edu// .sbttl "swpctx- PALcode for swpctx instruction" 38398007Ssaidi@eecs.umich.edu 38408007Ssaidi@eecs.umich.edu//+ 38418007Ssaidi@eecs.umich.edu// 38428007Ssaidi@eecs.umich.edu// Entry: 38438007Ssaidi@eecs.umich.edu// hardware dispatch via callPal instruction 38448007Ssaidi@eecs.umich.edu// R16 -> new pcb 38458007Ssaidi@eecs.umich.edu// 38468007Ssaidi@eecs.umich.edu// Function: 38478007Ssaidi@eecs.umich.edu// dynamic state moved to old pcb 38488007Ssaidi@eecs.umich.edu// new state loaded from new pcb 38498007Ssaidi@eecs.umich.edu// pcbb pointer set 38508007Ssaidi@eecs.umich.edu// old pcbb returned in R0 38518007Ssaidi@eecs.umich.edu// 38528007Ssaidi@eecs.umich.edu// Note: need to add perf monitor stuff 38538007Ssaidi@eecs.umich.edu//- 38548007Ssaidi@eecs.umich.edu 38558007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) 38568007Ssaidi@eecs.umich.eduCall_Pal_Swpctx: 38578007Ssaidi@eecs.umich.edu rpcc r13 // get cyccounter 38588007Ssaidi@eecs.umich.edu mfpr r0, pt_pcbb // get pcbb 38598007Ssaidi@eecs.umich.edu 38608007Ssaidi@eecs.umich.edu ldqp r22, osfpcb_q_fen(r16) // get new fen/pme 38618007Ssaidi@eecs.umich.edu ldqp r23, osfpcb_l_cc(r16) // get new asn 38628007Ssaidi@eecs.umich.edu 38638007Ssaidi@eecs.umich.edu srl r13, 32, r25 // move offset 38648007Ssaidi@eecs.umich.edu mfpr r24, pt_usp // get usp 38658007Ssaidi@eecs.umich.edu 38668007Ssaidi@eecs.umich.edu stqp r30, osfpcb_q_ksp(r0) // store old ksp 38678007Ssaidi@eecs.umich.edu// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow. 38688007Ssaidi@eecs.umich.edu mtpr r16, pt_pcbb // set new pcbb 38698007Ssaidi@eecs.umich.edu 38708007Ssaidi@eecs.umich.edu stqp r24, osfpcb_q_usp(r0) // store usp 38718007Ssaidi@eecs.umich.edu addl r13, r25, r25 // merge for new time 38728007Ssaidi@eecs.umich.edu 38738007Ssaidi@eecs.umich.edu stlp r25, osfpcb_l_cc(r0) // save time 38748007Ssaidi@eecs.umich.edu ldah r24, (1<<(icsr_v_fpe-16))(r31) 38758007Ssaidi@eecs.umich.edu 38768007Ssaidi@eecs.umich.edu and r22, 1, r12 // isolate fen 38778007Ssaidi@eecs.umich.edu mfpr r25, icsr // get current icsr 38788007Ssaidi@eecs.umich.edu 38798007Ssaidi@eecs.umich.edu ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24) 38808007Ssaidi@eecs.umich.edu br r31, swpctx_cont 38818007Ssaidi@eecs.umich.edu 38828007Ssaidi@eecs.umich.edu// .sbttl "wrval - PALcode for wrval instruction" 38838007Ssaidi@eecs.umich.edu//+ 38848007Ssaidi@eecs.umich.edu// 38858007Ssaidi@eecs.umich.edu// Entry: 38868007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 38878007Ssaidi@eecs.umich.edu// 38888007Ssaidi@eecs.umich.edu// Function: 38898007Ssaidi@eecs.umich.edu// sysvalue <- a0 (r16) 38908007Ssaidi@eecs.umich.edu//- 38918007Ssaidi@eecs.umich.edu 38928007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRVAL_ENTRY) 38938007Ssaidi@eecs.umich.eduCall_Pal_Wrval: 38948007Ssaidi@eecs.umich.edu nop 38958007Ssaidi@eecs.umich.edu mtpr r16, pt_sysval // Pad paltemp write 38968007Ssaidi@eecs.umich.edu nop 38978007Ssaidi@eecs.umich.edu nop 38988007Ssaidi@eecs.umich.edu hw_rei 38998007Ssaidi@eecs.umich.edu 39008007Ssaidi@eecs.umich.edu 39018007Ssaidi@eecs.umich.edu// .sbttl "rdval - PALcode for rdval instruction" 39028007Ssaidi@eecs.umich.edu 39038007Ssaidi@eecs.umich.edu//+ 39048007Ssaidi@eecs.umich.edu// 39058007Ssaidi@eecs.umich.edu// Entry: 39068007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 39078007Ssaidi@eecs.umich.edu// 39088007Ssaidi@eecs.umich.edu// Function: 39098007Ssaidi@eecs.umich.edu// v0 (r0) <- sysvalue 39108007Ssaidi@eecs.umich.edu//- 39118007Ssaidi@eecs.umich.edu 39128007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDVAL_ENTRY) 39138007Ssaidi@eecs.umich.eduCall_Pal_Rdval: 39148007Ssaidi@eecs.umich.edu nop 39158007Ssaidi@eecs.umich.edu mfpr r0, pt_sysval 39168007Ssaidi@eecs.umich.edu nop 39178007Ssaidi@eecs.umich.edu hw_rei 39188007Ssaidi@eecs.umich.edu 39198007Ssaidi@eecs.umich.edu// .sbttl "tbi - PALcode for tbi instruction" 39208007Ssaidi@eecs.umich.edu//+ 39218007Ssaidi@eecs.umich.edu// 39228007Ssaidi@eecs.umich.edu// Entry: 39238007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 39248007Ssaidi@eecs.umich.edu// 39258007Ssaidi@eecs.umich.edu// Function: 39268007Ssaidi@eecs.umich.edu// TB invalidate 39278007Ssaidi@eecs.umich.edu// r16/a0 = TBI type 39288007Ssaidi@eecs.umich.edu// r17/a1 = Va for TBISx instructions 39298007Ssaidi@eecs.umich.edu//- 39308007Ssaidi@eecs.umich.edu 39318007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_TBI_ENTRY) 39328007Ssaidi@eecs.umich.eduCall_Pal_Tbi: 39338007Ssaidi@eecs.umich.edu addq r16, 2, r16 // change range to 0-2 39348007Ssaidi@eecs.umich.edu br r23, CALL_PAL_tbi_10_ // get our address 39358007Ssaidi@eecs.umich.edu 39368007Ssaidi@eecs.umich.eduCALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range 39378007Ssaidi@eecs.umich.edu lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table 39388007Ssaidi@eecs.umich.edu sll r16, 4, r16 // * 16 39398007Ssaidi@eecs.umich.edu blbc r22, CALL_PAL_tbi_30_ // go rei, if not 39408007Ssaidi@eecs.umich.edu 39418007Ssaidi@eecs.umich.edu addq r23, r16, r23 // addr of our code 39428007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi 39438007Ssaidi@eecs.umich.edu jmp r31, (r23) // and go do it 39448007Ssaidi@eecs.umich.edu 39458007Ssaidi@eecs.umich.eduCALL_PAL_tbi_30_: 39468007Ssaidi@eecs.umich.edu hw_rei 39478007Ssaidi@eecs.umich.edu nop 39488007Ssaidi@eecs.umich.edu 39498007Ssaidi@eecs.umich.edu// .sbttl "wrent - PALcode for wrent instruction" 39508007Ssaidi@eecs.umich.edu//+ 39518007Ssaidi@eecs.umich.edu// 39528007Ssaidi@eecs.umich.edu// Entry: 39538007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 39548007Ssaidi@eecs.umich.edu// 39558007Ssaidi@eecs.umich.edu// Function: 39568007Ssaidi@eecs.umich.edu// Update ent* in paltemps 39578007Ssaidi@eecs.umich.edu// r16/a0 = Address of entry routine 39588007Ssaidi@eecs.umich.edu// r17/a1 = Entry Number 0..5 39598007Ssaidi@eecs.umich.edu// 39608007Ssaidi@eecs.umich.edu// r22, r23 trashed 39618007Ssaidi@eecs.umich.edu//- 39628007Ssaidi@eecs.umich.edu 39638007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRENT_ENTRY) 39648007Ssaidi@eecs.umich.eduCall_Pal_Wrent: 39658007Ssaidi@eecs.umich.edu cmpult r17, 6, r22 // see if in range 39668007Ssaidi@eecs.umich.edu br r23, CALL_PAL_wrent_10_ // get our address 39678007Ssaidi@eecs.umich.edu 39688007Ssaidi@eecs.umich.eduCALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc 39698007Ssaidi@eecs.umich.edu blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range 39708007Ssaidi@eecs.umich.edu 39718007Ssaidi@eecs.umich.edu lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table 39728007Ssaidi@eecs.umich.edu sll r17, 4, r17 // *16 39738007Ssaidi@eecs.umich.edu 39748007Ssaidi@eecs.umich.edu addq r17, r23, r23 // Get address in table 39758007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent 39768007Ssaidi@eecs.umich.edu jmp r31, (r23) // and go do it 39778007Ssaidi@eecs.umich.edu 39788007Ssaidi@eecs.umich.eduCALL_PAL_wrent_30_: 39798007Ssaidi@eecs.umich.edu hw_rei // out of range, just return 39808007Ssaidi@eecs.umich.edu 39818007Ssaidi@eecs.umich.edu// .sbttl "swpipl - PALcode for swpipl instruction" 39828007Ssaidi@eecs.umich.edu//+ 39838007Ssaidi@eecs.umich.edu// 39848007Ssaidi@eecs.umich.edu// Entry: 39858007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 39868007Ssaidi@eecs.umich.edu// 39878007Ssaidi@eecs.umich.edu// Function: 39888007Ssaidi@eecs.umich.edu// v0 (r0) <- PS<IPL> 39898007Ssaidi@eecs.umich.edu// PS<IPL> <- a0<2:0> (r16) 39908007Ssaidi@eecs.umich.edu// 39918007Ssaidi@eecs.umich.edu// t8 (r22) is scratch 39928007Ssaidi@eecs.umich.edu//- 39938007Ssaidi@eecs.umich.edu 39948007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) 39958007Ssaidi@eecs.umich.eduCall_Pal_Swpipl: 39968007Ssaidi@eecs.umich.edu and r16, osfps_m_ipl, r16 // clean New ipl 39978007Ssaidi@eecs.umich.edu mfpr r22, pt_intmask // get int mask 39988007Ssaidi@eecs.umich.edu 39998007Ssaidi@eecs.umich.edu extbl r22, r16, r22 // get mask for this ipl 40008007Ssaidi@eecs.umich.edu bis r11, r31, r0 // return old ipl 40018007Ssaidi@eecs.umich.edu 40028007Ssaidi@eecs.umich.edu bis r16, r31, r11 // set new ps 40038007Ssaidi@eecs.umich.edu mtpr r22, ev5__ipl // set new mask 40048007Ssaidi@eecs.umich.edu 40058007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad ipl write 40068007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad ipl write 40078007Ssaidi@eecs.umich.edu 40088007Ssaidi@eecs.umich.edu hw_rei // back 40098007Ssaidi@eecs.umich.edu 40108007Ssaidi@eecs.umich.edu// .sbttl "rdps - PALcode for rdps instruction" 40118007Ssaidi@eecs.umich.edu//+ 40128007Ssaidi@eecs.umich.edu// 40138007Ssaidi@eecs.umich.edu// Entry: 40148007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 40158007Ssaidi@eecs.umich.edu// 40168007Ssaidi@eecs.umich.edu// Function: 40178007Ssaidi@eecs.umich.edu// v0 (r0) <- ps 40188007Ssaidi@eecs.umich.edu//- 40198007Ssaidi@eecs.umich.edu 40208007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDPS_ENTRY) 40218007Ssaidi@eecs.umich.eduCall_Pal_Rdps: 40228007Ssaidi@eecs.umich.edu bis r11, r31, r0 // Fetch PALshadow PS 40238007Ssaidi@eecs.umich.edu nop // Must be 2 cycles long 40248007Ssaidi@eecs.umich.edu hw_rei 40258007Ssaidi@eecs.umich.edu 40268007Ssaidi@eecs.umich.edu// .sbttl "wrkgp - PALcode for wrkgp instruction" 40278007Ssaidi@eecs.umich.edu//+ 40288007Ssaidi@eecs.umich.edu// 40298007Ssaidi@eecs.umich.edu// Entry: 40308007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 40318007Ssaidi@eecs.umich.edu// 40328007Ssaidi@eecs.umich.edu// Function: 40338007Ssaidi@eecs.umich.edu// kgp <- a0 (r16) 40348007Ssaidi@eecs.umich.edu//- 40358007Ssaidi@eecs.umich.edu 40368007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRKGP_ENTRY) 40378007Ssaidi@eecs.umich.eduCall_Pal_Wrkgp: 40388007Ssaidi@eecs.umich.edu nop 40398007Ssaidi@eecs.umich.edu mtpr r16, pt_kgp 40408007Ssaidi@eecs.umich.edu nop // Pad for pt write->read restriction 40418007Ssaidi@eecs.umich.edu nop 40428007Ssaidi@eecs.umich.edu hw_rei 40438007Ssaidi@eecs.umich.edu 40448007Ssaidi@eecs.umich.edu// .sbttl "wrusp - PALcode for wrusp instruction" 40458007Ssaidi@eecs.umich.edu//+ 40468007Ssaidi@eecs.umich.edu// 40478007Ssaidi@eecs.umich.edu// Entry: 40488007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 40498007Ssaidi@eecs.umich.edu// 40508007Ssaidi@eecs.umich.edu// Function: 40518007Ssaidi@eecs.umich.edu// usp <- a0 (r16) 40528007Ssaidi@eecs.umich.edu//- 40538007Ssaidi@eecs.umich.edu 40548007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRUSP_ENTRY) 40558007Ssaidi@eecs.umich.eduCall_Pal_Wrusp: 40568007Ssaidi@eecs.umich.edu nop 40578007Ssaidi@eecs.umich.edu mtpr r16, pt_usp 40588007Ssaidi@eecs.umich.edu nop // Pad possible pt write->read restriction 40598007Ssaidi@eecs.umich.edu nop 40608007Ssaidi@eecs.umich.edu hw_rei 40618007Ssaidi@eecs.umich.edu 40628007Ssaidi@eecs.umich.edu// .sbttl "wrperfmon - PALcode for wrperfmon instruction" 40638007Ssaidi@eecs.umich.edu//+ 40648007Ssaidi@eecs.umich.edu// 40658007Ssaidi@eecs.umich.edu// Entry: 40668007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 40678007Ssaidi@eecs.umich.edu// 40688007Ssaidi@eecs.umich.edu// 40698007Ssaidi@eecs.umich.edu// Function: 40708007Ssaidi@eecs.umich.edu// Various control functions for the onchip performance counters 40718007Ssaidi@eecs.umich.edu// 40728007Ssaidi@eecs.umich.edu// option selector in r16 40738007Ssaidi@eecs.umich.edu// option argument in r17 40748007Ssaidi@eecs.umich.edu// returned status in r0 40758007Ssaidi@eecs.umich.edu// 40768007Ssaidi@eecs.umich.edu// 40778007Ssaidi@eecs.umich.edu// r16 = 0 Disable performance monitoring for one or more cpu's 40788007Ssaidi@eecs.umich.edu// r17 = 0 disable no counters 40798007Ssaidi@eecs.umich.edu// r17 = bitmask disable counters specified in bit mask (1=disable) 40808007Ssaidi@eecs.umich.edu// 40818007Ssaidi@eecs.umich.edu// r16 = 1 Enable performance monitoring for one or more cpu's 40828007Ssaidi@eecs.umich.edu// r17 = 0 enable no counters 40838007Ssaidi@eecs.umich.edu// r17 = bitmask enable counters specified in bit mask (1=enable) 40848007Ssaidi@eecs.umich.edu// 40858007Ssaidi@eecs.umich.edu// r16 = 2 Mux select for one or more cpu's 40868007Ssaidi@eecs.umich.edu// r17 = Mux selection (cpu specific) 40878007Ssaidi@eecs.umich.edu// <24:19> bc_ctl<pm_mux_sel> field (see spec) 40888007Ssaidi@eecs.umich.edu// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec) 40898007Ssaidi@eecs.umich.edu// 40908007Ssaidi@eecs.umich.edu// r16 = 3 Options 40918007Ssaidi@eecs.umich.edu// r17 = (cpu specific) 40928007Ssaidi@eecs.umich.edu// <0> = 0 log all processes 40938007Ssaidi@eecs.umich.edu// <0> = 1 log only selected processes 40948007Ssaidi@eecs.umich.edu// <30,9,8> mode select - ku,kp,kk 40958007Ssaidi@eecs.umich.edu// 40968007Ssaidi@eecs.umich.edu// r16 = 4 Interrupt frequency select 40978007Ssaidi@eecs.umich.edu// r17 = (cpu specific) indicates interrupt frequencies desired for each 40988007Ssaidi@eecs.umich.edu// counter, with "zero interrupts" being an option 40998007Ssaidi@eecs.umich.edu// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below 41008007Ssaidi@eecs.umich.edu// 41018007Ssaidi@eecs.umich.edu// r16 = 5 Read Counters 41028007Ssaidi@eecs.umich.edu// r17 = na 41038007Ssaidi@eecs.umich.edu// r0 = value (same format as ev5 pmctr) 41048007Ssaidi@eecs.umich.edu// <0> = 0 Read failed 41058007Ssaidi@eecs.umich.edu// <0> = 1 Read succeeded 41068007Ssaidi@eecs.umich.edu// 41078007Ssaidi@eecs.umich.edu// r16 = 6 Write Counters 41088007Ssaidi@eecs.umich.edu// r17 = value (same format as ev5 pmctr; all counters written simultaneously) 41098007Ssaidi@eecs.umich.edu// 41108007Ssaidi@eecs.umich.edu// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0 41118007Ssaidi@eecs.umich.edu// r17 = 0 enable no counters 41128007Ssaidi@eecs.umich.edu// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear) 41138007Ssaidi@eecs.umich.edu// 41148007Ssaidi@eecs.umich.edu//============================================================================= 41158007Ssaidi@eecs.umich.edu//Assumptions: 41168007Ssaidi@eecs.umich.edu//PMCTR_CTL: 41178007Ssaidi@eecs.umich.edu// 41188007Ssaidi@eecs.umich.edu// <15:14> CTL0 -- encoded frequency select and enable - CTR0 41198007Ssaidi@eecs.umich.edu// <13:12> CTL1 -- " - CTR1 41208007Ssaidi@eecs.umich.edu// <11:10> CTL2 -- " - CTR2 41218007Ssaidi@eecs.umich.edu// 41228007Ssaidi@eecs.umich.edu// <9:8> FRQ0 -- frequency select for CTR0 (no enable info) 41238007Ssaidi@eecs.umich.edu// <7:6> FRQ1 -- frequency select for CTR1 41248007Ssaidi@eecs.umich.edu// <5:4> FRQ2 -- frequency select for CTR2 41258007Ssaidi@eecs.umich.edu// 41268007Ssaidi@eecs.umich.edu// <0> all vs. select processes (0=all,1=select) 41278007Ssaidi@eecs.umich.edu// 41288007Ssaidi@eecs.umich.edu// where 41298007Ssaidi@eecs.umich.edu// FRQx<1:0> 41308007Ssaidi@eecs.umich.edu// 0 1 disable interrupt 41318007Ssaidi@eecs.umich.edu// 1 0 frequency = 65536 (16384 for ctr2) 41328007Ssaidi@eecs.umich.edu// 1 1 frequency = 256 41338007Ssaidi@eecs.umich.edu// note: FRQx<1:0> = 00 will keep counters from ever being enabled. 41348007Ssaidi@eecs.umich.edu// 41358007Ssaidi@eecs.umich.edu//============================================================================= 41368007Ssaidi@eecs.umich.edu// 41378007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0039) 41388007Ssaidi@eecs.umich.edu// unsupported in Hudson code .. pboyle Nov/95 41398007Ssaidi@eecs.umich.eduCALL_PAL_Wrperfmon: 41408007Ssaidi@eecs.umich.edu#if perfmon_debug == 0 41418007Ssaidi@eecs.umich.edu // "real" performance monitoring code 41428007Ssaidi@eecs.umich.edu cmpeq r16, 1, r0 // check for enable 41438007Ssaidi@eecs.umich.edu bne r0, perfmon_en // br if requested to enable 41448007Ssaidi@eecs.umich.edu 41458007Ssaidi@eecs.umich.edu cmpeq r16, 2, r0 // check for mux ctl 41468007Ssaidi@eecs.umich.edu bne r0, perfmon_muxctl // br if request to set mux controls 41478007Ssaidi@eecs.umich.edu 41488007Ssaidi@eecs.umich.edu cmpeq r16, 3, r0 // check for options 41498007Ssaidi@eecs.umich.edu bne r0, perfmon_ctl // br if request to set options 41508007Ssaidi@eecs.umich.edu 41518007Ssaidi@eecs.umich.edu cmpeq r16, 4, r0 // check for interrupt frequency select 41528007Ssaidi@eecs.umich.edu bne r0, perfmon_freq // br if request to change frequency select 41538007Ssaidi@eecs.umich.edu 41548007Ssaidi@eecs.umich.edu cmpeq r16, 5, r0 // check for counter read request 41558007Ssaidi@eecs.umich.edu bne r0, perfmon_rd // br if request to read counters 41568007Ssaidi@eecs.umich.edu 41578007Ssaidi@eecs.umich.edu cmpeq r16, 6, r0 // check for counter write request 41588007Ssaidi@eecs.umich.edu bne r0, perfmon_wr // br if request to write counters 41598007Ssaidi@eecs.umich.edu 41608007Ssaidi@eecs.umich.edu cmpeq r16, 7, r0 // check for counter clear/enable request 41618007Ssaidi@eecs.umich.edu bne r0, perfmon_enclr // br if request to clear/enable counters 41628007Ssaidi@eecs.umich.edu 41638007Ssaidi@eecs.umich.edu beq r16, perfmon_dis // br if requested to disable (r16=0) 41648007Ssaidi@eecs.umich.edu br r31, perfmon_unknown // br if unknown request 41658007Ssaidi@eecs.umich.edu#else 41668007Ssaidi@eecs.umich.edu 41678007Ssaidi@eecs.umich.edu br r31, pal_perfmon_debug 41688007Ssaidi@eecs.umich.edu#endif 41698007Ssaidi@eecs.umich.edu 41708007Ssaidi@eecs.umich.edu// .sbttl "rdusp - PALcode for rdusp instruction" 41718007Ssaidi@eecs.umich.edu//+ 41728007Ssaidi@eecs.umich.edu// 41738007Ssaidi@eecs.umich.edu// Entry: 41748007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 41758007Ssaidi@eecs.umich.edu// 41768007Ssaidi@eecs.umich.edu// Function: 41778007Ssaidi@eecs.umich.edu// v0 (r0) <- usp 41788007Ssaidi@eecs.umich.edu//- 41798007Ssaidi@eecs.umich.edu 41808007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDUSP_ENTRY) 41818007Ssaidi@eecs.umich.eduCall_Pal_Rdusp: 41828007Ssaidi@eecs.umich.edu nop 41838007Ssaidi@eecs.umich.edu mfpr r0, pt_usp 41848007Ssaidi@eecs.umich.edu hw_rei 41858007Ssaidi@eecs.umich.edu 41868007Ssaidi@eecs.umich.edu 41878007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x003B) 41888007Ssaidi@eecs.umich.eduCallPal_OpcDec3B: 41898007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 41908007Ssaidi@eecs.umich.edu 41918007Ssaidi@eecs.umich.edu// .sbttl "whami - PALcode for whami instruction" 41928007Ssaidi@eecs.umich.edu//+ 41938007Ssaidi@eecs.umich.edu// 41948007Ssaidi@eecs.umich.edu// Entry: 41958007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 41968007Ssaidi@eecs.umich.edu// 41978007Ssaidi@eecs.umich.edu// Function: 41988007Ssaidi@eecs.umich.edu// v0 (r0) <- whami 41998007Ssaidi@eecs.umich.edu//- 42008007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WHAMI_ENTRY) 42018007Ssaidi@eecs.umich.eduCall_Pal_Whami: 42028007Ssaidi@eecs.umich.edu nop 42038007Ssaidi@eecs.umich.edu mfpr r0, pt_whami // Get Whami 42048007Ssaidi@eecs.umich.edu extbl r0, 1, r0 // Isolate just whami bits 42058007Ssaidi@eecs.umich.edu hw_rei 42068007Ssaidi@eecs.umich.edu 42078007Ssaidi@eecs.umich.edu// .sbttl "retsys - PALcode for retsys instruction" 42088007Ssaidi@eecs.umich.edu// 42098007Ssaidi@eecs.umich.edu// Entry: 42108007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 42118007Ssaidi@eecs.umich.edu// 00(sp) contains return pc 42128007Ssaidi@eecs.umich.edu// 08(sp) contains r29 42138007Ssaidi@eecs.umich.edu// 42148007Ssaidi@eecs.umich.edu// Function: 42158007Ssaidi@eecs.umich.edu// Return from system call. 42168007Ssaidi@eecs.umich.edu// mode switched from kern to user. 42178007Ssaidi@eecs.umich.edu// stacks swapped, ugp, upc restored. 42188007Ssaidi@eecs.umich.edu// r23, r25 junked 42198007Ssaidi@eecs.umich.edu//- 42208007Ssaidi@eecs.umich.edu 42218007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RETSYS_ENTRY) 42228007Ssaidi@eecs.umich.eduCall_Pal_Retsys: 42238007Ssaidi@eecs.umich.edu lda r25, osfsf_c_size(sp) // pop stack 42248007Ssaidi@eecs.umich.edu bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr 42258007Ssaidi@eecs.umich.edu 42268007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // save exc_addr in case of fault 42278007Ssaidi@eecs.umich.edu ldq r23, osfsf_pc(sp) // get pc 42288007Ssaidi@eecs.umich.edu 42298007Ssaidi@eecs.umich.edu ldq r29, osfsf_gp(sp) // get gp 42308007Ssaidi@eecs.umich.edu stl_c r31, -4(sp) // clear lock_flag 42318007Ssaidi@eecs.umich.edu 42328007Ssaidi@eecs.umich.edu lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user 42338007Ssaidi@eecs.umich.edu mfpr r30, pt_usp // get users stack 42348007Ssaidi@eecs.umich.edu 42358007Ssaidi@eecs.umich.edu bic r23, 3, r23 // clean return pc 42368007Ssaidi@eecs.umich.edu mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei 42378007Ssaidi@eecs.umich.edu 42388007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 42398007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 42408007Ssaidi@eecs.umich.edu 42418007Ssaidi@eecs.umich.edu mtpr r23, exc_addr // set return address - 1 bubble to hw_rei 42428007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save kern stack 42438007Ssaidi@eecs.umich.edu 42448007Ssaidi@eecs.umich.edu rc r31 // clear inter_flag 42458007Ssaidi@eecs.umich.edu// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal 42468007Ssaidi@eecs.umich.edu hw_rei_spe // and back 42478007Ssaidi@eecs.umich.edu 42488007Ssaidi@eecs.umich.edu 42498007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x003E) 42508007Ssaidi@eecs.umich.eduCallPal_OpcDec3E: 42518007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 42528007Ssaidi@eecs.umich.edu 42538007Ssaidi@eecs.umich.edu// .sbttl "rti - PALcode for rti instruction" 42548007Ssaidi@eecs.umich.edu//+ 42558007Ssaidi@eecs.umich.edu// 42568007Ssaidi@eecs.umich.edu// Entry: 42578007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 42588007Ssaidi@eecs.umich.edu// 42598007Ssaidi@eecs.umich.edu// Function: 42608007Ssaidi@eecs.umich.edu// 00(sp) -> ps 42618007Ssaidi@eecs.umich.edu// 08(sp) -> pc 42628007Ssaidi@eecs.umich.edu// 16(sp) -> r29 (gp) 42638007Ssaidi@eecs.umich.edu// 24(sp) -> r16 (a0) 42648007Ssaidi@eecs.umich.edu// 32(sp) -> r17 (a1) 42658007Ssaidi@eecs.umich.edu// 40(sp) -> r18 (a3) 42668007Ssaidi@eecs.umich.edu//- 42678007Ssaidi@eecs.umich.edu 42688007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RTI_ENTRY) 42698007Ssaidi@eecs.umich.edu#ifdef SIMOS 42708007Ssaidi@eecs.umich.edu /* called once by platform_tlaser */ 42718007Ssaidi@eecs.umich.edu .globl Call_Pal_Rti 42728007Ssaidi@eecs.umich.edu#endif 42738007Ssaidi@eecs.umich.eduCall_Pal_Rti: 42748007Ssaidi@eecs.umich.edu lda r25, osfsf_c_size(sp) // get updated sp 42758007Ssaidi@eecs.umich.edu bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr 42768007Ssaidi@eecs.umich.edu 42778007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // save PC in case of fault 42788007Ssaidi@eecs.umich.edu rc r31 // clear intr_flag 42798007Ssaidi@eecs.umich.edu 42808007Ssaidi@eecs.umich.edu ldq r12, -6*8(r25) // get ps 42818007Ssaidi@eecs.umich.edu ldq r13, -5*8(r25) // pc 42828007Ssaidi@eecs.umich.edu 42838007Ssaidi@eecs.umich.edu ldq r18, -1*8(r25) // a2 42848007Ssaidi@eecs.umich.edu ldq r17, -2*8(r25) // a1 42858007Ssaidi@eecs.umich.edu 42868007Ssaidi@eecs.umich.edu ldq r16, -3*8(r25) // a0 42878007Ssaidi@eecs.umich.edu ldq r29, -4*8(r25) // gp 42888007Ssaidi@eecs.umich.edu 42898007Ssaidi@eecs.umich.edu bic r13, 3, r13 // clean return pc 42908007Ssaidi@eecs.umich.edu stl_c r31, -4(r25) // clear lock_flag 42918007Ssaidi@eecs.umich.edu 42928007Ssaidi@eecs.umich.edu and r12, osfps_m_mode, r11 // get mode 42938007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set return address 42948007Ssaidi@eecs.umich.edu 42958007Ssaidi@eecs.umich.edu beq r11, rti_to_kern // br if rti to Kern 42968007Ssaidi@eecs.umich.edu br r31, rti_to_user // out of call_pal space 42978007Ssaidi@eecs.umich.edu 42988007Ssaidi@eecs.umich.edu 42998007Ssaidi@eecs.umich.edu// .sbttl "Start the Unprivileged CALL_PAL Entry Points" 43008007Ssaidi@eecs.umich.edu// .sbttl "bpt- PALcode for bpt instruction" 43018007Ssaidi@eecs.umich.edu//+ 43028007Ssaidi@eecs.umich.edu// 43038007Ssaidi@eecs.umich.edu// Entry: 43048007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 43058007Ssaidi@eecs.umich.edu// 43068007Ssaidi@eecs.umich.edu// Function: 43078007Ssaidi@eecs.umich.edu// Build stack frame 43088007Ssaidi@eecs.umich.edu// a0 <- code 43098007Ssaidi@eecs.umich.edu// a1 <- unpred 43108007Ssaidi@eecs.umich.edu// a2 <- unpred 43118007Ssaidi@eecs.umich.edu// vector via entIF 43128007Ssaidi@eecs.umich.edu// 43138007Ssaidi@eecs.umich.edu//- 43148007Ssaidi@eecs.umich.edu// 43158007Ssaidi@eecs.umich.edu .text 1 43168007Ssaidi@eecs.umich.edu// . = 0x3000 43178007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_BPT_ENTRY) 43188007Ssaidi@eecs.umich.eduCall_Pal_Bpt: 43198007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 43208007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 43218007Ssaidi@eecs.umich.edu 43228007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 43238007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern 43248007Ssaidi@eecs.umich.edu 43258007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 43268007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 43278007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 43288007Ssaidi@eecs.umich.edu 43298007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 43308007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 43318007Ssaidi@eecs.umich.edu 43328007Ssaidi@eecs.umich.eduCALL_PAL_bpt_10_: 43338007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 43348007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 43358007Ssaidi@eecs.umich.edu 43368007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 43378007Ssaidi@eecs.umich.edu bis r31, osf_a0_bpt, r16 // set a0 43388007Ssaidi@eecs.umich.edu 43398007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 43408007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 43418007Ssaidi@eecs.umich.edu 43428007Ssaidi@eecs.umich.edu 43438007Ssaidi@eecs.umich.edu// .sbttl "bugchk- PALcode for bugchk instruction" 43448007Ssaidi@eecs.umich.edu//+ 43458007Ssaidi@eecs.umich.edu// 43468007Ssaidi@eecs.umich.edu// Entry: 43478007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 43488007Ssaidi@eecs.umich.edu// 43498007Ssaidi@eecs.umich.edu// Function: 43508007Ssaidi@eecs.umich.edu// Build stack frame 43518007Ssaidi@eecs.umich.edu// a0 <- code 43528007Ssaidi@eecs.umich.edu// a1 <- unpred 43538007Ssaidi@eecs.umich.edu// a2 <- unpred 43548007Ssaidi@eecs.umich.edu// vector via entIF 43558007Ssaidi@eecs.umich.edu// 43568007Ssaidi@eecs.umich.edu//- 43578007Ssaidi@eecs.umich.edu// 43588007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY) 43598007Ssaidi@eecs.umich.eduCall_Pal_Bugchk: 43608007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 43618007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 43628007Ssaidi@eecs.umich.edu 43638007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 43648007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern 43658007Ssaidi@eecs.umich.edu 43668007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 43678007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 43688007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 43698007Ssaidi@eecs.umich.edu 43708007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 43718007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 43728007Ssaidi@eecs.umich.edu 43738007Ssaidi@eecs.umich.eduCALL_PAL_bugchk_10_: 43748007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 43758007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 43768007Ssaidi@eecs.umich.edu 43778007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 43788007Ssaidi@eecs.umich.edu bis r31, osf_a0_bugchk, r16 // set a0 43798007Ssaidi@eecs.umich.edu 43808007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 43818007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 43828007Ssaidi@eecs.umich.edu 43838007Ssaidi@eecs.umich.edu 43848007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0082) 43858007Ssaidi@eecs.umich.eduCallPal_OpcDec82: 43868007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 43878007Ssaidi@eecs.umich.edu 43888007Ssaidi@eecs.umich.edu// .sbttl "callsys - PALcode for callsys instruction" 43898007Ssaidi@eecs.umich.edu//+ 43908007Ssaidi@eecs.umich.edu// 43918007Ssaidi@eecs.umich.edu// Entry: 43928007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 43938007Ssaidi@eecs.umich.edu// 43948007Ssaidi@eecs.umich.edu// Function: 43958007Ssaidi@eecs.umich.edu// Switch mode to kernel and build a callsys stack frame. 43968007Ssaidi@eecs.umich.edu// sp = ksp 43978007Ssaidi@eecs.umich.edu// gp = kgp 43988007Ssaidi@eecs.umich.edu// t8 - t10 (r22-r24) trashed 43998007Ssaidi@eecs.umich.edu// 44008007Ssaidi@eecs.umich.edu//- 44018007Ssaidi@eecs.umich.edu// 44028007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY) 44038007Ssaidi@eecs.umich.eduCall_Pal_Callsys: 44048007Ssaidi@eecs.umich.edu 44058007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r24 // get mode 44068007Ssaidi@eecs.umich.edu mfpr r22, pt_ksp // get ksp 44078007Ssaidi@eecs.umich.edu 44088007Ssaidi@eecs.umich.edu beq r24, sys_from_kern // sysCall from kern is not allowed 44098007Ssaidi@eecs.umich.edu mfpr r12, pt_entsys // get address of callSys routine 44108007Ssaidi@eecs.umich.edu 44118007Ssaidi@eecs.umich.edu//+ 44128007Ssaidi@eecs.umich.edu// from here on we know we are in user going to Kern 44138007Ssaidi@eecs.umich.edu//- 44148007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 44158007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 44168007Ssaidi@eecs.umich.edu 44178007Ssaidi@eecs.umich.edu bis r31, r31, r11 // PS=0 (mode=kern) 44188007Ssaidi@eecs.umich.edu mfpr r23, exc_addr // get pc 44198007Ssaidi@eecs.umich.edu 44208007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save usp 44218007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(r22)// set new sp 44228007Ssaidi@eecs.umich.edu 44238007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save user gp/r29 44248007Ssaidi@eecs.umich.edu stq r24, osfsf_ps(sp) // save ps 44258007Ssaidi@eecs.umich.edu 44268007Ssaidi@eecs.umich.edu stq r23, osfsf_pc(sp) // save pc 44278007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // set address 44288007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 44298007Ssaidi@eecs.umich.edu 44308007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kern gp/r29 44318007Ssaidi@eecs.umich.edu 44328007Ssaidi@eecs.umich.edu hw_rei_spe // and off we go! 44338007Ssaidi@eecs.umich.edu 44348007Ssaidi@eecs.umich.edu 44358007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0084) 44368007Ssaidi@eecs.umich.eduCallPal_OpcDec84: 44378007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44388007Ssaidi@eecs.umich.edu 44398007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0085) 44408007Ssaidi@eecs.umich.eduCallPal_OpcDec85: 44418007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44428007Ssaidi@eecs.umich.edu 44438007Ssaidi@eecs.umich.edu// .sbttl "imb - PALcode for imb instruction" 44448007Ssaidi@eecs.umich.edu//+ 44458007Ssaidi@eecs.umich.edu// 44468007Ssaidi@eecs.umich.edu// Entry: 44478007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 44488007Ssaidi@eecs.umich.edu// 44498007Ssaidi@eecs.umich.edu// Function: 44508007Ssaidi@eecs.umich.edu// Flush the writebuffer and flush the Icache 44518007Ssaidi@eecs.umich.edu// 44528007Ssaidi@eecs.umich.edu//- 44538007Ssaidi@eecs.umich.edu// 44548007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_IMB_ENTRY) 44558007Ssaidi@eecs.umich.eduCall_Pal_Imb: 44568007Ssaidi@eecs.umich.edu mb // Clear the writebuffer 44578007Ssaidi@eecs.umich.edu mfpr r31, ev5__mcsr // Sync with clear 44588007Ssaidi@eecs.umich.edu nop 44598007Ssaidi@eecs.umich.edu nop 44608007Ssaidi@eecs.umich.edu br r31, pal_ic_flush // Flush Icache 44618007Ssaidi@eecs.umich.edu 44628007Ssaidi@eecs.umich.edu 44638007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 44648007Ssaidi@eecs.umich.edu 44658007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0087) 44668007Ssaidi@eecs.umich.eduCallPal_OpcDec87: 44678007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44688007Ssaidi@eecs.umich.edu 44698007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0088) 44708007Ssaidi@eecs.umich.eduCallPal_OpcDec88: 44718007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44728007Ssaidi@eecs.umich.edu 44738007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0089) 44748007Ssaidi@eecs.umich.eduCallPal_OpcDec89: 44758007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44768007Ssaidi@eecs.umich.edu 44778007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008A) 44788007Ssaidi@eecs.umich.eduCallPal_OpcDec8A: 44798007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44808007Ssaidi@eecs.umich.edu 44818007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008B) 44828007Ssaidi@eecs.umich.eduCallPal_OpcDec8B: 44838007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44848007Ssaidi@eecs.umich.edu 44858007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008C) 44868007Ssaidi@eecs.umich.eduCallPal_OpcDec8C: 44878007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44888007Ssaidi@eecs.umich.edu 44898007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008D) 44908007Ssaidi@eecs.umich.eduCallPal_OpcDec8D: 44918007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44928007Ssaidi@eecs.umich.edu 44938007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008E) 44948007Ssaidi@eecs.umich.eduCallPal_OpcDec8E: 44958007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 44968007Ssaidi@eecs.umich.edu 44978007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008F) 44988007Ssaidi@eecs.umich.eduCallPal_OpcDec8F: 44998007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45008007Ssaidi@eecs.umich.edu 45018007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0090) 45028007Ssaidi@eecs.umich.eduCallPal_OpcDec90: 45038007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45048007Ssaidi@eecs.umich.edu 45058007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0091) 45068007Ssaidi@eecs.umich.eduCallPal_OpcDec91: 45078007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45088007Ssaidi@eecs.umich.edu 45098007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0092) 45108007Ssaidi@eecs.umich.eduCallPal_OpcDec92: 45118007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45128007Ssaidi@eecs.umich.edu 45138007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0093) 45148007Ssaidi@eecs.umich.eduCallPal_OpcDec93: 45158007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45168007Ssaidi@eecs.umich.edu 45178007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0094) 45188007Ssaidi@eecs.umich.eduCallPal_OpcDec94: 45198007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45208007Ssaidi@eecs.umich.edu 45218007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0095) 45228007Ssaidi@eecs.umich.eduCallPal_OpcDec95: 45238007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45248007Ssaidi@eecs.umich.edu 45258007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0096) 45268007Ssaidi@eecs.umich.eduCallPal_OpcDec96: 45278007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45288007Ssaidi@eecs.umich.edu 45298007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0097) 45308007Ssaidi@eecs.umich.eduCallPal_OpcDec97: 45318007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45328007Ssaidi@eecs.umich.edu 45338007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0098) 45348007Ssaidi@eecs.umich.eduCallPal_OpcDec98: 45358007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45368007Ssaidi@eecs.umich.edu 45378007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0099) 45388007Ssaidi@eecs.umich.eduCallPal_OpcDec99: 45398007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45408007Ssaidi@eecs.umich.edu 45418007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009A) 45428007Ssaidi@eecs.umich.eduCallPal_OpcDec9A: 45438007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45448007Ssaidi@eecs.umich.edu 45458007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009B) 45468007Ssaidi@eecs.umich.eduCallPal_OpcDec9B: 45478007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45488007Ssaidi@eecs.umich.edu 45498007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009C) 45508007Ssaidi@eecs.umich.eduCallPal_OpcDec9C: 45518007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45528007Ssaidi@eecs.umich.edu 45538007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009D) 45548007Ssaidi@eecs.umich.eduCallPal_OpcDec9D: 45558007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45568007Ssaidi@eecs.umich.edu 45578007Ssaidi@eecs.umich.edu// .sbttl "rdunique - PALcode for rdunique instruction" 45588007Ssaidi@eecs.umich.edu//+ 45598007Ssaidi@eecs.umich.edu// 45608007Ssaidi@eecs.umich.edu// Entry: 45618007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 45628007Ssaidi@eecs.umich.edu// 45638007Ssaidi@eecs.umich.edu// Function: 45648007Ssaidi@eecs.umich.edu// v0 (r0) <- unique 45658007Ssaidi@eecs.umich.edu// 45668007Ssaidi@eecs.umich.edu//- 45678007Ssaidi@eecs.umich.edu// 45688007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY) 45698007Ssaidi@eecs.umich.eduCALL_PALrdunique_: 45708007Ssaidi@eecs.umich.edu mfpr r0, pt_pcbb // get pcb pointer 45718007Ssaidi@eecs.umich.edu ldqp r0, osfpcb_q_unique(r0) // get new value 45728007Ssaidi@eecs.umich.edu 45738007Ssaidi@eecs.umich.edu hw_rei 45748007Ssaidi@eecs.umich.edu 45758007Ssaidi@eecs.umich.edu// .sbttl "wrunique - PALcode for wrunique instruction" 45768007Ssaidi@eecs.umich.edu//+ 45778007Ssaidi@eecs.umich.edu// 45788007Ssaidi@eecs.umich.edu// Entry: 45798007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 45808007Ssaidi@eecs.umich.edu// 45818007Ssaidi@eecs.umich.edu// Function: 45828007Ssaidi@eecs.umich.edu// unique <- a0 (r16) 45838007Ssaidi@eecs.umich.edu// 45848007Ssaidi@eecs.umich.edu//- 45858007Ssaidi@eecs.umich.edu// 45868007Ssaidi@eecs.umich.eduCALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY) 45878007Ssaidi@eecs.umich.eduCALL_PAL_Wrunique: 45888007Ssaidi@eecs.umich.edu nop 45898007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // get pcb pointer 45908007Ssaidi@eecs.umich.edu stqp r16, osfpcb_q_unique(r12)// get new value 45918007Ssaidi@eecs.umich.edu nop // Pad palshadow write 45928007Ssaidi@eecs.umich.edu hw_rei // back 45938007Ssaidi@eecs.umich.edu 45948007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 45958007Ssaidi@eecs.umich.edu 45968007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A0) 45978007Ssaidi@eecs.umich.eduCallPal_OpcDecA0: 45988007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 45998007Ssaidi@eecs.umich.edu 46008007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A1) 46018007Ssaidi@eecs.umich.eduCallPal_OpcDecA1: 46028007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46038007Ssaidi@eecs.umich.edu 46048007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A2) 46058007Ssaidi@eecs.umich.eduCallPal_OpcDecA2: 46068007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46078007Ssaidi@eecs.umich.edu 46088007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A3) 46098007Ssaidi@eecs.umich.eduCallPal_OpcDecA3: 46108007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46118007Ssaidi@eecs.umich.edu 46128007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A4) 46138007Ssaidi@eecs.umich.eduCallPal_OpcDecA4: 46148007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46158007Ssaidi@eecs.umich.edu 46168007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A5) 46178007Ssaidi@eecs.umich.eduCallPal_OpcDecA5: 46188007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46198007Ssaidi@eecs.umich.edu 46208007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A6) 46218007Ssaidi@eecs.umich.eduCallPal_OpcDecA6: 46228007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46238007Ssaidi@eecs.umich.edu 46248007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A7) 46258007Ssaidi@eecs.umich.eduCallPal_OpcDecA7: 46268007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46278007Ssaidi@eecs.umich.edu 46288007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A8) 46298007Ssaidi@eecs.umich.eduCallPal_OpcDecA8: 46308007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46318007Ssaidi@eecs.umich.edu 46328007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A9) 46338007Ssaidi@eecs.umich.eduCallPal_OpcDecA9: 46348007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46358007Ssaidi@eecs.umich.edu 46368007Ssaidi@eecs.umich.edu 46378007Ssaidi@eecs.umich.edu// .sbttl "gentrap - PALcode for gentrap instruction" 46388007Ssaidi@eecs.umich.edu//+ 46398007Ssaidi@eecs.umich.edu// CALL_PAL_gentrap: 46408007Ssaidi@eecs.umich.edu// Entry: 46418007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 46428007Ssaidi@eecs.umich.edu// 46438007Ssaidi@eecs.umich.edu// Function: 46448007Ssaidi@eecs.umich.edu// Build stack frame 46458007Ssaidi@eecs.umich.edu// a0 <- code 46468007Ssaidi@eecs.umich.edu// a1 <- unpred 46478007Ssaidi@eecs.umich.edu// a2 <- unpred 46488007Ssaidi@eecs.umich.edu// vector via entIF 46498007Ssaidi@eecs.umich.edu// 46508007Ssaidi@eecs.umich.edu//- 46518007Ssaidi@eecs.umich.edu 46528007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AA) 46538007Ssaidi@eecs.umich.edu// unsupported in Hudson code .. pboyle Nov/95 46548007Ssaidi@eecs.umich.eduCALL_PAL_gentrap: 46558007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 46568007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 46578007Ssaidi@eecs.umich.edu 46588007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 46598007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern 46608007Ssaidi@eecs.umich.edu 46618007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 46628007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 46638007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 46648007Ssaidi@eecs.umich.edu 46658007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 46668007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 46678007Ssaidi@eecs.umich.edu 46688007Ssaidi@eecs.umich.eduCALL_PAL_gentrap_10_: 46698007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 46708007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 46718007Ssaidi@eecs.umich.edu 46728007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 46738007Ssaidi@eecs.umich.edu bis r31, osf_a0_gentrap, r16// set a0 46748007Ssaidi@eecs.umich.edu 46758007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 46768007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 46778007Ssaidi@eecs.umich.edu 46788007Ssaidi@eecs.umich.edu 46798007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 46808007Ssaidi@eecs.umich.edu 46818007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AB) 46828007Ssaidi@eecs.umich.eduCallPal_OpcDecAB: 46838007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46848007Ssaidi@eecs.umich.edu 46858007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AC) 46868007Ssaidi@eecs.umich.eduCallPal_OpcDecAC: 46878007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46888007Ssaidi@eecs.umich.edu 46898007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AD) 46908007Ssaidi@eecs.umich.eduCallPal_OpcDecAD: 46918007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46928007Ssaidi@eecs.umich.edu 46938007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AE) 46948007Ssaidi@eecs.umich.eduCallPal_OpcDecAE: 46958007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 46968007Ssaidi@eecs.umich.edu 46978007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AF) 46988007Ssaidi@eecs.umich.eduCallPal_OpcDecAF: 46998007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47008007Ssaidi@eecs.umich.edu 47018007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B0) 47028007Ssaidi@eecs.umich.eduCallPal_OpcDecB0: 47038007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47048007Ssaidi@eecs.umich.edu 47058007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B1) 47068007Ssaidi@eecs.umich.eduCallPal_OpcDecB1: 47078007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47088007Ssaidi@eecs.umich.edu 47098007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B2) 47108007Ssaidi@eecs.umich.eduCallPal_OpcDecB2: 47118007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47128007Ssaidi@eecs.umich.edu 47138007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B3) 47148007Ssaidi@eecs.umich.eduCallPal_OpcDecB3: 47158007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47168007Ssaidi@eecs.umich.edu 47178007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B4) 47188007Ssaidi@eecs.umich.eduCallPal_OpcDecB4: 47198007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47208007Ssaidi@eecs.umich.edu 47218007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B5) 47228007Ssaidi@eecs.umich.eduCallPal_OpcDecB5: 47238007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47248007Ssaidi@eecs.umich.edu 47258007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B6) 47268007Ssaidi@eecs.umich.eduCallPal_OpcDecB6: 47278007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47288007Ssaidi@eecs.umich.edu 47298007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B7) 47308007Ssaidi@eecs.umich.eduCallPal_OpcDecB7: 47318007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47328007Ssaidi@eecs.umich.edu 47338007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B8) 47348007Ssaidi@eecs.umich.eduCallPal_OpcDecB8: 47358007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47368007Ssaidi@eecs.umich.edu 47378007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B9) 47388007Ssaidi@eecs.umich.eduCallPal_OpcDecB9: 47398007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47408007Ssaidi@eecs.umich.edu 47418007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BA) 47428007Ssaidi@eecs.umich.eduCallPal_OpcDecBA: 47438007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47448007Ssaidi@eecs.umich.edu 47458007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BB) 47468007Ssaidi@eecs.umich.eduCallPal_OpcDecBB: 47478007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47488007Ssaidi@eecs.umich.edu 47498007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BC) 47508007Ssaidi@eecs.umich.eduCallPal_OpcDecBC: 47518007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47528007Ssaidi@eecs.umich.edu 47538007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BD) 47548007Ssaidi@eecs.umich.eduCallPal_OpcDecBD: 47558007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47568007Ssaidi@eecs.umich.edu 47578007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BE) 47588007Ssaidi@eecs.umich.eduCallPal_OpcDecBE: 47598007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 47608007Ssaidi@eecs.umich.edu 47618007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BF) 47628007Ssaidi@eecs.umich.eduCallPal_OpcDecBF: 47638007Ssaidi@eecs.umich.edu // MODIFIED BY EGH 2/25/04 47648007Ssaidi@eecs.umich.edu br r31, copypal_impl 47658007Ssaidi@eecs.umich.edu 47668007Ssaidi@eecs.umich.edu 47678007Ssaidi@eecs.umich.edu/*======================================================================*/ 47688007Ssaidi@eecs.umich.edu/* OSF/1 CALL_PAL CONTINUATION AREA */ 47698007Ssaidi@eecs.umich.edu/*======================================================================*/ 47708007Ssaidi@eecs.umich.edu 47718007Ssaidi@eecs.umich.edu .text 2 47728007Ssaidi@eecs.umich.edu 47738007Ssaidi@eecs.umich.edu . = 0x4000 47748007Ssaidi@eecs.umich.edu 47758007Ssaidi@eecs.umich.edu 47768007Ssaidi@eecs.umich.edu// .sbttl "Continuation of MTPR_PERFMON" 47778007Ssaidi@eecs.umich.edu ALIGN_BLOCK 47788007Ssaidi@eecs.umich.edu#if perfmon_debug == 0 47798007Ssaidi@eecs.umich.edu // "real" performance monitoring code 47808007Ssaidi@eecs.umich.edu// mux ctl 47818007Ssaidi@eecs.umich.eduperfmon_muxctl: 47828007Ssaidi@eecs.umich.edu lda r8, 1(r31) // get a 1 47838007Ssaidi@eecs.umich.edu sll r8, pmctr_v_sel0, r8 // move to sel0 position 47848007Ssaidi@eecs.umich.edu or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask 47858007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate pmctr mux select bits 47868007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 47878007Ssaidi@eecs.umich.edu bic r0, r8, r0 // clear old mux select bits 47888007Ssaidi@eecs.umich.edu or r0,r25, r25 // or in new mux select bits 47898007Ssaidi@eecs.umich.edu mtpr r25, ev5__pmctr 47908007Ssaidi@eecs.umich.edu 47918007Ssaidi@eecs.umich.edu // ok, now tackle cbox mux selects 47928007Ssaidi@eecs.umich.edu ldah r14, 0xfff0(r31) 47938007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 47948007Ssaidi@eecs.umich.edu//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword 47958007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 47968007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 47978007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 47988007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16); 47998007Ssaidi@eecs.umich.edu 48008007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) // build mux select mask 48018007Ssaidi@eecs.umich.edu sll r8, bc_ctl_v_pm_mux_sel, r8 48028007Ssaidi@eecs.umich.edu 48038007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate bc_ctl mux select bits 48048007Ssaidi@eecs.umich.edu bic r16, r8, r16 // isolate old mux select bits 48058007Ssaidi@eecs.umich.edu or r16, r25, r25 // create new bc_ctl 48068007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 48078007Ssaidi@eecs.umich.edu stqp r25, ev5__bc_ctl(r14) // store to cbox ipr 48088007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 48098007Ssaidi@eecs.umich.edu 48108007Ssaidi@eecs.umich.edu//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 48118007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 48128007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 48138007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 48148007Ssaidi@eecs.umich.edu SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 48158007Ssaidi@eecs.umich.edu 48168007Ssaidi@eecs.umich.edu br r31, perfmon_success 48178007Ssaidi@eecs.umich.edu 48188007Ssaidi@eecs.umich.edu 48198007Ssaidi@eecs.umich.edu// requested to disable perf monitoring 48208007Ssaidi@eecs.umich.eduperfmon_dis: 48218007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr // read ibox pmctr ipr 48228007Ssaidi@eecs.umich.eduperfmon_dis_ctr0: // and begin with ctr0 48238007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_ctr1 // do not disable ctr0 48248007Ssaidi@eecs.umich.edu lda r8, 3(r31) 48258007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl0, r8 48268007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr0 48278007Ssaidi@eecs.umich.eduperfmon_dis_ctr1: 48288007Ssaidi@eecs.umich.edu srl r17, 1, r17 48298007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_ctr2 // do not disable ctr1 48308007Ssaidi@eecs.umich.edu lda r8, 3(r31) 48318007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl1, r8 48328007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr1 48338007Ssaidi@eecs.umich.eduperfmon_dis_ctr2: 48348007Ssaidi@eecs.umich.edu srl r17, 1, r17 48358007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_update // do not disable ctr2 48368007Ssaidi@eecs.umich.edu lda r8, 3(r31) 48378007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl2, r8 48388007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr2 48398007Ssaidi@eecs.umich.eduperfmon_dis_update: 48408007Ssaidi@eecs.umich.edu mtpr r14, ev5__pmctr // update pmctr ipr 48418007Ssaidi@eecs.umich.edu//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in 48428007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 48438007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25 48448007Ssaidi@eecs.umich.edu mfpr r25, pt_impure 48458007Ssaidi@eecs.umich.edu lda r25, CNS_Q_IPR(r25) 48468007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25); 48478007Ssaidi@eecs.umich.edu 48488007Ssaidi@eecs.umich.edu lda r17, 0x3F(r31) // build mask 48498007Ssaidi@eecs.umich.edu sll r17, pmctr_v_ctl2, r17 // shift mask to correct position 48508007Ssaidi@eecs.umich.edu and r14, r17, r14 // isolate ctl bits 48518007Ssaidi@eecs.umich.edu bic r8, r17, r8 // clear out old ctl bits 48528007Ssaidi@eecs.umich.edu or r14, r8, r14 // create shadow ctl bits 48538007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register 48548007Ssaidi@eecs.umich.edu//adjusted impure pointer still in r25 48558007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25); 48568007Ssaidi@eecs.umich.edu 48578007Ssaidi@eecs.umich.edu br r31, perfmon_success 48588007Ssaidi@eecs.umich.edu 48598007Ssaidi@eecs.umich.edu 48608007Ssaidi@eecs.umich.edu// requested to enable perf monitoring 48618007Ssaidi@eecs.umich.edu//;the following code can be greatly simplified for pass2, but should work fine as is. 48628007Ssaidi@eecs.umich.edu 48638007Ssaidi@eecs.umich.edu 48648007Ssaidi@eecs.umich.eduperfmon_enclr: 48658007Ssaidi@eecs.umich.edu lda r9, 1(r31) // set enclr flag 48668007Ssaidi@eecs.umich.edu br perfmon_en_cont 48678007Ssaidi@eecs.umich.edu 48688007Ssaidi@eecs.umich.eduperfmon_en: 48698007Ssaidi@eecs.umich.edu bis r31, r31, r9 // clear enclr flag 48708007Ssaidi@eecs.umich.edu 48718007Ssaidi@eecs.umich.eduperfmon_en_cont: 48728007Ssaidi@eecs.umich.edu mfpr r8, pt_pcbb // get PCB base 48738007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r25, r25 48748007Ssaidi@eecs.umich.edu mfpr r25, pt_impure 48758007Ssaidi@eecs.umich.edu lda r25, CNS_Q_IPR(r25) 48768007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25); 48778007Ssaidi@eecs.umich.edu 48788007Ssaidi@eecs.umich.edu ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword 48798007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr // read ibox pmctr ipr 48808007Ssaidi@eecs.umich.edu srl r16, osfpcb_v_pme, r16 // get pme bit 48818007Ssaidi@eecs.umich.edu mfpr r13, icsr 48828007Ssaidi@eecs.umich.edu and r16, 1, r16 // isolate pme bit 48838007Ssaidi@eecs.umich.edu 48848007Ssaidi@eecs.umich.edu // this code only needed in pass2 and later 48858007Ssaidi@eecs.umich.edu//orig sget_addr r12, 1<<icsr_v_pmp, r31 48868007Ssaidi@eecs.umich.edu lda r12, 1<<icsr_v_pmp(r31) // pb 48878007Ssaidi@eecs.umich.edu bic r13, r12, r13 // clear pmp bit 48888007Ssaidi@eecs.umich.edu sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position 48898007Ssaidi@eecs.umich.edu or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear 48908007Ssaidi@eecs.umich.edu ev5_pass2 mtpr r13, icsr // update icsr 48918007Ssaidi@eecs.umich.edu 48928007Ssaidi@eecs.umich.edu#if ev5_p1 != 0 48938007Ssaidi@eecs.umich.edu lda r12, 1(r31) 48948007Ssaidi@eecs.umich.edu cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25) 48958007Ssaidi@eecs.umich.edu#else 48968007Ssaidi@eecs.umich.edu bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable) 48978007Ssaidi@eecs.umich.edu#endif 48988007Ssaidi@eecs.umich.edu 48998007Ssaidi@eecs.umich.edu sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions 49008007Ssaidi@eecs.umich.edu bis r14, r31, r13 // copy pmctr 49018007Ssaidi@eecs.umich.edu 49028007Ssaidi@eecs.umich.eduperfmon_en_ctr0: // and begin with ctr0 49038007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_ctr1 // do not enable ctr0 49048007Ssaidi@eecs.umich.edu 49058007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field 49068007Ssaidi@eecs.umich.edu lda r8, 0xffff(r31) 49078007Ssaidi@eecs.umich.edu zapnot r8, 3, r8 // ctr0<15:0> mask 49088007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr0, r8 49098007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 49108007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 49118007Ssaidi@eecs.umich.edu 49128007Ssaidi@eecs.umich.eduperfmon_en_noclr0: 49138007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl0, r31 49148007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl0)) 49158007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr0 49168007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl0 bits in preparation for enabling 49178007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl0 bits 49188007Ssaidi@eecs.umich.edu 49198007Ssaidi@eecs.umich.eduperfmon_en_ctr1: // enable ctr1 49208007Ssaidi@eecs.umich.edu srl r17, 1, r17 // get ctr1 enable 49218007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_ctr2 // do not enable ctr1 49228007Ssaidi@eecs.umich.edu 49238007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field 49248007Ssaidi@eecs.umich.edu lda r8, 0xffff(r31) 49258007Ssaidi@eecs.umich.edu zapnot r8, 3, r8 // ctr1<15:0> mask 49268007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr1, r8 49278007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 49288007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 49298007Ssaidi@eecs.umich.edu 49308007Ssaidi@eecs.umich.eduperfmon_en_noclr1: 49318007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl1, r31 49328007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl1)) 49338007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr1 49348007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl1 bits in preparation for enabling 49358007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl1 bits 49368007Ssaidi@eecs.umich.edu 49378007Ssaidi@eecs.umich.eduperfmon_en_ctr2: // enable ctr2 49388007Ssaidi@eecs.umich.edu srl r17, 1, r17 // get ctr2 enable 49398007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_return // do not enable ctr2 - return 49408007Ssaidi@eecs.umich.edu 49418007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field 49428007Ssaidi@eecs.umich.edu lda r8, 0x3FFF(r31) // ctr2<13:0> mask 49438007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr2, r8 49448007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 49458007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 49468007Ssaidi@eecs.umich.edu 49478007Ssaidi@eecs.umich.eduperfmon_en_noclr2: 49488007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl2, r31 49498007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl2)) 49508007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr2 49518007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl2 bits in preparation for enabling 49528007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl2 bits 49538007Ssaidi@eecs.umich.edu 49548007Ssaidi@eecs.umich.eduperfmon_en_return: 49558007Ssaidi@eecs.umich.edu cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr 49568007Ssaidi@eecs.umich.edu // else only do the counter clears 49578007Ssaidi@eecs.umich.edu mtpr r13, ev5__pmctr // update pmctr ipr 49588007Ssaidi@eecs.umich.edu 49598007Ssaidi@eecs.umich.edu//;this code not needed for pass2 and later, but does not hurt to leave it in 49608007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) 49618007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer 49628007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 49638007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 49648007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12); 49658007Ssaidi@eecs.umich.edu 49668007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl2, r8 // build ctl mask 49678007Ssaidi@eecs.umich.edu and r8, r14, r14 // isolate new ctl bits 49688007Ssaidi@eecs.umich.edu bic r25, r8, r25 // clear out old ctl value 49698007Ssaidi@eecs.umich.edu or r25, r14, r14 // create new pmctr_ctl 49708007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 49718007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 49728007Ssaidi@eecs.umich.edu 49738007Ssaidi@eecs.umich.edu br r31, perfmon_success 49748007Ssaidi@eecs.umich.edu 49758007Ssaidi@eecs.umich.edu 49768007Ssaidi@eecs.umich.edu// options... 49778007Ssaidi@eecs.umich.eduperfmon_ctl: 49788007Ssaidi@eecs.umich.edu 49798007Ssaidi@eecs.umich.edu// set mode 49808007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 49818007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 49828007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 49838007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 49848007Ssaidi@eecs.umich.edu 49858007Ssaidi@eecs.umich.edu//orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register 49868007Ssaidi@eecs.umich.edu LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk))) 49878007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 49888007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate pmctr mode bits 49898007Ssaidi@eecs.umich.edu bic r0, r8, r0 // clear old mode bits 49908007Ssaidi@eecs.umich.edu or r0, r25, r25 // or in new mode bits 49918007Ssaidi@eecs.umich.edu mtpr r25, ev5__pmctr 49928007Ssaidi@eecs.umich.edu 49938007Ssaidi@eecs.umich.edu//;the following code will only be used in pass2, but should not hurt anything if run in pass1. 49948007Ssaidi@eecs.umich.edu mfpr r8, icsr 49958007Ssaidi@eecs.umich.edu lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0 49968007Ssaidi@eecs.umich.edu bic r8, r25, r8 // clear old pma bit 49978007Ssaidi@eecs.umich.edu cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1 49988007Ssaidi@eecs.umich.edu or r8, r25, r8 49998007Ssaidi@eecs.umich.edu ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei 50008007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad icsr write 50018007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad icsr write 50028007Ssaidi@eecs.umich.edu 50038007Ssaidi@eecs.umich.edu//;the following code not needed for pass2 and later, but should work anyway. 50048007Ssaidi@eecs.umich.edu bis r14, 1, r14 // set for select processes 50058007Ssaidi@eecs.umich.edu blbs r17, perfmon_sp // branch if select processes 50068007Ssaidi@eecs.umich.edu bic r14, 1, r14 // all processes 50078007Ssaidi@eecs.umich.eduperfmon_sp: 50088007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 50098007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 50108007Ssaidi@eecs.umich.edu br r31, perfmon_success 50118007Ssaidi@eecs.umich.edu 50128007Ssaidi@eecs.umich.edu// counter frequency select 50138007Ssaidi@eecs.umich.eduperfmon_freq: 50148007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 50158007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 50168007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 50178007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 50188007Ssaidi@eecs.umich.edu 50198007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) 50208007Ssaidi@eecs.umich.edu//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field 50218007Ssaidi@eecs.umich.edu// I guess this should be a shift of 4 bits from the above control register structure .. pb 50228007Ssaidi@eecs.umich.edu#define pmctr_ctl_v_frq2_SHIFT 4 50238007Ssaidi@eecs.umich.edu sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field 50248007Ssaidi@eecs.umich.edu 50258007Ssaidi@eecs.umich.edu and r8, r17, r17 50268007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear out old frequency select bits 50278007Ssaidi@eecs.umich.edu 50288007Ssaidi@eecs.umich.edu or r17, r14, r14 // or in new frequency select info 50298007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 50308007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 50318007Ssaidi@eecs.umich.edu 50328007Ssaidi@eecs.umich.edu br r31, perfmon_success 50338007Ssaidi@eecs.umich.edu 50348007Ssaidi@eecs.umich.edu// read counters 50358007Ssaidi@eecs.umich.eduperfmon_rd: 50368007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 50378007Ssaidi@eecs.umich.edu or r0, 1, r0 // or in return status 50388007Ssaidi@eecs.umich.edu hw_rei // back to user 50398007Ssaidi@eecs.umich.edu 50408007Ssaidi@eecs.umich.edu// write counters 50418007Ssaidi@eecs.umich.eduperfmon_wr: 50428007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr 50438007Ssaidi@eecs.umich.edu lda r8, 0x3FFF(r31) // ctr2<13:0> mask 50448007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr2, r8 50458007Ssaidi@eecs.umich.edu 50468007Ssaidi@eecs.umich.edu//orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask 50478007Ssaidi@eecs.umich.edu LDLI(r9, (0xFFFFFFFF)) 50488007Ssaidi@eecs.umich.edu sll r9, pmctr_v_ctr1, r9 50498007Ssaidi@eecs.umich.edu or r8, r9, r8 // or ctr2, ctr1, ctr0 mask 50508007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr fields 50518007Ssaidi@eecs.umich.edu and r17, r8, r25 // clear all but ctr fields 50528007Ssaidi@eecs.umich.edu or r25, r14, r14 // write ctr fields 50538007Ssaidi@eecs.umich.edu mtpr r14, ev5__pmctr // update pmctr ipr 50548007Ssaidi@eecs.umich.edu 50558007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy) 50568007Ssaidi@eecs.umich.edu 50578007Ssaidi@eecs.umich.eduperfmon_success: 50588007Ssaidi@eecs.umich.edu or r31, 1, r0 // set success 50598007Ssaidi@eecs.umich.edu hw_rei // back to user 50608007Ssaidi@eecs.umich.edu 50618007Ssaidi@eecs.umich.eduperfmon_unknown: 50628007Ssaidi@eecs.umich.edu or r31, r31, r0 // set fail 50638007Ssaidi@eecs.umich.edu hw_rei // back to user 50648007Ssaidi@eecs.umich.edu 50658007Ssaidi@eecs.umich.edu#else 50668007Ssaidi@eecs.umich.edu 50678007Ssaidi@eecs.umich.edu// end of "real code", start of debug code 50688007Ssaidi@eecs.umich.edu 50698007Ssaidi@eecs.umich.edu//+ 50708007Ssaidi@eecs.umich.edu// Debug environment: 50718007Ssaidi@eecs.umich.edu// (in pass2, always set icsr<pma> to ensure master counter enable is on) 50728007Ssaidi@eecs.umich.edu// R16 = 0 Write to on-chip performance monitor ipr 50738007Ssaidi@eecs.umich.edu// r17 = on-chip ipr 50748007Ssaidi@eecs.umich.edu// r0 = return value of read of on-chip performance monitor ipr 50758007Ssaidi@eecs.umich.edu// R16 = 1 Setup Cbox mux selects 50768007Ssaidi@eecs.umich.edu// r17 = Cbox mux selects in same position as in bc_ctl ipr. 50778007Ssaidi@eecs.umich.edu// r0 = return value of read of on-chip performance monitor ipr 50788007Ssaidi@eecs.umich.edu// 50798007Ssaidi@eecs.umich.edu//- 50808007Ssaidi@eecs.umich.edupal_perfmon_debug: 50818007Ssaidi@eecs.umich.edu mfpr r8, icsr 50828007Ssaidi@eecs.umich.edu lda r9, 1<<icsr_v_pma(r31) 50838007Ssaidi@eecs.umich.edu bis r8, r9, r8 50848007Ssaidi@eecs.umich.edu mtpr r8, icsr 50858007Ssaidi@eecs.umich.edu 50868007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr // read old value 50878007Ssaidi@eecs.umich.edu bne r16, cbox_mux_sel 50888007Ssaidi@eecs.umich.edu 50898007Ssaidi@eecs.umich.edu mtpr r17, ev5__pmctr // update pmctr ipr 50908007Ssaidi@eecs.umich.edu br r31, end_pm 50918007Ssaidi@eecs.umich.edu 50928007Ssaidi@eecs.umich.educbox_mux_sel: 50938007Ssaidi@eecs.umich.edu // ok, now tackle cbox mux selects 50948007Ssaidi@eecs.umich.edu ldah r14, 0xfff0(r31) 50958007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 50968007Ssaidi@eecs.umich.edu//orig get_bc_ctl_shadow r16 // bc_ctl returned 50978007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 50988007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 50998007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16); 51008007Ssaidi@eecs.umich.edu 51018007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) // build mux select mask 51028007Ssaidi@eecs.umich.edu sll r8, BC_CTL_V_PM_MUX_SEL, r8 51038007Ssaidi@eecs.umich.edu 51048007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate bc_ctl mux select bits 51058007Ssaidi@eecs.umich.edu bic r16, r8, r16 // isolate old mux select bits 51068007Ssaidi@eecs.umich.edu or r16, r25, r25 // create new bc_ctl 51078007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 51088007Ssaidi@eecs.umich.edu stqp r25, ev5__bc_ctl(r14) // store to cbox ipr 51098007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 51108007Ssaidi@eecs.umich.edu//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 51118007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 51128007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 51138007Ssaidi@eecs.umich.edu SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 51148007Ssaidi@eecs.umich.edu 51158007Ssaidi@eecs.umich.eduend_pm: hw_rei 51168007Ssaidi@eecs.umich.edu 51178007Ssaidi@eecs.umich.edu#endif 51188007Ssaidi@eecs.umich.edu 51198007Ssaidi@eecs.umich.edu 51208007Ssaidi@eecs.umich.edu//;The following code is a workaround for a cpu bug where Istream prefetches to 51218007Ssaidi@eecs.umich.edu//;super-page address space in user mode may escape off-chip. 51228007Ssaidi@eecs.umich.edu#if spe_fix != 0 51238007Ssaidi@eecs.umich.edu 51248007Ssaidi@eecs.umich.edu ALIGN_BLOCK 51258007Ssaidi@eecs.umich.eduhw_rei_update_spe: 51268007Ssaidi@eecs.umich.edu mfpr r12, pt_misc // get previous mode 51278007Ssaidi@eecs.umich.edu srl r11, osfps_v_mode, r10 // isolate current mode bit 51288007Ssaidi@eecs.umich.edu and r10, 1, r10 51298007Ssaidi@eecs.umich.edu extbl r12, 7, r8 // get previous mode field 51308007Ssaidi@eecs.umich.edu and r8, 1, r8 // isolate previous mode bit 51318007Ssaidi@eecs.umich.edu cmpeq r10, r8, r8 // compare previous and current modes 51328007Ssaidi@eecs.umich.edu beq r8, hw_rei_update_spe_5_ 51338007Ssaidi@eecs.umich.edu hw_rei // if same, just return 51348007Ssaidi@eecs.umich.edu 51358007Ssaidi@eecs.umich.eduhw_rei_update_spe_5_: 51368007Ssaidi@eecs.umich.edu 51378007Ssaidi@eecs.umich.edu#if fill_err_hack != 0 51388007Ssaidi@eecs.umich.edu 51398007Ssaidi@eecs.umich.edu fill_error_hack 51408007Ssaidi@eecs.umich.edu#endif 51418007Ssaidi@eecs.umich.edu 51428007Ssaidi@eecs.umich.edu mfpr r8, icsr // get current icsr value 51438007Ssaidi@eecs.umich.edu ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask 51448007Ssaidi@eecs.umich.edu bic r8, r9, r8 // disable spe 51458007Ssaidi@eecs.umich.edu xor r10, 1, r9 // flip mode for new spe bit 51468007Ssaidi@eecs.umich.edu sll r9, icsr_v_spe+1, r9 // shift into position 51478007Ssaidi@eecs.umich.edu bis r8, r9, r8 // enable/disable spe 51488007Ssaidi@eecs.umich.edu lda r9, 1(r31) // now update our flag 51498007Ssaidi@eecs.umich.edu sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask 51508007Ssaidi@eecs.umich.edu bic r12, r9, r12 // clear saved previous mode 51518007Ssaidi@eecs.umich.edu sll r10, pt_misc_v_cm, r9 // current mode saved bit mask 51528007Ssaidi@eecs.umich.edu bis r12, r9, r12 // set saved current mode 51538007Ssaidi@eecs.umich.edu mtpr r12, pt_misc // update pt_misc 51548007Ssaidi@eecs.umich.edu mtpr r8, icsr // update icsr 51558007Ssaidi@eecs.umich.edu 51568007Ssaidi@eecs.umich.edu#if osf_chm_fix != 0 51578007Ssaidi@eecs.umich.edu 51588007Ssaidi@eecs.umich.edu 51598007Ssaidi@eecs.umich.edu blbc r10, hw_rei_update_spe_10_ // branch if not user mode 51608007Ssaidi@eecs.umich.edu 51618007Ssaidi@eecs.umich.edu mb // ensure no outstanding fills 51628007Ssaidi@eecs.umich.edu lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode 51638007Ssaidi@eecs.umich.edu mtpr r12, dc_mode // Turn on dcache 51648007Ssaidi@eecs.umich.edu mtpr r31, dc_flush // and flush it 51658007Ssaidi@eecs.umich.edu br r31, pal_ic_flush 51668007Ssaidi@eecs.umich.edu 51678007Ssaidi@eecs.umich.eduhw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode 51688007Ssaidi@eecs.umich.edu ldqp r9, osfpcb_q_Fen(r9) // get FEN 51698007Ssaidi@eecs.umich.edu blbc r9, pal_ic_flush // return if FP disabled 51708007Ssaidi@eecs.umich.edu mb // ensure no outstanding fills 51718007Ssaidi@eecs.umich.edu mtpr r31, dc_mode // turn off dcache 51728007Ssaidi@eecs.umich.edu#endif 51738007Ssaidi@eecs.umich.edu 51748007Ssaidi@eecs.umich.edu 51758007Ssaidi@eecs.umich.edu br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE> 51768007Ssaidi@eecs.umich.edu#endif 51778007Ssaidi@eecs.umich.edu 51788007Ssaidi@eecs.umich.edu 51798007Ssaidi@eecs.umich.educopypal_impl: 51808007Ssaidi@eecs.umich.edu mov r16, r0 51818007Ssaidi@eecs.umich.edu ble r18, finished #if len <=0 we are finished 51828007Ssaidi@eecs.umich.edu ldq_u r8, 0(r17) 51838007Ssaidi@eecs.umich.edu xor r17, r16, r9 51848007Ssaidi@eecs.umich.edu and r9, 7, r9 51858007Ssaidi@eecs.umich.edu and r16, 7, r10 51868007Ssaidi@eecs.umich.edu bne r9, unaligned 51878007Ssaidi@eecs.umich.edu beq r10, aligned 51888007Ssaidi@eecs.umich.edu ldq_u r9, 0(r16) 51898007Ssaidi@eecs.umich.edu addq r18, r10, r18 51908007Ssaidi@eecs.umich.edu mskqh r8, r17, r8 51918007Ssaidi@eecs.umich.edu mskql r9, r17, r9 51928007Ssaidi@eecs.umich.edu bis r8, r9, r8 51938007Ssaidi@eecs.umich.edualigned: 51948007Ssaidi@eecs.umich.edu subq r18, 1, r10 51958007Ssaidi@eecs.umich.edu bic r10, 7, r10 51968007Ssaidi@eecs.umich.edu and r18, 7, r18 51978007Ssaidi@eecs.umich.edu beq r10, aligned_done 51988007Ssaidi@eecs.umich.eduloop: 51998007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 52008007Ssaidi@eecs.umich.edu ldq_u r8, 8(r17) 52018007Ssaidi@eecs.umich.edu subq r10, 8, r10 52028007Ssaidi@eecs.umich.edu lda r16,8(r16) 52038007Ssaidi@eecs.umich.edu lda r17,8(r17) 52048007Ssaidi@eecs.umich.edu bne r10, loop 52058007Ssaidi@eecs.umich.edualigned_done: 52068007Ssaidi@eecs.umich.edu bne r18, few_left 52078007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 52088007Ssaidi@eecs.umich.edu br r31, finished 52098007Ssaidi@eecs.umich.edu few_left: 52108007Ssaidi@eecs.umich.edu mskql r8, r18, r10 52118007Ssaidi@eecs.umich.edu ldq_u r9, 0(r16) 52128007Ssaidi@eecs.umich.edu mskqh r9, r18, r9 52138007Ssaidi@eecs.umich.edu bis r10, r9, r10 52148007Ssaidi@eecs.umich.edu stq_u r10, 0(r16) 52158007Ssaidi@eecs.umich.edu br r31, finished 52168007Ssaidi@eecs.umich.eduunaligned: 52178007Ssaidi@eecs.umich.edu addq r17, r18, r25 52188007Ssaidi@eecs.umich.edu cmpule r18, 8, r9 52198007Ssaidi@eecs.umich.edu bne r9, unaligned_few_left 52208007Ssaidi@eecs.umich.edu beq r10, unaligned_dest_aligned 52218007Ssaidi@eecs.umich.edu and r16, 7, r10 52228007Ssaidi@eecs.umich.edu subq r31, r10, r10 52238007Ssaidi@eecs.umich.edu addq r10, 8, r10 52248007Ssaidi@eecs.umich.edu ldq_u r9, 7(r17) 52258007Ssaidi@eecs.umich.edu extql r8, r17, r8 52268007Ssaidi@eecs.umich.edu extqh r9, r17, r9 52278007Ssaidi@eecs.umich.edu bis r8, r9, r12 52288007Ssaidi@eecs.umich.edu insql r12, r16, r12 52298007Ssaidi@eecs.umich.edu ldq_u r13, 0(r16) 52308007Ssaidi@eecs.umich.edu mskql r13, r16, r13 52318007Ssaidi@eecs.umich.edu bis r12, r13, r12 52328007Ssaidi@eecs.umich.edu stq_u r12, 0(r16) 52338007Ssaidi@eecs.umich.edu addq r16, r10, r16 52348007Ssaidi@eecs.umich.edu addq r17, r10, r17 52358007Ssaidi@eecs.umich.edu subq r18, r10, r18 52368007Ssaidi@eecs.umich.edu ldq_u r8, 0(r17) 52378007Ssaidi@eecs.umich.eduunaligned_dest_aligned: 52388007Ssaidi@eecs.umich.edu subq r18, 1, r10 52398007Ssaidi@eecs.umich.edu bic r10, 7, r10 52408007Ssaidi@eecs.umich.edu and r18, 7, r18 52418007Ssaidi@eecs.umich.edu beq r10, unaligned_partial_left 52428007Ssaidi@eecs.umich.eduunaligned_loop: 52438007Ssaidi@eecs.umich.edu ldq_u r9, 7(r17) 52448007Ssaidi@eecs.umich.edu lda r17, 8(r17) 52458007Ssaidi@eecs.umich.edu extql r8, r17, r12 52468007Ssaidi@eecs.umich.edu extqh r9, r17, r13 52478007Ssaidi@eecs.umich.edu subq r10, 8, r10 52488007Ssaidi@eecs.umich.edu bis r12, r13, r13 52498007Ssaidi@eecs.umich.edu stq r13, 0(r16) 52508007Ssaidi@eecs.umich.edu lda r16, 8(r16) 52518007Ssaidi@eecs.umich.edu beq r10, unaligned_second_partial_left 52528007Ssaidi@eecs.umich.edu ldq_u r8, 7(r17) 52538007Ssaidi@eecs.umich.edu lda r17, 8(r17) 52548007Ssaidi@eecs.umich.edu extql r9, r17, r12 52558007Ssaidi@eecs.umich.edu extqh r8, r17, r13 52568007Ssaidi@eecs.umich.edu bis r12, r13, r13 52578007Ssaidi@eecs.umich.edu subq r10, 8, r10 52588007Ssaidi@eecs.umich.edu stq r13, 0(r16) 52598007Ssaidi@eecs.umich.edu lda r16, 8(r16) 52608007Ssaidi@eecs.umich.edu bne r10, unaligned_loop 52618007Ssaidi@eecs.umich.eduunaligned_partial_left: 52628007Ssaidi@eecs.umich.edu mov r8, r9 52638007Ssaidi@eecs.umich.eduunaligned_second_partial_left: 52648007Ssaidi@eecs.umich.edu ldq_u r8, -1(r25) 52658007Ssaidi@eecs.umich.edu extql r9, r17, r9 52668007Ssaidi@eecs.umich.edu extqh r8, r17, r8 52678007Ssaidi@eecs.umich.edu bis r8, r9, r8 52688007Ssaidi@eecs.umich.edu bne r18, few_left 52698007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 52708007Ssaidi@eecs.umich.edu br r31, finished 52718007Ssaidi@eecs.umich.eduunaligned_few_left: 52728007Ssaidi@eecs.umich.edu ldq_u r9, -1(r25) 52738007Ssaidi@eecs.umich.edu extql r8, r17, r8 52748007Ssaidi@eecs.umich.edu extqh r9, r17, r9 52758007Ssaidi@eecs.umich.edu bis r8, r9, r8 52768007Ssaidi@eecs.umich.edu insqh r8, r16, r9 52778007Ssaidi@eecs.umich.edu insql r8, r16, r8 52788007Ssaidi@eecs.umich.edu lda r12, -1(r31) 52798007Ssaidi@eecs.umich.edu mskql r12, r18, r13 52808007Ssaidi@eecs.umich.edu cmovne r13, r13, r12 52818007Ssaidi@eecs.umich.edu insqh r12, r16, r13 52828007Ssaidi@eecs.umich.edu insql r12, r16, r12 52838007Ssaidi@eecs.umich.edu addq r16, r18, r10 52848007Ssaidi@eecs.umich.edu ldq_u r14, 0(r16) 52858007Ssaidi@eecs.umich.edu ldq_u r25, -1(r10) 52868007Ssaidi@eecs.umich.edu bic r14, r12, r14 52878007Ssaidi@eecs.umich.edu bic r25, r13, r25 52888007Ssaidi@eecs.umich.edu and r8, r12, r8 52898007Ssaidi@eecs.umich.edu and r9, r13, r9 52908007Ssaidi@eecs.umich.edu bis r8, r14, r8 52918007Ssaidi@eecs.umich.edu bis r9, r25, r9 52928007Ssaidi@eecs.umich.edu stq_u r9, -1(r10) 52938007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 52948007Ssaidi@eecs.umich.edufinished: 52958007Ssaidi@eecs.umich.edu hw_rei 5296