fromHudsonOsf.h revision 8029:442f90a944eb
1/* 2 * Copyright (c) 1993-1994 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef FROMHUDSONOSF_INCLUDED 30#define FROMHUDSONOSF_INCLUDED 1 31 32#define __OSF_LOADED 1 33/* 34** Seg0 and Seg1 Virtual Address (VA) Format 35** 36** Loc Size Name Function 37** ----- ---- ---- --------------------------------- 38** <42:33> 10 SEG1 First level page table offset 39** <32:23> 10 SEG2 Second level page table offset 40** <22:13> 10 SEG3 Third level page table offset 41** <12:00> 13 OFFSET Byte within page offset 42*/ 43 44#define VA_V_SEG1 33 45#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) 46#define VA_V_SEG2 23 47#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) 48#define VA_V_SEG3 13 49#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) 50#define VA_V_OFFSET 0 51#define VA_M_OFFSET 0x1FFF 52 53/* 54** Virtual Address Options: 8K byte page size 55*/ 56 57#define VA_S_SIZE 43 58#define VA_S_OFF 13 59#define va_s_off 13 60#define VA_S_SEG 10 61#define VA_S_PAGE_SIZE 8192 62 63/* 64** Page Table Entry (PTE) Format 65** 66** Extent Size Name Function 67** ------ ---- ---- --------------------------------- 68** <63:32> 32 PFN Page Frame Number 69** <31:16> 16 SW Reserved for software 70** <15:14> 2 RSV0 Reserved for hardware SBZ 71** <13> 1 UWE User Write Enable 72** <12> 1 KWE Kernel Write Enable 73** <11:10> 2 RSV1 Reserved for hardware SBZ 74** <9> 1 URE User Read Enable 75** <8> 1 KRE Kernel Read Enable 76** <7> 1 RSV2 Reserved for hardware SBZ 77** <6:5> 2 GH Granularity Hint 78** <4> 1 ASM Address Space Match 79** <3> 1 FOE Fault On Execute 80** <2> 1 FOW Fault On Write 81** <1> 1 FOR Fault On Read 82** <0> 1 V Valid 83*/ 84 85#define PTE_V_PFN 32 86#define PTE_M_PFN 0xFFFFFFFF00000000 87#define PTE_V_SW 16 88#define PTE_M_SW 0x00000000FFFF0000 89#define PTE_V_UWE 13 90#define PTE_M_UWE (1<<PTE_V_UWE) 91#define PTE_V_KWE 12 92#define PTE_M_KWE (1<<PTE_V_KWE) 93#define PTE_V_URE 9 94#define PTE_M_URE (1<<PTE_V_URE) 95#define PTE_V_KRE 8 96#define PTE_M_KRE (1<<PTE_V_KRE) 97#define PTE_V_GH 5 98#define PTE_M_GH (3<<PTE_V_GH) 99#define PTE_V_ASM 4 100#define PTE_M_ASM (1<<PTE_V_ASM) 101#define PTE_V_FOE 3 102#define PTE_M_FOE (1<<PTE_V_FOE) 103#define PTE_V_FOW 2 104#define PTE_M_FOW (1<<PTE_V_FOW) 105#define PTE_V_FOR 1 106#define PTE_M_FOR (1<<PTE_V_FOR) 107#define PTE_V_VALID 0 108#define PTE_M_VALID (1<<PTE_V_VALID) 109 110#define PTE_M_KSEG 0x1111 111#define PTE_M_PROT 0x3300 112#define pte_m_prot 0x3300 113 114/* 115** System Entry Instruction Fault (entIF) Constants: 116*/ 117 118#define IF_K_BPT 0x0 119#define IF_K_BUGCHK 0x1 120#define IF_K_GENTRAP 0x2 121#define IF_K_FEN 0x3 122#define IF_K_OPCDEC 0x4 123 124/* 125** System Entry Hardware Interrupt (entInt) Constants: 126*/ 127 128#define INT_K_IP 0x0 129#define INT_K_CLK 0x1 130#define INT_K_MCHK 0x2 131#define INT_K_DEV 0x3 132#define INT_K_PERF 0x4 133 134/* 135** System Entry MM Fault (entMM) Constants: 136*/ 137 138#define MM_K_TNV 0x0 139#define MM_K_ACV 0x1 140#define MM_K_FOR 0x2 141#define MM_K_FOE 0x3 142#define MM_K_FOW 0x4 143 144/* 145** Process Control Block (PCB) Offsets: 146*/ 147 148#define PCB_Q_KSP 0x0000 149#define PCB_Q_USP 0x0008 150#define PCB_Q_PTBR 0x0010 151#define PCB_L_PCC 0x0018 152#define PCB_L_ASN 0x001C 153#define PCB_Q_UNIQUE 0x0020 154#define PCB_Q_FEN 0x0028 155#define PCB_Q_RSV0 0x0030 156#define PCB_Q_RSV1 0x0038 157 158/* 159** Processor Status Register (PS) Bit Summary 160** 161** Extent Size Name Function 162** ------ ---- ---- --------------------------------- 163** <3> 1 CM Current Mode 164** <2:0> 3 IPL Interrupt Priority Level 165**/ 166 167#define PS_V_CM 3 168#define PS_M_CM (1<<PS_V_CM) 169#define PS_V_IPL 0 170#define PS_M_IPL (7<<PS_V_IPL) 171 172#define PS_K_KERN (0<<PS_V_CM) 173#define PS_K_USER (1<<PS_V_CM) 174 175#define IPL_K_ZERO 0x0 176#define IPL_K_SW0 0x1 177#define IPL_K_SW1 0x2 178#define IPL_K_DEV0 0x3 179#define IPL_K_DEV1 0x4 180#define IPL_K_CLK 0x5 181#define IPL_K_RT 0x6 182#define IPL_K_PERF 0x6 183#define IPL_K_PFAIL 0x6 184#define IPL_K_MCHK 0x7 185 186#define IPL_K_LOW 0x0 187#define IPL_K_HIGH 0x7 188 189/* 190** SCB Offset Definitions: 191*/ 192 193#define SCB_Q_FEN 0x0010 194#define SCB_Q_ACV 0x0080 195#define SCB_Q_TNV 0x0090 196#define SCB_Q_FOR 0x00A0 197#define SCB_Q_FOW 0x00B0 198#define SCB_Q_FOE 0x00C0 199#define SCB_Q_ARITH 0x0200 200#define SCB_Q_KAST 0x0240 201#define SCB_Q_EAST 0x0250 202#define SCB_Q_SAST 0x0260 203#define SCB_Q_UAST 0x0270 204#define SCB_Q_UNALIGN 0x0280 205#define SCB_Q_BPT 0x0400 206#define SCB_Q_BUGCHK 0x0410 207#define SCB_Q_OPCDEC 0x0420 208#define SCB_Q_ILLPAL 0x0430 209#define SCB_Q_TRAP 0x0440 210#define SCB_Q_CHMK 0x0480 211#define SCB_Q_CHME 0x0490 212#define SCB_Q_CHMS 0x04A0 213#define SCB_Q_CHMU 0x04B0 214#define SCB_Q_SW0 0x0500 215#define SCB_Q_SW1 0x0510 216#define SCB_Q_SW2 0x0520 217#define SCB_Q_SW3 0x0530 218#define SCB_Q_SW4 0x0540 219#define SCB_Q_SW5 0x0550 220#define SCB_Q_SW6 0x0560 221#define SCB_Q_SW7 0x0570 222#define SCB_Q_SW8 0x0580 223#define SCB_Q_SW9 0x0590 224#define SCB_Q_SW10 0x05A0 225#define SCB_Q_SW11 0x05B0 226#define SCB_Q_SW12 0x05C0 227#define SCB_Q_SW13 0x05D0 228#define SCB_Q_SW14 0x05E0 229#define SCB_Q_SW15 0x05F0 230#define SCB_Q_CLOCK 0x0600 231#define SCB_Q_INTER 0x0610 232#define SCB_Q_SYSERR 0x0620 233#define SCB_Q_PROCERR 0x0630 234#define SCB_Q_PWRFAIL 0x0640 235#define SCB_Q_PERFMON 0x0650 236#define SCB_Q_SYSMCHK 0x0660 237#define SCB_Q_PROCMCHK 0x0670 238#define SCB_Q_PASSREL 0x0680 239 240/* 241** Stack Frame (FRM) Offsets: 242** 243** There are two types of system entries for OSF/1 - those for the 244** callsys CALL_PAL function and those for exceptions and interrupts. 245** Both entry types use the same stack frame layout. The stack frame 246** contains space for the PC, the PS, the saved GP, and the saved 247** argument registers a0, a1, and a2. On entry, SP points to the 248** saved PS. 249*/ 250 251#define FRM_Q_PS 0x0000 252#define FRM_Q_PC 0x0008 253#define FRM_Q_GP 0x0010 254#define FRM_Q_A0 0x0018 255#define FRM_Q_A1 0x0020 256#define FRM_Q_A2 0x0028 257 258#define FRM_K_SIZE 48 259 260#define STACK_FRAME(tmp1,tmp2) \ 261 sll ps, 63-PS_V_CM, p7; \ 262 bge p7, 0f; \ 263 bis zero, zero, ps; \ 264 mtpr sp, ptUsp; \ 265 mfpr sp, ptKsp; \ 2660: lda sp, 0-FRM_K_SIZE(sp); \ 267 stq tmp1, FRM_Q_PS(sp); \ 268 stq tmp2, FRM_Q_PC(sp); \ 269 stq gp, FRM_Q_GP(sp); \ 270 stq a0, FRM_Q_A0(sp); \ 271 stq a1, FRM_Q_A1(sp); \ 272 stq a2, FRM_Q_A2(sp) 273 274/* 275** Halt Codes: 276*/ 277 278#define HLT_K_RESET 0x0000 279#define HLT_K_HW_HALT 0x0001 280#define HLT_K_KSP_INVAL 0x0002 281#define HLT_K_SCBB_INVAL 0x0003 282#define HLT_K_PTBR_INVAL 0x0004 283#define HLT_K_SW_HALT 0x0005 284#define HLT_K_DBL_MCHK 0x0006 285#define HLT_K_MCHK_FROM_PAL 0x0007 286 287/* 288** Machine Check Codes: 289*/ 290 291#define MCHK_K_TPERR 0x0080 292#define MCHK_K_TCPERR 0x0082 293#define MCHK_K_HERR 0x0084 294#define MCHK_K_ECC_C 0x0086 295#define MCHK_K_ECC_NC 0x0088 296#define MCHK_K_UNKNOWN 0x008A 297#define MCHK_K_CACKSOFT 0x008C 298#define MCHK_K_BUGCHECK 0x008E 299#define MCHK_K_OS_BUGCHECK 0x0090 300#define MCHK_K_DCPERR 0x0092 301#define MCHK_K_ICPERR 0x0094 302#define MCHK_K_RETRY_IRD 0x0096 303#define MCHK_K_PROC_HERR 0x0098 304 305/* 306** System Machine Check Codes: 307*/ 308 309#define MCHK_K_READ_NXM 0x0200 310#define MCHK_K_SYS_HERR 0x0202 311 312/* 313** Machine Check Error Status Summary (MCES) Register Format 314** 315** Extent Size Name Function 316** ------ ---- ---- --------------------------------- 317** <0> 1 MIP Machine check in progress 318** <1> 1 SCE System correctable error in progress 319** <2> 1 PCE Processor correctable error in progress 320** <3> 1 DPC Disable PCE error reporting 321** <4> 1 DSC Disable SCE error reporting 322*/ 323 324#define MCES_V_MIP 0 325#define MCES_M_MIP (1<<MCES_V_MIP) 326#define MCES_V_SCE 1 327#define MCES_M_SCE (1<<MCES_V_SCE) 328#define MCES_V_PCE 2 329#define MCES_M_PCE (1<<MCES_V_PCE) 330#define MCES_V_DPC 3 331#define MCES_M_DPC (1<<MCES_V_DPC) 332#define MCES_V_DSC 4 333#define MCES_M_DSC (1<<MCES_V_DSC) 334 335#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ 336 | MCES_M_DSC) 337 338/* 339** Who-Am-I (WHAMI) Register Format 340** 341** Extent Size Name Function 342** ------ ---- ---- --------------------------------- 343** <7:0> 8 ID Who-Am-I identifier 344** <15:8> 1 SWAP Swap PALcode flag - character 'S' 345*/ 346 347#define WHAMI_V_SWAP 8 348#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) 349#define WHAMI_V_ID 0 350#define WHAMI_M_ID 0xFF 351 352#define WHAMI_K_SWAP 0x53 /* Character 'S' */ 353 354/* 355** Conventional Register Usage Definitions 356** 357** Assembler temporary `at' is `AT' so it doesn't conflict with the 358** `.set at' assembler directive. 359*/ 360 361#define v0 $0 /* Function Return Value Register */ 362#define t0 $1 /* Scratch (Temporary) Registers ... */ 363#define t1 $2 364#define t2 $3 365#define t3 $4 366#define t4 $5 367#define t5 $6 368#define t6 $7 369#define t7 $8 370#define s0 $9 /* Saved (Non-Volatile) Registers ... */ 371#define s1 $10 372#define s2 $11 373#define s3 $12 374#define s4 $13 375#define s5 $14 376#define fp $15 /* Frame Pointer Register, Or S6 */ 377#define s6 $15 378#define a0 $16 /* Argument Registers ... */ 379#define a1 $17 380#define a2 $18 381#define a3 $19 382#define a4 $20 383#define a5 $21 384#define t8 $22 /* Scratch (Temporary) Registers ... */ 385#define t9 $23 386#define t10 $24 387#define t11 $25 388#define ra $26 /* Return Address Register */ 389#define pv $27 /* Procedure Value Register, Or T12 */ 390#define t12 $27 391#define AT $28 /* Assembler Temporary (Volatile) Register */ 392#define gp $29 /* Global Pointer Register */ 393#define sp $30 /* Stack Pointer Register */ 394#define zero $31 /* Zero Register */ 395 396/* 397** OSF/1 Unprivileged CALL_PAL Entry Offsets: 398** 399** Entry Name Offset (Hex) 400** 401** bpt 0080 402** bugchk 0081 403** callsys 0083 404** imb 0086 405** rdunique 009E 406** wrunique 009F 407** gentrap 00AA 408** dbgstop 00AD 409*/ 410 411#define UNPRIV 0x80 412#define PAL_BPT_ENTRY 0x80 413#define PAL_BUGCHK_ENTRY 0x81 414#define PAL_CALLSYS_ENTRY 0x83 415#define PAL_IMB_ENTRY 0x86 416#define PAL_RDUNIQUE_ENTRY 0x9E 417#define PAL_WRUNIQUE_ENTRY 0x9F 418#define PAL_GENTRAP_ENTRY 0xAA 419 420#if defined(KDEBUG) 421#define PAL_DBGSTOP_ENTRY 0xAD 422/* #define NUM_UNPRIV_CALL_PALS 10 */ 423#else 424/* #define NUM_UNPRIV_CALL_PALS 9 */ 425#endif /* KDEBUG */ 426 427/* 428** OSF/1 Privileged CALL_PAL Entry Offsets: 429** 430** Entry Name Offset (Hex) 431** 432** halt 0000 433** cflush 0001 434** draina 0002 435** cserve 0009 436** swppal 000A 437** rdmces 0010 438** wrmces 0011 439** wrfen 002B 440** wrvptptr 002D 441** swpctx 0030 442** wrval 0031 443** rdval 0032 444** tbi 0033 445** wrent 0034 446** swpipl 0035 447** rdps 0036 448** wrkgp 0037 449** wrusp 0038 450** rdusp 003A 451** whami 003C 452** retsys 003D 453** rti 003F 454*/ 455 456#define PAL_HALT_ENTRY 0x0000 457#define PAL_CFLUSH_ENTRY 0x0001 458#define PAL_DRAINA_ENTRY 0x0002 459#define PAL_CSERVE_ENTRY 0x0009 460#define PAL_SWPPAL_ENTRY 0x000A 461#define PAL_WRIPIR_ENTRY 0x000D 462#define PAL_RDMCES_ENTRY 0x0010 463#define PAL_WRMCES_ENTRY 0x0011 464#define PAL_WRFEN_ENTRY 0x002B 465#define PAL_WRVPTPTR_ENTRY 0x002D 466#define PAL_SWPCTX_ENTRY 0x0030 467#define PAL_WRVAL_ENTRY 0x0031 468#define PAL_RDVAL_ENTRY 0x0032 469#define PAL_TBI_ENTRY 0x0033 470#define PAL_WRENT_ENTRY 0x0034 471#define PAL_SWPIPL_ENTRY 0x0035 472#define PAL_RDPS_ENTRY 0x0036 473#define PAL_WRKGP_ENTRY 0x0037 474#define PAL_WRUSP_ENTRY 0x0038 475#define PAL_RDUSP_ENTRY 0x003A 476#define PAL_WHAMI_ENTRY 0x003C 477#define PAL_RETSYS_ENTRY 0x003D 478#define PAL_RTI_ENTRY 0x003F 479 480#define NUM_PRIV_CALL_PALS 23 481 482#endif 483 484