fromHudsonOsf.h revision 8012:2f71125bf413
1/* 2Copyright 1993, 1994 Hewlett-Packard Development Company, L.P. 3 4Permission is hereby granted, free of charge, to any person obtaining a copy of 5this software and associated documentation files (the "Software"), to deal in 6the Software without restriction, including without limitation the rights to 7use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 8of the Software, and to permit persons to whom the Software is furnished to do 9so, subject to the following conditions: 10 11The above copyright notice and this permission notice shall be included in all 12copies or substantial portions of the Software. 13 14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20SOFTWARE. 21*/ 22 23#ifndef FROMHUDSONOSF_INCLUDED 24#define FROMHUDSONOSF_INCLUDED 1 25/* 26 * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] 27 * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] 28 */ 29#define __OSF_LOADED 1 30/* 31** 32** FACILITY: 33** 34** DECchip 21164 PALcode 35** 36** MODULE: 37** 38** osf.h 39** 40** MODULE DESCRIPTION: 41** 42** OSF/1 specific definitions 43** 44** AUTHOR: ER 45** 46** CREATION DATE: 24-Nov-1993 47** 48** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 49** 50** MODIFICATION HISTORY: 51** 52** $Log: fromHudsonOsf.h,v $ 53** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 54** current 10/29/97 55** 56** Revision 1.1 1995/11/18 01:46:31 boyle 57** Initial revision 58** 59** Revision 1.11 1995/04/21 02:06:30 fdh 60** Replaced C++ style comments with Standard C style comments. 61** 62** Revision 1.10 1994/09/26 14:17:47 samberg 63** Complete VICE work and EB164/SD164 breakout. 64** 65** Revision 1.9 1994/07/26 17:39:10 samberg 66** Changes for SD164. 67** 68** Revision 1.8 1994/07/08 17:03:48 samberg 69** Changes to support platform specific additions 70** 71** Revision 1.7 1994/05/20 19:23:51 ericr 72** Moved STACK_FRAME macro from osfpal.s to here 73** 74** Revision 1.6 1994/05/20 18:08:19 ericr 75** Changed line comments to C++ style comment character 76** 77** Revision 1.5 1994/01/11 18:43:33 ericr 78** Removed PAL version/revision and size constants 79** 80** Revision 1.4 1994/01/05 16:22:32 ericr 81** Added more SCB vector offsets and MCHK error code 82** 83** Revision 1.3 1994/01/03 19:35:40 ericr 84** Derive mask definitions from field constants 85** 86** Revision 1.2 1993/12/22 20:43:01 eric 87** Added mask definitions for MCES bits 88** 89** Revision 1.1 1993/12/16 21:55:05 eric 90** Initial revision 91** 92** 93**-- 94*/ 95 96/* 97** Seg0 and Seg1 Virtual Address (VA) Format 98** 99** Loc Size Name Function 100** ----- ---- ---- --------------------------------- 101** <42:33> 10 SEG1 First level page table offset 102** <32:23> 10 SEG2 Second level page table offset 103** <22:13> 10 SEG3 Third level page table offset 104** <12:00> 13 OFFSET Byte within page offset 105*/ 106 107#define VA_V_SEG1 33 108#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) 109#define VA_V_SEG2 23 110#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) 111#define VA_V_SEG3 13 112#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) 113#define VA_V_OFFSET 0 114#define VA_M_OFFSET 0x1FFF 115 116/* 117** Virtual Address Options: 8K byte page size 118*/ 119 120#define VA_S_SIZE 43 121#define VA_S_OFF 13 122#define va_s_off 13 123#define VA_S_SEG 10 124#define VA_S_PAGE_SIZE 8192 125 126/* 127** Page Table Entry (PTE) Format 128** 129** Extent Size Name Function 130** ------ ---- ---- --------------------------------- 131** <63:32> 32 PFN Page Frame Number 132** <31:16> 16 SW Reserved for software 133** <15:14> 2 RSV0 Reserved for hardware SBZ 134** <13> 1 UWE User Write Enable 135** <12> 1 KWE Kernel Write Enable 136** <11:10> 2 RSV1 Reserved for hardware SBZ 137** <9> 1 URE User Read Enable 138** <8> 1 KRE Kernel Read Enable 139** <7> 1 RSV2 Reserved for hardware SBZ 140** <6:5> 2 GH Granularity Hint 141** <4> 1 ASM Address Space Match 142** <3> 1 FOE Fault On Execute 143** <2> 1 FOW Fault On Write 144** <1> 1 FOR Fault On Read 145** <0> 1 V Valid 146*/ 147 148#define PTE_V_PFN 32 149#define PTE_M_PFN 0xFFFFFFFF00000000 150#define PTE_V_SW 16 151#define PTE_M_SW 0x00000000FFFF0000 152#define PTE_V_UWE 13 153#define PTE_M_UWE (1<<PTE_V_UWE) 154#define PTE_V_KWE 12 155#define PTE_M_KWE (1<<PTE_V_KWE) 156#define PTE_V_URE 9 157#define PTE_M_URE (1<<PTE_V_URE) 158#define PTE_V_KRE 8 159#define PTE_M_KRE (1<<PTE_V_KRE) 160#define PTE_V_GH 5 161#define PTE_M_GH (3<<PTE_V_GH) 162#define PTE_V_ASM 4 163#define PTE_M_ASM (1<<PTE_V_ASM) 164#define PTE_V_FOE 3 165#define PTE_M_FOE (1<<PTE_V_FOE) 166#define PTE_V_FOW 2 167#define PTE_M_FOW (1<<PTE_V_FOW) 168#define PTE_V_FOR 1 169#define PTE_M_FOR (1<<PTE_V_FOR) 170#define PTE_V_VALID 0 171#define PTE_M_VALID (1<<PTE_V_VALID) 172 173#define PTE_M_KSEG 0x1111 174#define PTE_M_PROT 0x3300 175#define pte_m_prot 0x3300 176 177/* 178** System Entry Instruction Fault (entIF) Constants: 179*/ 180 181#define IF_K_BPT 0x0 182#define IF_K_BUGCHK 0x1 183#define IF_K_GENTRAP 0x2 184#define IF_K_FEN 0x3 185#define IF_K_OPCDEC 0x4 186 187/* 188** System Entry Hardware Interrupt (entInt) Constants: 189*/ 190 191#define INT_K_IP 0x0 192#define INT_K_CLK 0x1 193#define INT_K_MCHK 0x2 194#define INT_K_DEV 0x3 195#define INT_K_PERF 0x4 196 197/* 198** System Entry MM Fault (entMM) Constants: 199*/ 200 201#define MM_K_TNV 0x0 202#define MM_K_ACV 0x1 203#define MM_K_FOR 0x2 204#define MM_K_FOE 0x3 205#define MM_K_FOW 0x4 206 207/* 208** Process Control Block (PCB) Offsets: 209*/ 210 211#define PCB_Q_KSP 0x0000 212#define PCB_Q_USP 0x0008 213#define PCB_Q_PTBR 0x0010 214#define PCB_L_PCC 0x0018 215#define PCB_L_ASN 0x001C 216#define PCB_Q_UNIQUE 0x0020 217#define PCB_Q_FEN 0x0028 218#define PCB_Q_RSV0 0x0030 219#define PCB_Q_RSV1 0x0038 220 221/* 222** Processor Status Register (PS) Bit Summary 223** 224** Extent Size Name Function 225** ------ ---- ---- --------------------------------- 226** <3> 1 CM Current Mode 227** <2:0> 3 IPL Interrupt Priority Level 228**/ 229 230#define PS_V_CM 3 231#define PS_M_CM (1<<PS_V_CM) 232#define PS_V_IPL 0 233#define PS_M_IPL (7<<PS_V_IPL) 234 235#define PS_K_KERN (0<<PS_V_CM) 236#define PS_K_USER (1<<PS_V_CM) 237 238#define IPL_K_ZERO 0x0 239#define IPL_K_SW0 0x1 240#define IPL_K_SW1 0x2 241#define IPL_K_DEV0 0x3 242#define IPL_K_DEV1 0x4 243#define IPL_K_CLK 0x5 244#define IPL_K_RT 0x6 245#define IPL_K_PERF 0x6 246#define IPL_K_PFAIL 0x6 247#define IPL_K_MCHK 0x7 248 249#define IPL_K_LOW 0x0 250#define IPL_K_HIGH 0x7 251 252/* 253** SCB Offset Definitions: 254*/ 255 256#define SCB_Q_FEN 0x0010 257#define SCB_Q_ACV 0x0080 258#define SCB_Q_TNV 0x0090 259#define SCB_Q_FOR 0x00A0 260#define SCB_Q_FOW 0x00B0 261#define SCB_Q_FOE 0x00C0 262#define SCB_Q_ARITH 0x0200 263#define SCB_Q_KAST 0x0240 264#define SCB_Q_EAST 0x0250 265#define SCB_Q_SAST 0x0260 266#define SCB_Q_UAST 0x0270 267#define SCB_Q_UNALIGN 0x0280 268#define SCB_Q_BPT 0x0400 269#define SCB_Q_BUGCHK 0x0410 270#define SCB_Q_OPCDEC 0x0420 271#define SCB_Q_ILLPAL 0x0430 272#define SCB_Q_TRAP 0x0440 273#define SCB_Q_CHMK 0x0480 274#define SCB_Q_CHME 0x0490 275#define SCB_Q_CHMS 0x04A0 276#define SCB_Q_CHMU 0x04B0 277#define SCB_Q_SW0 0x0500 278#define SCB_Q_SW1 0x0510 279#define SCB_Q_SW2 0x0520 280#define SCB_Q_SW3 0x0530 281#define SCB_Q_SW4 0x0540 282#define SCB_Q_SW5 0x0550 283#define SCB_Q_SW6 0x0560 284#define SCB_Q_SW7 0x0570 285#define SCB_Q_SW8 0x0580 286#define SCB_Q_SW9 0x0590 287#define SCB_Q_SW10 0x05A0 288#define SCB_Q_SW11 0x05B0 289#define SCB_Q_SW12 0x05C0 290#define SCB_Q_SW13 0x05D0 291#define SCB_Q_SW14 0x05E0 292#define SCB_Q_SW15 0x05F0 293#define SCB_Q_CLOCK 0x0600 294#define SCB_Q_INTER 0x0610 295#define SCB_Q_SYSERR 0x0620 296#define SCB_Q_PROCERR 0x0630 297#define SCB_Q_PWRFAIL 0x0640 298#define SCB_Q_PERFMON 0x0650 299#define SCB_Q_SYSMCHK 0x0660 300#define SCB_Q_PROCMCHK 0x0670 301#define SCB_Q_PASSREL 0x0680 302 303/* 304** Stack Frame (FRM) Offsets: 305** 306** There are two types of system entries for OSF/1 - those for the 307** callsys CALL_PAL function and those for exceptions and interrupts. 308** Both entry types use the same stack frame layout. The stack frame 309** contains space for the PC, the PS, the saved GP, and the saved 310** argument registers a0, a1, and a2. On entry, SP points to the 311** saved PS. 312*/ 313 314#define FRM_Q_PS 0x0000 315#define FRM_Q_PC 0x0008 316#define FRM_Q_GP 0x0010 317#define FRM_Q_A0 0x0018 318#define FRM_Q_A1 0x0020 319#define FRM_Q_A2 0x0028 320 321#define FRM_K_SIZE 48 322 323#define STACK_FRAME(tmp1,tmp2) \ 324 sll ps, 63-PS_V_CM, p7; \ 325 bge p7, 0f; \ 326 bis zero, zero, ps; \ 327 mtpr sp, ptUsp; \ 328 mfpr sp, ptKsp; \ 3290: lda sp, 0-FRM_K_SIZE(sp); \ 330 stq tmp1, FRM_Q_PS(sp); \ 331 stq tmp2, FRM_Q_PC(sp); \ 332 stq gp, FRM_Q_GP(sp); \ 333 stq a0, FRM_Q_A0(sp); \ 334 stq a1, FRM_Q_A1(sp); \ 335 stq a2, FRM_Q_A2(sp) 336 337/* 338** Halt Codes: 339*/ 340 341#define HLT_K_RESET 0x0000 342#define HLT_K_HW_HALT 0x0001 343#define HLT_K_KSP_INVAL 0x0002 344#define HLT_K_SCBB_INVAL 0x0003 345#define HLT_K_PTBR_INVAL 0x0004 346#define HLT_K_SW_HALT 0x0005 347#define HLT_K_DBL_MCHK 0x0006 348#define HLT_K_MCHK_FROM_PAL 0x0007 349 350/* 351** Machine Check Codes: 352*/ 353 354#define MCHK_K_TPERR 0x0080 355#define MCHK_K_TCPERR 0x0082 356#define MCHK_K_HERR 0x0084 357#define MCHK_K_ECC_C 0x0086 358#define MCHK_K_ECC_NC 0x0088 359#define MCHK_K_UNKNOWN 0x008A 360#define MCHK_K_CACKSOFT 0x008C 361#define MCHK_K_BUGCHECK 0x008E 362#define MCHK_K_OS_BUGCHECK 0x0090 363#define MCHK_K_DCPERR 0x0092 364#define MCHK_K_ICPERR 0x0094 365#define MCHK_K_RETRY_IRD 0x0096 366#define MCHK_K_PROC_HERR 0x0098 367 368/* 369** System Machine Check Codes: 370*/ 371 372#define MCHK_K_READ_NXM 0x0200 373#define MCHK_K_SYS_HERR 0x0202 374 375/* 376** Machine Check Error Status Summary (MCES) Register Format 377** 378** Extent Size Name Function 379** ------ ---- ---- --------------------------------- 380** <0> 1 MIP Machine check in progress 381** <1> 1 SCE System correctable error in progress 382** <2> 1 PCE Processor correctable error in progress 383** <3> 1 DPC Disable PCE error reporting 384** <4> 1 DSC Disable SCE error reporting 385*/ 386 387#define MCES_V_MIP 0 388#define MCES_M_MIP (1<<MCES_V_MIP) 389#define MCES_V_SCE 1 390#define MCES_M_SCE (1<<MCES_V_SCE) 391#define MCES_V_PCE 2 392#define MCES_M_PCE (1<<MCES_V_PCE) 393#define MCES_V_DPC 3 394#define MCES_M_DPC (1<<MCES_V_DPC) 395#define MCES_V_DSC 4 396#define MCES_M_DSC (1<<MCES_V_DSC) 397 398#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ 399 | MCES_M_DSC) 400 401/* 402** Who-Am-I (WHAMI) Register Format 403** 404** Extent Size Name Function 405** ------ ---- ---- --------------------------------- 406** <7:0> 8 ID Who-Am-I identifier 407** <15:8> 1 SWAP Swap PALcode flag - character 'S' 408*/ 409 410#define WHAMI_V_SWAP 8 411#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) 412#define WHAMI_V_ID 0 413#define WHAMI_M_ID 0xFF 414 415#define WHAMI_K_SWAP 0x53 /* Character 'S' */ 416 417/* 418** Conventional Register Usage Definitions 419** 420** Assembler temporary `at' is `AT' so it doesn't conflict with the 421** `.set at' assembler directive. 422*/ 423 424#define v0 $0 /* Function Return Value Register */ 425#define t0 $1 /* Scratch (Temporary) Registers ... */ 426#define t1 $2 427#define t2 $3 428#define t3 $4 429#define t4 $5 430#define t5 $6 431#define t6 $7 432#define t7 $8 433#define s0 $9 /* Saved (Non-Volatile) Registers ... */ 434#define s1 $10 435#define s2 $11 436#define s3 $12 437#define s4 $13 438#define s5 $14 439#define fp $15 /* Frame Pointer Register, Or S6 */ 440#define s6 $15 441#define a0 $16 /* Argument Registers ... */ 442#define a1 $17 443#define a2 $18 444#define a3 $19 445#define a4 $20 446#define a5 $21 447#define t8 $22 /* Scratch (Temporary) Registers ... */ 448#define t9 $23 449#define t10 $24 450#define t11 $25 451#define ra $26 /* Return Address Register */ 452#define pv $27 /* Procedure Value Register, Or T12 */ 453#define t12 $27 454#define AT $28 /* Assembler Temporary (Volatile) Register */ 455#define gp $29 /* Global Pointer Register */ 456#define sp $30 /* Stack Pointer Register */ 457#define zero $31 /* Zero Register */ 458 459/* 460** OSF/1 Unprivileged CALL_PAL Entry Offsets: 461** 462** Entry Name Offset (Hex) 463** 464** bpt 0080 465** bugchk 0081 466** callsys 0083 467** imb 0086 468** rdunique 009E 469** wrunique 009F 470** gentrap 00AA 471** dbgstop 00AD 472*/ 473 474#define UNPRIV 0x80 475#define PAL_BPT_ENTRY 0x80 476#define PAL_BUGCHK_ENTRY 0x81 477#define PAL_CALLSYS_ENTRY 0x83 478#define PAL_IMB_ENTRY 0x86 479#define PAL_RDUNIQUE_ENTRY 0x9E 480#define PAL_WRUNIQUE_ENTRY 0x9F 481#define PAL_GENTRAP_ENTRY 0xAA 482 483#if defined(KDEBUG) 484#define PAL_DBGSTOP_ENTRY 0xAD 485/* #define NUM_UNPRIV_CALL_PALS 10 */ 486#else 487/* #define NUM_UNPRIV_CALL_PALS 9 */ 488#endif /* KDEBUG */ 489 490/* 491** OSF/1 Privileged CALL_PAL Entry Offsets: 492** 493** Entry Name Offset (Hex) 494** 495** halt 0000 496** cflush 0001 497** draina 0002 498** cserve 0009 499** swppal 000A 500** rdmces 0010 501** wrmces 0011 502** wrfen 002B 503** wrvptptr 002D 504** swpctx 0030 505** wrval 0031 506** rdval 0032 507** tbi 0033 508** wrent 0034 509** swpipl 0035 510** rdps 0036 511** wrkgp 0037 512** wrusp 0038 513** rdusp 003A 514** whami 003C 515** retsys 003D 516** rti 003F 517*/ 518 519#define PAL_HALT_ENTRY 0x0000 520#define PAL_CFLUSH_ENTRY 0x0001 521#define PAL_DRAINA_ENTRY 0x0002 522#define PAL_CSERVE_ENTRY 0x0009 523#define PAL_SWPPAL_ENTRY 0x000A 524#define PAL_WRIPIR_ENTRY 0x000D 525#define PAL_RDMCES_ENTRY 0x0010 526#define PAL_WRMCES_ENTRY 0x0011 527#define PAL_WRFEN_ENTRY 0x002B 528#define PAL_WRVPTPTR_ENTRY 0x002D 529#define PAL_SWPCTX_ENTRY 0x0030 530#define PAL_WRVAL_ENTRY 0x0031 531#define PAL_RDVAL_ENTRY 0x0032 532#define PAL_TBI_ENTRY 0x0033 533#define PAL_WRENT_ENTRY 0x0034 534#define PAL_SWPIPL_ENTRY 0x0035 535#define PAL_RDPS_ENTRY 0x0036 536#define PAL_WRKGP_ENTRY 0x0037 537#define PAL_WRUSP_ENTRY 0x0038 538#define PAL_RDUSP_ENTRY 0x003A 539#define PAL_WHAMI_ENTRY 0x003C 540#define PAL_RETSYS_ENTRY 0x003D 541#define PAL_RTI_ENTRY 0x003F 542 543#define NUM_PRIV_CALL_PALS 23 544 545#endif 546 547