fromHudsonOsf.h revision 7997:b91bdbee66c3
12SN/A#ifndef FROMHUDSONOSF_INCLUDED 21762SN/A#define FROMHUDSONOSF_INCLUDED 1 32SN/A/* 42SN/A * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] 52SN/A * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] 62SN/A */ 72SN/A#define __OSF_LOADED 1 82SN/A/* 92SN/A***************************************************************************** 102SN/A** * 112SN/A** Copyright � 1993, 1994 * 122SN/A** by Digital Equipment Corporation, Maynard, Massachusetts. * 132SN/A** * 142SN/A** All Rights Reserved * 152SN/A** * 162SN/A** Permission is hereby granted to use, copy, modify and distribute * 172SN/A** this software and its documentation, in both source code and * 182SN/A** object code form, and without fee, for the purpose of distribution * 192SN/A** of this software or modifications of this software within products * 202SN/A** incorporating an integrated circuit implementing Digital's AXP * 212SN/A** architecture, regardless of the source of such integrated circuit, * 222SN/A** provided that the above copyright notice and this permission notice * 232SN/A** appear in all copies, and that the name of Digital Equipment * 242SN/A** Corporation not be used in advertising or publicity pertaining to * 252SN/A** distribution of the document or software without specific, written * 262SN/A** prior permission. * 272665Ssaidi@eecs.umich.edu** * 282665Ssaidi@eecs.umich.edu** Digital Equipment Corporation disclaims all warranties and/or * 292SN/A** guarantees with regard to this software, including all implied * 302SN/A** warranties of fitness for a particular purpose and merchantability, * 318229Snate@binkert.org** and makes no representations regarding the use of, or the results * 322SN/A** of the use of, the software and documentation in terms of correctness, * 332SN/A** accuracy, reliability, currentness or otherwise; and you rely on * 342SN/A** the software, documentation and results solely at your own risk. * 352SN/A** * 362SN/A** AXP is a trademark of Digital Equipment Corporation. * 37148SN/A** * 3856SN/A***************************************************************************** 395889Snate@binkert.org** 40441SN/A** FACILITY: 4156SN/A** 4256SN/A** DECchip 21164 PALcode 4356SN/A** 44441SN/A** MODULE: 45433SN/A** 462SN/A** osf.h 472SN/A** 482SN/A** MODULE DESCRIPTION: 49729SN/A** 50388SN/A** OSF/1 specific definitions 518243Sbradley.danofsky@amd.com** 525887Snate@binkert.org** AUTHOR: ER 535887Snate@binkert.org** 545887Snate@binkert.org** CREATION DATE: 24-Nov-1993 555887Snate@binkert.org** 565887Snate@binkert.org** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 57388SN/A** 585887Snate@binkert.org** MODIFICATION HISTORY: 595887Snate@binkert.org** 60388SN/A** $Log: fromHudsonOsf.h,v $ 61388SN/A** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 625887Snate@binkert.org** current 10/29/97 635887Snate@binkert.org** 64441SN/A** Revision 1.1 1995/11/18 01:46:31 boyle 655887Snate@binkert.org** Initial revision 665887Snate@binkert.org** 67441SN/A** Revision 1.11 1995/04/21 02:06:30 fdh 68441SN/A** Replaced C++ style comments with Standard C style comments. 69388SN/A** 705886Snate@binkert.org** Revision 1.10 1994/09/26 14:17:47 samberg 71388SN/A** Complete VICE work and EB164/SD164 breakout. 725887Snate@binkert.org** 735887Snate@binkert.org** Revision 1.9 1994/07/26 17:39:10 samberg 745887Snate@binkert.org** Changes for SD164. 755887Snate@binkert.org** 765887Snate@binkert.org** Revision 1.8 1994/07/08 17:03:48 samberg 775887Snate@binkert.org** Changes to support platform specific additions 785887Snate@binkert.org** 795887Snate@binkert.org** Revision 1.7 1994/05/20 19:23:51 ericr 805887Snate@binkert.org** Moved STACK_FRAME macro from osfpal.s to here 815887Snate@binkert.org** 825887Snate@binkert.org** Revision 1.6 1994/05/20 18:08:19 ericr 83388SN/A** Changed line comments to C++ style comment character 84388SN/A** 85388SN/A** Revision 1.5 1994/01/11 18:43:33 ericr 865889Snate@binkert.org** Removed PAL version/revision and size constants 875889Snate@binkert.org** 885889Snate@binkert.org** Revision 1.4 1994/01/05 16:22:32 ericr 895889Snate@binkert.org** Added more SCB vector offsets and MCHK error code 905889Snate@binkert.org** 915889Snate@binkert.org** Revision 1.3 1994/01/03 19:35:40 ericr 925886Snate@binkert.org** Derive mask definitions from field constants 93388SN/A** 946130Snate@binkert.org** Revision 1.2 1993/12/22 20:43:01 eric 95388SN/A** Added mask definitions for MCES bits 96388SN/A** 975886Snate@binkert.org** Revision 1.1 1993/12/16 21:55:05 eric 985886Snate@binkert.org** Initial revision 99388SN/A** 1005887Snate@binkert.org** 1015887Snate@binkert.org**-- 1025887Snate@binkert.org*/ 103388SN/A 104388SN/A/* 1055886Snate@binkert.org** Seg0 and Seg1 Virtual Address (VA) Format 1065886Snate@binkert.org** 1075886Snate@binkert.org** Loc Size Name Function 1085887Snate@binkert.org** ----- ---- ---- --------------------------------- 1095887Snate@binkert.org** <42:33> 10 SEG1 First level page table offset 1105887Snate@binkert.org** <32:23> 10 SEG2 Second level page table offset 1115886Snate@binkert.org** <22:13> 10 SEG3 Third level page table offset 1125886Snate@binkert.org** <12:00> 13 OFFSET Byte within page offset 1135889Snate@binkert.org*/ 1145889Snate@binkert.org 1155889Snate@binkert.org#define VA_V_SEG1 33 1165889Snate@binkert.org#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) 1176026Snate@binkert.org#define VA_V_SEG2 23 1186026Snate@binkert.org#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) 1196026Snate@binkert.org#define VA_V_SEG3 13 1206026Snate@binkert.org#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) 1216026Snate@binkert.org#define VA_V_OFFSET 0 1226026Snate@binkert.org#define VA_M_OFFSET 0x1FFF 1236026Snate@binkert.org 1246026Snate@binkert.org/* 1255889Snate@binkert.org** Virtual Address Options: 8K byte page size 1265889Snate@binkert.org*/ 1275889Snate@binkert.org 1285889Snate@binkert.org#define VA_S_SIZE 43 1295886Snate@binkert.org#define VA_S_OFF 13 1305889Snate@binkert.org#define va_s_off 13 131582SN/A#define VA_S_SEG 10 1325889Snate@binkert.org#define VA_S_PAGE_SIZE 8192 1335889Snate@binkert.org 1348231Snate@binkert.org/* 135582SN/A** Page Table Entry (PTE) Format 136582SN/A** 1375886Snate@binkert.org** Extent Size Name Function 138388SN/A** ------ ---- ---- --------------------------------- 139388SN/A** <63:32> 32 PFN Page Frame Number 140388SN/A** <31:16> 16 SW Reserved for software 1418248Snate@binkert.org** <15:14> 2 RSV0 Reserved for hardware SBZ 1428248Snate@binkert.org** <13> 1 UWE User Write Enable 1438248Snate@binkert.org** <12> 1 KWE Kernel Write Enable 1448248Snate@binkert.org** <11:10> 2 RSV1 Reserved for hardware SBZ 1458248Snate@binkert.org** <9> 1 URE User Read Enable 1468248Snate@binkert.org** <8> 1 KRE Kernel Read Enable 1478248Snate@binkert.org** <7> 1 RSV2 Reserved for hardware SBZ 1488248Snate@binkert.org** <6:5> 2 GH Granularity Hint 1498248Snate@binkert.org** <4> 1 ASM Address Space Match 1508248Snate@binkert.org** <3> 1 FOE Fault On Execute 1518248Snate@binkert.org** <2> 1 FOW Fault On Write 1528248Snate@binkert.org** <1> 1 FOR Fault On Read 1538248Snate@binkert.org** <0> 1 V Valid 1548248Snate@binkert.org*/ 1558248Snate@binkert.org 1568248Snate@binkert.org#define PTE_V_PFN 32 1578248Snate@binkert.org#define PTE_M_PFN 0xFFFFFFFF00000000 1588248Snate@binkert.org#define PTE_V_SW 16 1598248Snate@binkert.org#define PTE_M_SW 0x00000000FFFF0000 1608248Snate@binkert.org#define PTE_V_UWE 13 1618248Snate@binkert.org#define PTE_M_UWE (1<<PTE_V_UWE) 1628248Snate@binkert.org#define PTE_V_KWE 12 1638248Snate@binkert.org#define PTE_M_KWE (1<<PTE_V_KWE) 1648248Snate@binkert.org#define PTE_V_URE 9 1658248Snate@binkert.org#define PTE_M_URE (1<<PTE_V_URE) 1668248Snate@binkert.org#define PTE_V_KRE 8 1678248Snate@binkert.org#define PTE_M_KRE (1<<PTE_V_KRE) 1688248Snate@binkert.org#define PTE_V_GH 5 1698248Snate@binkert.org#define PTE_M_GH (3<<PTE_V_GH) 1708248Snate@binkert.org#define PTE_V_ASM 4 1718248Snate@binkert.org#define PTE_M_ASM (1<<PTE_V_ASM) 1726026Snate@binkert.org#define PTE_V_FOE 3 1736026Snate@binkert.org#define PTE_M_FOE (1<<PTE_V_FOE) 1746026Snate@binkert.org#define PTE_V_FOW 2 1758248Snate@binkert.org#define PTE_M_FOW (1<<PTE_V_FOW) 1768248Snate@binkert.org#define PTE_V_FOR 1 1778248Snate@binkert.org#define PTE_M_FOR (1<<PTE_V_FOR) 1786026Snate@binkert.org#define PTE_V_VALID 0 1796026Snate@binkert.org#define PTE_M_VALID (1<<PTE_V_VALID) 1806026Snate@binkert.org 1816026Snate@binkert.org#define PTE_M_KSEG 0x1111 1826026Snate@binkert.org#define PTE_M_PROT 0x3300 1836026Snate@binkert.org#define pte_m_prot 0x3300 1846026Snate@binkert.org 1856026Snate@binkert.org/* 1866026Snate@binkert.org** System Entry Instruction Fault (entIF) Constants: 1876026Snate@binkert.org*/ 1886026Snate@binkert.org 1896026Snate@binkert.org#define IF_K_BPT 0x0 1906026Snate@binkert.org#define IF_K_BUGCHK 0x1 1916026Snate@binkert.org#define IF_K_GENTRAP 0x2 1926026Snate@binkert.org#define IF_K_FEN 0x3 1932SN/A#define IF_K_OPCDEC 0x4 1945886Snate@binkert.org 1952SN/A/* 196388SN/A** System Entry Hardware Interrupt (entInt) Constants: 197388SN/A*/ 1982SN/A 1992SN/A#define INT_K_IP 0x0 2002SN/A#define INT_K_CLK 0x1 2012SN/A#define INT_K_MCHK 0x2 2022SN/A#define INT_K_DEV 0x3 2032SN/A#define INT_K_PERF 0x4 2042SN/A 2055599Snate@binkert.org/* 2065599Snate@binkert.org** System Entry MM Fault (entMM) Constants: 2072SN/A*/ 2082SN/A 2092SN/A#define MM_K_TNV 0x0 2102SN/A#define MM_K_ACV 0x1 2112SN/A#define MM_K_FOR 0x2 2122SN/A#define MM_K_FOE 0x3 2132SN/A#define MM_K_FOW 0x4 2142SN/A 2152SN/A/* 2162SN/A** Process Control Block (PCB) Offsets: 2172SN/A*/ 2182SN/A 219388SN/A#define PCB_Q_KSP 0x0000 2205886Snate@binkert.org#define PCB_Q_USP 0x0008 2212SN/A#define PCB_Q_PTBR 0x0010 2226000Snate@binkert.org#define PCB_L_PCC 0x0018 223582SN/A#define PCB_L_ASN 0x001C 224695SN/A#define PCB_Q_UNIQUE 0x0020 225388SN/A#define PCB_Q_FEN 0x0028 226388SN/A#define PCB_Q_RSV0 0x0030 227388SN/A#define PCB_Q_RSV1 0x0038 228388SN/A 2292SN/A/* 2307462Snate@binkert.org** Processor Status Register (PS) Bit Summary 231388SN/A** 232388SN/A** Extent Size Name Function 233388SN/A** ------ ---- ---- --------------------------------- 2342SN/A** <3> 1 CM Current Mode 235388SN/A** <2:0> 3 IPL Interrupt Priority Level 2362SN/A**/ 2372SN/A 2386001Snate@binkert.org#define PS_V_CM 3 2396001Snate@binkert.org#define PS_M_CM (1<<PS_V_CM) 2406001Snate@binkert.org#define PS_V_IPL 0 2416001Snate@binkert.org#define PS_M_IPL (7<<PS_V_IPL) 2426001Snate@binkert.org 2436001Snate@binkert.org#define PS_K_KERN (0<<PS_V_CM) 2446128Snate@binkert.org#define PS_K_USER (1<<PS_V_CM) 2456001Snate@binkert.org 2466001Snate@binkert.org#define IPL_K_ZERO 0x0 2476001Snate@binkert.org#define IPL_K_SW0 0x1 2486001Snate@binkert.org#define IPL_K_SW1 0x2 2496001Snate@binkert.org#define IPL_K_DEV0 0x3 2506001Snate@binkert.org#define IPL_K_DEV1 0x4 2516001Snate@binkert.org#define IPL_K_CLK 0x5 2526001Snate@binkert.org#define IPL_K_RT 0x6 2536001Snate@binkert.org#define IPL_K_PERF 0x6 2546128Snate@binkert.org#define IPL_K_PFAIL 0x6 2556001Snate@binkert.org#define IPL_K_MCHK 0x7 2566001Snate@binkert.org 2576001Snate@binkert.org#define IPL_K_LOW 0x0 2586001Snate@binkert.org#define IPL_K_HIGH 0x7 2596001Snate@binkert.org 2606001Snate@binkert.org/* 2616001Snate@binkert.org** SCB Offset Definitions: 2626001Snate@binkert.org*/ 2636001Snate@binkert.org 2646128Snate@binkert.org#define SCB_Q_FEN 0x0010 2656001Snate@binkert.org#define SCB_Q_ACV 0x0080 2666001Snate@binkert.org#define SCB_Q_TNV 0x0090 2676001Snate@binkert.org#define SCB_Q_FOR 0x00A0 2686001Snate@binkert.org#define SCB_Q_FOW 0x00B0 2696001Snate@binkert.org#define SCB_Q_FOE 0x00C0 2706001Snate@binkert.org#define SCB_Q_ARITH 0x0200 2716001Snate@binkert.org#define SCB_Q_KAST 0x0240 2726001Snate@binkert.org#define SCB_Q_EAST 0x0250 273695SN/A#define SCB_Q_SAST 0x0260 2747831Snate@binkert.org#define SCB_Q_UAST 0x0270 2757831Snate@binkert.org#define SCB_Q_UNALIGN 0x0280 2767831Snate@binkert.org#define SCB_Q_BPT 0x0400 2777831Snate@binkert.org#define SCB_Q_BUGCHK 0x0410 2787831Snate@binkert.org#define SCB_Q_OPCDEC 0x0420 2797831Snate@binkert.org#define SCB_Q_ILLPAL 0x0430 2807831Snate@binkert.org#define SCB_Q_TRAP 0x0440 2817831Snate@binkert.org#define SCB_Q_CHMK 0x0480 2827831Snate@binkert.org#define SCB_Q_CHME 0x0490 2837831Snate@binkert.org#define SCB_Q_CHMS 0x04A0 2847831Snate@binkert.org#define SCB_Q_CHMU 0x04B0 2857831Snate@binkert.org#define SCB_Q_SW0 0x0500 2867831Snate@binkert.org#define SCB_Q_SW1 0x0510 2877831Snate@binkert.org#define SCB_Q_SW2 0x0520 2887831Snate@binkert.org#define SCB_Q_SW3 0x0530 2897831Snate@binkert.org#define SCB_Q_SW4 0x0540 2907831Snate@binkert.org#define SCB_Q_SW5 0x0550 2917831Snate@binkert.org#define SCB_Q_SW6 0x0560 2927831Snate@binkert.org#define SCB_Q_SW7 0x0570 2937831Snate@binkert.org#define SCB_Q_SW8 0x0580 2947831Snate@binkert.org#define SCB_Q_SW9 0x0590 2957831Snate@binkert.org#define SCB_Q_SW10 0x05A0 2967831Snate@binkert.org#define SCB_Q_SW11 0x05B0 2977831Snate@binkert.org#define SCB_Q_SW12 0x05C0 2987831Snate@binkert.org#define SCB_Q_SW13 0x05D0 2997831Snate@binkert.org#define SCB_Q_SW14 0x05E0 3007831Snate@binkert.org#define SCB_Q_SW15 0x05F0 3017831Snate@binkert.org#define SCB_Q_CLOCK 0x0600 3027831Snate@binkert.org#define SCB_Q_INTER 0x0610 3037831Snate@binkert.org#define SCB_Q_SYSERR 0x0620 3047831Snate@binkert.org#define SCB_Q_PROCERR 0x0630 3057831Snate@binkert.org#define SCB_Q_PWRFAIL 0x0640 3067831Snate@binkert.org#define SCB_Q_PERFMON 0x0650 3077831Snate@binkert.org#define SCB_Q_SYSMCHK 0x0660 3087831Snate@binkert.org#define SCB_Q_PROCMCHK 0x0670 3097831Snate@binkert.org#define SCB_Q_PASSREL 0x0680 3107831Snate@binkert.org 3117831Snate@binkert.org/* 3127831Snate@binkert.org** Stack Frame (FRM) Offsets: 3137831Snate@binkert.org** 3147831Snate@binkert.org** There are two types of system entries for OSF/1 - those for the 3157831Snate@binkert.org** callsys CALL_PAL function and those for exceptions and interrupts. 3167831Snate@binkert.org** Both entry types use the same stack frame layout. The stack frame 3177831Snate@binkert.org** contains space for the PC, the PS, the saved GP, and the saved 3187831Snate@binkert.org** argument registers a0, a1, and a2. On entry, SP points to the 3197831Snate@binkert.org** saved PS. 3207831Snate@binkert.org*/ 3217831Snate@binkert.org 3227831Snate@binkert.org#define FRM_Q_PS 0x0000 3237831Snate@binkert.org#define FRM_Q_PC 0x0008 3247831Snate@binkert.org#define FRM_Q_GP 0x0010 3257831Snate@binkert.org#define FRM_Q_A0 0x0018 3267831Snate@binkert.org#define FRM_Q_A1 0x0020 3277831Snate@binkert.org#define FRM_Q_A2 0x0028 3287831Snate@binkert.org 3297831Snate@binkert.org#define FRM_K_SIZE 48 3307831Snate@binkert.org 3317831Snate@binkert.org#define STACK_FRAME(tmp1,tmp2) \ 3327831Snate@binkert.org sll ps, 63-PS_V_CM, p7; \ 3337831Snate@binkert.org bge p7, 0f; \ 3347831Snate@binkert.org bis zero, zero, ps; \ 3357831Snate@binkert.org mtpr sp, ptUsp; \ 3367831Snate@binkert.org mfpr sp, ptKsp; \ 3377831Snate@binkert.org0: lda sp, 0-FRM_K_SIZE(sp); \ 3387831Snate@binkert.org stq tmp1, FRM_Q_PS(sp); \ 3397831Snate@binkert.org stq tmp2, FRM_Q_PC(sp); \ 3407831Snate@binkert.org stq gp, FRM_Q_GP(sp); \ 3417831Snate@binkert.org stq a0, FRM_Q_A0(sp); \ 3427831Snate@binkert.org stq a1, FRM_Q_A1(sp); \ 3437831Snate@binkert.org stq a2, FRM_Q_A2(sp) 3447831Snate@binkert.org 3457831Snate@binkert.org/* 3467831Snate@binkert.org** Halt Codes: 3477831Snate@binkert.org*/ 3487831Snate@binkert.org 3497831Snate@binkert.org#define HLT_K_RESET 0x0000 3507831Snate@binkert.org#define HLT_K_HW_HALT 0x0001 3517831Snate@binkert.org#define HLT_K_KSP_INVAL 0x0002 3527831Snate@binkert.org#define HLT_K_SCBB_INVAL 0x0003 3537831Snate@binkert.org#define HLT_K_PTBR_INVAL 0x0004 3547831Snate@binkert.org#define HLT_K_SW_HALT 0x0005 3557831Snate@binkert.org#define HLT_K_DBL_MCHK 0x0006 3567831Snate@binkert.org#define HLT_K_MCHK_FROM_PAL 0x0007 357388SN/A 358388SN/A/* 359388SN/A** Machine Check Codes: 360388SN/A*/ 361388SN/A 362388SN/A#define MCHK_K_TPERR 0x0080 363388SN/A#define MCHK_K_TCPERR 0x0082 3647461Snate@binkert.org#define MCHK_K_HERR 0x0084 365388SN/A#define MCHK_K_ECC_C 0x0086 366388SN/A#define MCHK_K_ECC_NC 0x0088 367388SN/A#define MCHK_K_UNKNOWN 0x008A 368388SN/A#define MCHK_K_CACKSOFT 0x008C 369388SN/A#define MCHK_K_BUGCHECK 0x008E 370388SN/A#define MCHK_K_OS_BUGCHECK 0x0090 371388SN/A#define MCHK_K_DCPERR 0x0092 372388SN/A#define MCHK_K_ICPERR 0x0094 3737461Snate@binkert.org#define MCHK_K_RETRY_IRD 0x0096 374388SN/A#define MCHK_K_PROC_HERR 0x0098 375388SN/A 376388SN/A/* 377388SN/A** System Machine Check Codes: 378388SN/A*/ 379388SN/A 380388SN/A#define MCHK_K_READ_NXM 0x0200 381388SN/A#define MCHK_K_SYS_HERR 0x0202 382695SN/A 3837461Snate@binkert.org/* 384388SN/A** Machine Check Error Status Summary (MCES) Register Format 3857461Snate@binkert.org** 3867461Snate@binkert.org** Extent Size Name Function 3877461Snate@binkert.org** ------ ---- ---- --------------------------------- 388388SN/A** <0> 1 MIP Machine check in progress 389388SN/A** <1> 1 SCE System correctable error in progress 390388SN/A** <2> 1 PCE Processor correctable error in progress 391388SN/A** <3> 1 DPC Disable PCE error reporting 392142SN/A** <4> 1 DSC Disable SCE error reporting 3936000Snate@binkert.org*/ 3946000Snate@binkert.org 3956000Snate@binkert.org#define MCES_V_MIP 0 3966000Snate@binkert.org#define MCES_M_MIP (1<<MCES_V_MIP) 3976000Snate@binkert.org#define MCES_V_SCE 1 3986000Snate@binkert.org#define MCES_M_SCE (1<<MCES_V_SCE) 3996000Snate@binkert.org#define MCES_V_PCE 2 4006000Snate@binkert.org#define MCES_M_PCE (1<<MCES_V_PCE) 4016000Snate@binkert.org#define MCES_V_DPC 3 4026000Snate@binkert.org#define MCES_M_DPC (1<<MCES_V_DPC) 4036000Snate@binkert.org#define MCES_V_DSC 4 4046000Snate@binkert.org#define MCES_M_DSC (1<<MCES_V_DSC) 4056000Snate@binkert.org 4066000Snate@binkert.org#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ 4076000Snate@binkert.org | MCES_M_DSC) 4086000Snate@binkert.org 4096000Snate@binkert.org/* 4106000Snate@binkert.org** Who-Am-I (WHAMI) Register Format 4116000Snate@binkert.org** 4126000Snate@binkert.org** Extent Size Name Function 4136000Snate@binkert.org** ------ ---- ---- --------------------------------- 4146000Snate@binkert.org** <7:0> 8 ID Who-Am-I identifier 4156000Snate@binkert.org** <15:8> 1 SWAP Swap PALcode flag - character 'S' 4166000Snate@binkert.org*/ 4176000Snate@binkert.org 4186000Snate@binkert.org#define WHAMI_V_SWAP 8 4196000Snate@binkert.org#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) 4206000Snate@binkert.org#define WHAMI_V_ID 0 4216000Snate@binkert.org#define WHAMI_M_ID 0xFF 4226000Snate@binkert.org 4236000Snate@binkert.org#define WHAMI_K_SWAP 0x53 /* Character 'S' */ 4246227Snate@binkert.org 4256000Snate@binkert.org/* 4266000Snate@binkert.org** Conventional Register Usage Definitions 4276000Snate@binkert.org** 4286000Snate@binkert.org** Assembler temporary `at' is `AT' so it doesn't conflict with the 4296000Snate@binkert.org** `.set at' assembler directive. 4306000Snate@binkert.org*/ 4316000Snate@binkert.org 4326000Snate@binkert.org#define v0 $0 /* Function Return Value Register */ 4336000Snate@binkert.org#define t0 $1 /* Scratch (Temporary) Registers ... */ 4346000Snate@binkert.org#define t1 $2 4356000Snate@binkert.org#define t2 $3 436695SN/A#define t3 $4 4372SN/A#define t4 $5 438456SN/A#define t5 $6 439394SN/A#define t6 $7 440148SN/A#define t7 $8 441148SN/A#define s0 $9 /* Saved (Non-Volatile) Registers ... */ 442148SN/A#define s1 $10 443148SN/A#define s2 $11 4447811Ssteve.reinhardt@amd.com#define s3 $12 4458296Snate@binkert.org#define s4 $13 4468296Snate@binkert.org#define s5 $14 4478296Snate@binkert.org#define fp $15 /* Frame Pointer Register, Or S6 */ 4488296Snate@binkert.org#define s6 $15 4498296Snate@binkert.org#define a0 $16 /* Argument Registers ... */ 4508296Snate@binkert.org#define a1 $17 451#define a2 $18 452#define a3 $19 453#define a4 $20 454#define a5 $21 455#define t8 $22 /* Scratch (Temporary) Registers ... */ 456#define t9 $23 457#define t10 $24 458#define t11 $25 459#define ra $26 /* Return Address Register */ 460#define pv $27 /* Procedure Value Register, Or T12 */ 461#define t12 $27 462#define AT $28 /* Assembler Temporary (Volatile) Register */ 463#define gp $29 /* Global Pointer Register */ 464#define sp $30 /* Stack Pointer Register */ 465#define zero $31 /* Zero Register */ 466 467/* 468** OSF/1 Unprivileged CALL_PAL Entry Offsets: 469** 470** Entry Name Offset (Hex) 471** 472** bpt 0080 473** bugchk 0081 474** callsys 0083 475** imb 0086 476** rdunique 009E 477** wrunique 009F 478** gentrap 00AA 479** dbgstop 00AD 480*/ 481 482#define UNPRIV 0x80 483#define PAL_BPT_ENTRY 0x80 484#define PAL_BUGCHK_ENTRY 0x81 485#define PAL_CALLSYS_ENTRY 0x83 486#define PAL_IMB_ENTRY 0x86 487#define PAL_RDUNIQUE_ENTRY 0x9E 488#define PAL_WRUNIQUE_ENTRY 0x9F 489#define PAL_GENTRAP_ENTRY 0xAA 490 491#if defined(KDEBUG) 492#define PAL_DBGSTOP_ENTRY 0xAD 493/* #define NUM_UNPRIV_CALL_PALS 10 */ 494#else 495/* #define NUM_UNPRIV_CALL_PALS 9 */ 496#endif /* KDEBUG */ 497 498/* 499** OSF/1 Privileged CALL_PAL Entry Offsets: 500** 501** Entry Name Offset (Hex) 502** 503** halt 0000 504** cflush 0001 505** draina 0002 506** cserve 0009 507** swppal 000A 508** rdmces 0010 509** wrmces 0011 510** wrfen 002B 511** wrvptptr 002D 512** swpctx 0030 513** wrval 0031 514** rdval 0032 515** tbi 0033 516** wrent 0034 517** swpipl 0035 518** rdps 0036 519** wrkgp 0037 520** wrusp 0038 521** rdusp 003A 522** whami 003C 523** retsys 003D 524** rti 003F 525*/ 526 527#define PAL_HALT_ENTRY 0x0000 528#define PAL_CFLUSH_ENTRY 0x0001 529#define PAL_DRAINA_ENTRY 0x0002 530#define PAL_CSERVE_ENTRY 0x0009 531#define PAL_SWPPAL_ENTRY 0x000A 532#define PAL_WRIPIR_ENTRY 0x000D 533#define PAL_RDMCES_ENTRY 0x0010 534#define PAL_WRMCES_ENTRY 0x0011 535#define PAL_WRFEN_ENTRY 0x002B 536#define PAL_WRVPTPTR_ENTRY 0x002D 537#define PAL_SWPCTX_ENTRY 0x0030 538#define PAL_WRVAL_ENTRY 0x0031 539#define PAL_RDVAL_ENTRY 0x0032 540#define PAL_TBI_ENTRY 0x0033 541#define PAL_WRENT_ENTRY 0x0034 542#define PAL_SWPIPL_ENTRY 0x0035 543#define PAL_RDPS_ENTRY 0x0036 544#define PAL_WRKGP_ENTRY 0x0037 545#define PAL_WRUSP_ENTRY 0x0038 546#define PAL_RDUSP_ENTRY 0x003A 547#define PAL_WHAMI_ENTRY 0x003C 548#define PAL_RETSYS_ENTRY 0x003D 549#define PAL_RTI_ENTRY 0x003F 550 551#define NUM_PRIV_CALL_PALS 23 552 553#endif 554 555