fromHudsonOsf.h revision 7997
17997Ssaidi@eecs.umich.edu#ifndef FROMHUDSONOSF_INCLUDED 27997Ssaidi@eecs.umich.edu#define FROMHUDSONOSF_INCLUDED 1 37997Ssaidi@eecs.umich.edu/* 47997Ssaidi@eecs.umich.edu * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] 57997Ssaidi@eecs.umich.edu * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] 67997Ssaidi@eecs.umich.edu */ 77997Ssaidi@eecs.umich.edu#define __OSF_LOADED 1 87997Ssaidi@eecs.umich.edu/* 97997Ssaidi@eecs.umich.edu***************************************************************************** 107997Ssaidi@eecs.umich.edu** * 117997Ssaidi@eecs.umich.edu** Copyright � 1993, 1994 * 127997Ssaidi@eecs.umich.edu** by Digital Equipment Corporation, Maynard, Massachusetts. * 137997Ssaidi@eecs.umich.edu** * 147997Ssaidi@eecs.umich.edu** All Rights Reserved * 157997Ssaidi@eecs.umich.edu** * 167997Ssaidi@eecs.umich.edu** Permission is hereby granted to use, copy, modify and distribute * 177997Ssaidi@eecs.umich.edu** this software and its documentation, in both source code and * 187997Ssaidi@eecs.umich.edu** object code form, and without fee, for the purpose of distribution * 197997Ssaidi@eecs.umich.edu** of this software or modifications of this software within products * 207997Ssaidi@eecs.umich.edu** incorporating an integrated circuit implementing Digital's AXP * 217997Ssaidi@eecs.umich.edu** architecture, regardless of the source of such integrated circuit, * 227997Ssaidi@eecs.umich.edu** provided that the above copyright notice and this permission notice * 237997Ssaidi@eecs.umich.edu** appear in all copies, and that the name of Digital Equipment * 247997Ssaidi@eecs.umich.edu** Corporation not be used in advertising or publicity pertaining to * 257997Ssaidi@eecs.umich.edu** distribution of the document or software without specific, written * 267997Ssaidi@eecs.umich.edu** prior permission. * 277997Ssaidi@eecs.umich.edu** * 287997Ssaidi@eecs.umich.edu** Digital Equipment Corporation disclaims all warranties and/or * 297997Ssaidi@eecs.umich.edu** guarantees with regard to this software, including all implied * 307997Ssaidi@eecs.umich.edu** warranties of fitness for a particular purpose and merchantability, * 317997Ssaidi@eecs.umich.edu** and makes no representations regarding the use of, or the results * 327997Ssaidi@eecs.umich.edu** of the use of, the software and documentation in terms of correctness, * 337997Ssaidi@eecs.umich.edu** accuracy, reliability, currentness or otherwise; and you rely on * 347997Ssaidi@eecs.umich.edu** the software, documentation and results solely at your own risk. * 357997Ssaidi@eecs.umich.edu** * 367997Ssaidi@eecs.umich.edu** AXP is a trademark of Digital Equipment Corporation. * 377997Ssaidi@eecs.umich.edu** * 387997Ssaidi@eecs.umich.edu***************************************************************************** 397997Ssaidi@eecs.umich.edu** 407997Ssaidi@eecs.umich.edu** FACILITY: 417997Ssaidi@eecs.umich.edu** 427997Ssaidi@eecs.umich.edu** DECchip 21164 PALcode 437997Ssaidi@eecs.umich.edu** 447997Ssaidi@eecs.umich.edu** MODULE: 457997Ssaidi@eecs.umich.edu** 467997Ssaidi@eecs.umich.edu** osf.h 477997Ssaidi@eecs.umich.edu** 487997Ssaidi@eecs.umich.edu** MODULE DESCRIPTION: 497997Ssaidi@eecs.umich.edu** 507997Ssaidi@eecs.umich.edu** OSF/1 specific definitions 517997Ssaidi@eecs.umich.edu** 527997Ssaidi@eecs.umich.edu** AUTHOR: ER 537997Ssaidi@eecs.umich.edu** 547997Ssaidi@eecs.umich.edu** CREATION DATE: 24-Nov-1993 557997Ssaidi@eecs.umich.edu** 567997Ssaidi@eecs.umich.edu** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 577997Ssaidi@eecs.umich.edu** 587997Ssaidi@eecs.umich.edu** MODIFICATION HISTORY: 597997Ssaidi@eecs.umich.edu** 607997Ssaidi@eecs.umich.edu** $Log: fromHudsonOsf.h,v $ 617997Ssaidi@eecs.umich.edu** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 627997Ssaidi@eecs.umich.edu** current 10/29/97 637997Ssaidi@eecs.umich.edu** 647997Ssaidi@eecs.umich.edu** Revision 1.1 1995/11/18 01:46:31 boyle 657997Ssaidi@eecs.umich.edu** Initial revision 667997Ssaidi@eecs.umich.edu** 677997Ssaidi@eecs.umich.edu** Revision 1.11 1995/04/21 02:06:30 fdh 687997Ssaidi@eecs.umich.edu** Replaced C++ style comments with Standard C style comments. 697997Ssaidi@eecs.umich.edu** 707997Ssaidi@eecs.umich.edu** Revision 1.10 1994/09/26 14:17:47 samberg 717997Ssaidi@eecs.umich.edu** Complete VICE work and EB164/SD164 breakout. 727997Ssaidi@eecs.umich.edu** 737997Ssaidi@eecs.umich.edu** Revision 1.9 1994/07/26 17:39:10 samberg 747997Ssaidi@eecs.umich.edu** Changes for SD164. 757997Ssaidi@eecs.umich.edu** 767997Ssaidi@eecs.umich.edu** Revision 1.8 1994/07/08 17:03:48 samberg 777997Ssaidi@eecs.umich.edu** Changes to support platform specific additions 787997Ssaidi@eecs.umich.edu** 797997Ssaidi@eecs.umich.edu** Revision 1.7 1994/05/20 19:23:51 ericr 807997Ssaidi@eecs.umich.edu** Moved STACK_FRAME macro from osfpal.s to here 817997Ssaidi@eecs.umich.edu** 827997Ssaidi@eecs.umich.edu** Revision 1.6 1994/05/20 18:08:19 ericr 837997Ssaidi@eecs.umich.edu** Changed line comments to C++ style comment character 847997Ssaidi@eecs.umich.edu** 857997Ssaidi@eecs.umich.edu** Revision 1.5 1994/01/11 18:43:33 ericr 867997Ssaidi@eecs.umich.edu** Removed PAL version/revision and size constants 877997Ssaidi@eecs.umich.edu** 887997Ssaidi@eecs.umich.edu** Revision 1.4 1994/01/05 16:22:32 ericr 897997Ssaidi@eecs.umich.edu** Added more SCB vector offsets and MCHK error code 907997Ssaidi@eecs.umich.edu** 917997Ssaidi@eecs.umich.edu** Revision 1.3 1994/01/03 19:35:40 ericr 927997Ssaidi@eecs.umich.edu** Derive mask definitions from field constants 937997Ssaidi@eecs.umich.edu** 947997Ssaidi@eecs.umich.edu** Revision 1.2 1993/12/22 20:43:01 eric 957997Ssaidi@eecs.umich.edu** Added mask definitions for MCES bits 967997Ssaidi@eecs.umich.edu** 977997Ssaidi@eecs.umich.edu** Revision 1.1 1993/12/16 21:55:05 eric 987997Ssaidi@eecs.umich.edu** Initial revision 997997Ssaidi@eecs.umich.edu** 1007997Ssaidi@eecs.umich.edu** 1017997Ssaidi@eecs.umich.edu**-- 1027997Ssaidi@eecs.umich.edu*/ 1037997Ssaidi@eecs.umich.edu 1047997Ssaidi@eecs.umich.edu/* 1057997Ssaidi@eecs.umich.edu** Seg0 and Seg1 Virtual Address (VA) Format 1067997Ssaidi@eecs.umich.edu** 1077997Ssaidi@eecs.umich.edu** Loc Size Name Function 1087997Ssaidi@eecs.umich.edu** ----- ---- ---- --------------------------------- 1097997Ssaidi@eecs.umich.edu** <42:33> 10 SEG1 First level page table offset 1107997Ssaidi@eecs.umich.edu** <32:23> 10 SEG2 Second level page table offset 1117997Ssaidi@eecs.umich.edu** <22:13> 10 SEG3 Third level page table offset 1127997Ssaidi@eecs.umich.edu** <12:00> 13 OFFSET Byte within page offset 1137997Ssaidi@eecs.umich.edu*/ 1147997Ssaidi@eecs.umich.edu 1157997Ssaidi@eecs.umich.edu#define VA_V_SEG1 33 1167997Ssaidi@eecs.umich.edu#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) 1177997Ssaidi@eecs.umich.edu#define VA_V_SEG2 23 1187997Ssaidi@eecs.umich.edu#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) 1197997Ssaidi@eecs.umich.edu#define VA_V_SEG3 13 1207997Ssaidi@eecs.umich.edu#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) 1217997Ssaidi@eecs.umich.edu#define VA_V_OFFSET 0 1227997Ssaidi@eecs.umich.edu#define VA_M_OFFSET 0x1FFF 1237997Ssaidi@eecs.umich.edu 1247997Ssaidi@eecs.umich.edu/* 1257997Ssaidi@eecs.umich.edu** Virtual Address Options: 8K byte page size 1267997Ssaidi@eecs.umich.edu*/ 1277997Ssaidi@eecs.umich.edu 1287997Ssaidi@eecs.umich.edu#define VA_S_SIZE 43 1297997Ssaidi@eecs.umich.edu#define VA_S_OFF 13 1307997Ssaidi@eecs.umich.edu#define va_s_off 13 1317997Ssaidi@eecs.umich.edu#define VA_S_SEG 10 1327997Ssaidi@eecs.umich.edu#define VA_S_PAGE_SIZE 8192 1337997Ssaidi@eecs.umich.edu 1347997Ssaidi@eecs.umich.edu/* 1357997Ssaidi@eecs.umich.edu** Page Table Entry (PTE) Format 1367997Ssaidi@eecs.umich.edu** 1377997Ssaidi@eecs.umich.edu** Extent Size Name Function 1387997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 1397997Ssaidi@eecs.umich.edu** <63:32> 32 PFN Page Frame Number 1407997Ssaidi@eecs.umich.edu** <31:16> 16 SW Reserved for software 1417997Ssaidi@eecs.umich.edu** <15:14> 2 RSV0 Reserved for hardware SBZ 1427997Ssaidi@eecs.umich.edu** <13> 1 UWE User Write Enable 1437997Ssaidi@eecs.umich.edu** <12> 1 KWE Kernel Write Enable 1447997Ssaidi@eecs.umich.edu** <11:10> 2 RSV1 Reserved for hardware SBZ 1457997Ssaidi@eecs.umich.edu** <9> 1 URE User Read Enable 1467997Ssaidi@eecs.umich.edu** <8> 1 KRE Kernel Read Enable 1477997Ssaidi@eecs.umich.edu** <7> 1 RSV2 Reserved for hardware SBZ 1487997Ssaidi@eecs.umich.edu** <6:5> 2 GH Granularity Hint 1497997Ssaidi@eecs.umich.edu** <4> 1 ASM Address Space Match 1507997Ssaidi@eecs.umich.edu** <3> 1 FOE Fault On Execute 1517997Ssaidi@eecs.umich.edu** <2> 1 FOW Fault On Write 1527997Ssaidi@eecs.umich.edu** <1> 1 FOR Fault On Read 1537997Ssaidi@eecs.umich.edu** <0> 1 V Valid 1547997Ssaidi@eecs.umich.edu*/ 1557997Ssaidi@eecs.umich.edu 1567997Ssaidi@eecs.umich.edu#define PTE_V_PFN 32 1577997Ssaidi@eecs.umich.edu#define PTE_M_PFN 0xFFFFFFFF00000000 1587997Ssaidi@eecs.umich.edu#define PTE_V_SW 16 1597997Ssaidi@eecs.umich.edu#define PTE_M_SW 0x00000000FFFF0000 1607997Ssaidi@eecs.umich.edu#define PTE_V_UWE 13 1617997Ssaidi@eecs.umich.edu#define PTE_M_UWE (1<<PTE_V_UWE) 1627997Ssaidi@eecs.umich.edu#define PTE_V_KWE 12 1637997Ssaidi@eecs.umich.edu#define PTE_M_KWE (1<<PTE_V_KWE) 1647997Ssaidi@eecs.umich.edu#define PTE_V_URE 9 1657997Ssaidi@eecs.umich.edu#define PTE_M_URE (1<<PTE_V_URE) 1667997Ssaidi@eecs.umich.edu#define PTE_V_KRE 8 1677997Ssaidi@eecs.umich.edu#define PTE_M_KRE (1<<PTE_V_KRE) 1687997Ssaidi@eecs.umich.edu#define PTE_V_GH 5 1697997Ssaidi@eecs.umich.edu#define PTE_M_GH (3<<PTE_V_GH) 1707997Ssaidi@eecs.umich.edu#define PTE_V_ASM 4 1717997Ssaidi@eecs.umich.edu#define PTE_M_ASM (1<<PTE_V_ASM) 1727997Ssaidi@eecs.umich.edu#define PTE_V_FOE 3 1737997Ssaidi@eecs.umich.edu#define PTE_M_FOE (1<<PTE_V_FOE) 1747997Ssaidi@eecs.umich.edu#define PTE_V_FOW 2 1757997Ssaidi@eecs.umich.edu#define PTE_M_FOW (1<<PTE_V_FOW) 1767997Ssaidi@eecs.umich.edu#define PTE_V_FOR 1 1777997Ssaidi@eecs.umich.edu#define PTE_M_FOR (1<<PTE_V_FOR) 1787997Ssaidi@eecs.umich.edu#define PTE_V_VALID 0 1797997Ssaidi@eecs.umich.edu#define PTE_M_VALID (1<<PTE_V_VALID) 1807997Ssaidi@eecs.umich.edu 1817997Ssaidi@eecs.umich.edu#define PTE_M_KSEG 0x1111 1827997Ssaidi@eecs.umich.edu#define PTE_M_PROT 0x3300 1837997Ssaidi@eecs.umich.edu#define pte_m_prot 0x3300 1847997Ssaidi@eecs.umich.edu 1857997Ssaidi@eecs.umich.edu/* 1867997Ssaidi@eecs.umich.edu** System Entry Instruction Fault (entIF) Constants: 1877997Ssaidi@eecs.umich.edu*/ 1887997Ssaidi@eecs.umich.edu 1897997Ssaidi@eecs.umich.edu#define IF_K_BPT 0x0 1907997Ssaidi@eecs.umich.edu#define IF_K_BUGCHK 0x1 1917997Ssaidi@eecs.umich.edu#define IF_K_GENTRAP 0x2 1927997Ssaidi@eecs.umich.edu#define IF_K_FEN 0x3 1937997Ssaidi@eecs.umich.edu#define IF_K_OPCDEC 0x4 1947997Ssaidi@eecs.umich.edu 1957997Ssaidi@eecs.umich.edu/* 1967997Ssaidi@eecs.umich.edu** System Entry Hardware Interrupt (entInt) Constants: 1977997Ssaidi@eecs.umich.edu*/ 1987997Ssaidi@eecs.umich.edu 1997997Ssaidi@eecs.umich.edu#define INT_K_IP 0x0 2007997Ssaidi@eecs.umich.edu#define INT_K_CLK 0x1 2017997Ssaidi@eecs.umich.edu#define INT_K_MCHK 0x2 2027997Ssaidi@eecs.umich.edu#define INT_K_DEV 0x3 2037997Ssaidi@eecs.umich.edu#define INT_K_PERF 0x4 2047997Ssaidi@eecs.umich.edu 2057997Ssaidi@eecs.umich.edu/* 2067997Ssaidi@eecs.umich.edu** System Entry MM Fault (entMM) Constants: 2077997Ssaidi@eecs.umich.edu*/ 2087997Ssaidi@eecs.umich.edu 2097997Ssaidi@eecs.umich.edu#define MM_K_TNV 0x0 2107997Ssaidi@eecs.umich.edu#define MM_K_ACV 0x1 2117997Ssaidi@eecs.umich.edu#define MM_K_FOR 0x2 2127997Ssaidi@eecs.umich.edu#define MM_K_FOE 0x3 2137997Ssaidi@eecs.umich.edu#define MM_K_FOW 0x4 2147997Ssaidi@eecs.umich.edu 2157997Ssaidi@eecs.umich.edu/* 2167997Ssaidi@eecs.umich.edu** Process Control Block (PCB) Offsets: 2177997Ssaidi@eecs.umich.edu*/ 2187997Ssaidi@eecs.umich.edu 2197997Ssaidi@eecs.umich.edu#define PCB_Q_KSP 0x0000 2207997Ssaidi@eecs.umich.edu#define PCB_Q_USP 0x0008 2217997Ssaidi@eecs.umich.edu#define PCB_Q_PTBR 0x0010 2227997Ssaidi@eecs.umich.edu#define PCB_L_PCC 0x0018 2237997Ssaidi@eecs.umich.edu#define PCB_L_ASN 0x001C 2247997Ssaidi@eecs.umich.edu#define PCB_Q_UNIQUE 0x0020 2257997Ssaidi@eecs.umich.edu#define PCB_Q_FEN 0x0028 2267997Ssaidi@eecs.umich.edu#define PCB_Q_RSV0 0x0030 2277997Ssaidi@eecs.umich.edu#define PCB_Q_RSV1 0x0038 2287997Ssaidi@eecs.umich.edu 2297997Ssaidi@eecs.umich.edu/* 2307997Ssaidi@eecs.umich.edu** Processor Status Register (PS) Bit Summary 2317997Ssaidi@eecs.umich.edu** 2327997Ssaidi@eecs.umich.edu** Extent Size Name Function 2337997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 2347997Ssaidi@eecs.umich.edu** <3> 1 CM Current Mode 2357997Ssaidi@eecs.umich.edu** <2:0> 3 IPL Interrupt Priority Level 2367997Ssaidi@eecs.umich.edu**/ 2377997Ssaidi@eecs.umich.edu 2387997Ssaidi@eecs.umich.edu#define PS_V_CM 3 2397997Ssaidi@eecs.umich.edu#define PS_M_CM (1<<PS_V_CM) 2407997Ssaidi@eecs.umich.edu#define PS_V_IPL 0 2417997Ssaidi@eecs.umich.edu#define PS_M_IPL (7<<PS_V_IPL) 2427997Ssaidi@eecs.umich.edu 2437997Ssaidi@eecs.umich.edu#define PS_K_KERN (0<<PS_V_CM) 2447997Ssaidi@eecs.umich.edu#define PS_K_USER (1<<PS_V_CM) 2457997Ssaidi@eecs.umich.edu 2467997Ssaidi@eecs.umich.edu#define IPL_K_ZERO 0x0 2477997Ssaidi@eecs.umich.edu#define IPL_K_SW0 0x1 2487997Ssaidi@eecs.umich.edu#define IPL_K_SW1 0x2 2497997Ssaidi@eecs.umich.edu#define IPL_K_DEV0 0x3 2507997Ssaidi@eecs.umich.edu#define IPL_K_DEV1 0x4 2517997Ssaidi@eecs.umich.edu#define IPL_K_CLK 0x5 2527997Ssaidi@eecs.umich.edu#define IPL_K_RT 0x6 2537997Ssaidi@eecs.umich.edu#define IPL_K_PERF 0x6 2547997Ssaidi@eecs.umich.edu#define IPL_K_PFAIL 0x6 2557997Ssaidi@eecs.umich.edu#define IPL_K_MCHK 0x7 2567997Ssaidi@eecs.umich.edu 2577997Ssaidi@eecs.umich.edu#define IPL_K_LOW 0x0 2587997Ssaidi@eecs.umich.edu#define IPL_K_HIGH 0x7 2597997Ssaidi@eecs.umich.edu 2607997Ssaidi@eecs.umich.edu/* 2617997Ssaidi@eecs.umich.edu** SCB Offset Definitions: 2627997Ssaidi@eecs.umich.edu*/ 2637997Ssaidi@eecs.umich.edu 2647997Ssaidi@eecs.umich.edu#define SCB_Q_FEN 0x0010 2657997Ssaidi@eecs.umich.edu#define SCB_Q_ACV 0x0080 2667997Ssaidi@eecs.umich.edu#define SCB_Q_TNV 0x0090 2677997Ssaidi@eecs.umich.edu#define SCB_Q_FOR 0x00A0 2687997Ssaidi@eecs.umich.edu#define SCB_Q_FOW 0x00B0 2697997Ssaidi@eecs.umich.edu#define SCB_Q_FOE 0x00C0 2707997Ssaidi@eecs.umich.edu#define SCB_Q_ARITH 0x0200 2717997Ssaidi@eecs.umich.edu#define SCB_Q_KAST 0x0240 2727997Ssaidi@eecs.umich.edu#define SCB_Q_EAST 0x0250 2737997Ssaidi@eecs.umich.edu#define SCB_Q_SAST 0x0260 2747997Ssaidi@eecs.umich.edu#define SCB_Q_UAST 0x0270 2757997Ssaidi@eecs.umich.edu#define SCB_Q_UNALIGN 0x0280 2767997Ssaidi@eecs.umich.edu#define SCB_Q_BPT 0x0400 2777997Ssaidi@eecs.umich.edu#define SCB_Q_BUGCHK 0x0410 2787997Ssaidi@eecs.umich.edu#define SCB_Q_OPCDEC 0x0420 2797997Ssaidi@eecs.umich.edu#define SCB_Q_ILLPAL 0x0430 2807997Ssaidi@eecs.umich.edu#define SCB_Q_TRAP 0x0440 2817997Ssaidi@eecs.umich.edu#define SCB_Q_CHMK 0x0480 2827997Ssaidi@eecs.umich.edu#define SCB_Q_CHME 0x0490 2837997Ssaidi@eecs.umich.edu#define SCB_Q_CHMS 0x04A0 2847997Ssaidi@eecs.umich.edu#define SCB_Q_CHMU 0x04B0 2857997Ssaidi@eecs.umich.edu#define SCB_Q_SW0 0x0500 2867997Ssaidi@eecs.umich.edu#define SCB_Q_SW1 0x0510 2877997Ssaidi@eecs.umich.edu#define SCB_Q_SW2 0x0520 2887997Ssaidi@eecs.umich.edu#define SCB_Q_SW3 0x0530 2897997Ssaidi@eecs.umich.edu#define SCB_Q_SW4 0x0540 2907997Ssaidi@eecs.umich.edu#define SCB_Q_SW5 0x0550 2917997Ssaidi@eecs.umich.edu#define SCB_Q_SW6 0x0560 2927997Ssaidi@eecs.umich.edu#define SCB_Q_SW7 0x0570 2937997Ssaidi@eecs.umich.edu#define SCB_Q_SW8 0x0580 2947997Ssaidi@eecs.umich.edu#define SCB_Q_SW9 0x0590 2957997Ssaidi@eecs.umich.edu#define SCB_Q_SW10 0x05A0 2967997Ssaidi@eecs.umich.edu#define SCB_Q_SW11 0x05B0 2977997Ssaidi@eecs.umich.edu#define SCB_Q_SW12 0x05C0 2987997Ssaidi@eecs.umich.edu#define SCB_Q_SW13 0x05D0 2997997Ssaidi@eecs.umich.edu#define SCB_Q_SW14 0x05E0 3007997Ssaidi@eecs.umich.edu#define SCB_Q_SW15 0x05F0 3017997Ssaidi@eecs.umich.edu#define SCB_Q_CLOCK 0x0600 3027997Ssaidi@eecs.umich.edu#define SCB_Q_INTER 0x0610 3037997Ssaidi@eecs.umich.edu#define SCB_Q_SYSERR 0x0620 3047997Ssaidi@eecs.umich.edu#define SCB_Q_PROCERR 0x0630 3057997Ssaidi@eecs.umich.edu#define SCB_Q_PWRFAIL 0x0640 3067997Ssaidi@eecs.umich.edu#define SCB_Q_PERFMON 0x0650 3077997Ssaidi@eecs.umich.edu#define SCB_Q_SYSMCHK 0x0660 3087997Ssaidi@eecs.umich.edu#define SCB_Q_PROCMCHK 0x0670 3097997Ssaidi@eecs.umich.edu#define SCB_Q_PASSREL 0x0680 3107997Ssaidi@eecs.umich.edu 3117997Ssaidi@eecs.umich.edu/* 3127997Ssaidi@eecs.umich.edu** Stack Frame (FRM) Offsets: 3137997Ssaidi@eecs.umich.edu** 3147997Ssaidi@eecs.umich.edu** There are two types of system entries for OSF/1 - those for the 3157997Ssaidi@eecs.umich.edu** callsys CALL_PAL function and those for exceptions and interrupts. 3167997Ssaidi@eecs.umich.edu** Both entry types use the same stack frame layout. The stack frame 3177997Ssaidi@eecs.umich.edu** contains space for the PC, the PS, the saved GP, and the saved 3187997Ssaidi@eecs.umich.edu** argument registers a0, a1, and a2. On entry, SP points to the 3197997Ssaidi@eecs.umich.edu** saved PS. 3207997Ssaidi@eecs.umich.edu*/ 3217997Ssaidi@eecs.umich.edu 3227997Ssaidi@eecs.umich.edu#define FRM_Q_PS 0x0000 3237997Ssaidi@eecs.umich.edu#define FRM_Q_PC 0x0008 3247997Ssaidi@eecs.umich.edu#define FRM_Q_GP 0x0010 3257997Ssaidi@eecs.umich.edu#define FRM_Q_A0 0x0018 3267997Ssaidi@eecs.umich.edu#define FRM_Q_A1 0x0020 3277997Ssaidi@eecs.umich.edu#define FRM_Q_A2 0x0028 3287997Ssaidi@eecs.umich.edu 3297997Ssaidi@eecs.umich.edu#define FRM_K_SIZE 48 3307997Ssaidi@eecs.umich.edu 3317997Ssaidi@eecs.umich.edu#define STACK_FRAME(tmp1,tmp2) \ 3327997Ssaidi@eecs.umich.edu sll ps, 63-PS_V_CM, p7; \ 3337997Ssaidi@eecs.umich.edu bge p7, 0f; \ 3347997Ssaidi@eecs.umich.edu bis zero, zero, ps; \ 3357997Ssaidi@eecs.umich.edu mtpr sp, ptUsp; \ 3367997Ssaidi@eecs.umich.edu mfpr sp, ptKsp; \ 3377997Ssaidi@eecs.umich.edu0: lda sp, 0-FRM_K_SIZE(sp); \ 3387997Ssaidi@eecs.umich.edu stq tmp1, FRM_Q_PS(sp); \ 3397997Ssaidi@eecs.umich.edu stq tmp2, FRM_Q_PC(sp); \ 3407997Ssaidi@eecs.umich.edu stq gp, FRM_Q_GP(sp); \ 3417997Ssaidi@eecs.umich.edu stq a0, FRM_Q_A0(sp); \ 3427997Ssaidi@eecs.umich.edu stq a1, FRM_Q_A1(sp); \ 3437997Ssaidi@eecs.umich.edu stq a2, FRM_Q_A2(sp) 3447997Ssaidi@eecs.umich.edu 3457997Ssaidi@eecs.umich.edu/* 3467997Ssaidi@eecs.umich.edu** Halt Codes: 3477997Ssaidi@eecs.umich.edu*/ 3487997Ssaidi@eecs.umich.edu 3497997Ssaidi@eecs.umich.edu#define HLT_K_RESET 0x0000 3507997Ssaidi@eecs.umich.edu#define HLT_K_HW_HALT 0x0001 3517997Ssaidi@eecs.umich.edu#define HLT_K_KSP_INVAL 0x0002 3527997Ssaidi@eecs.umich.edu#define HLT_K_SCBB_INVAL 0x0003 3537997Ssaidi@eecs.umich.edu#define HLT_K_PTBR_INVAL 0x0004 3547997Ssaidi@eecs.umich.edu#define HLT_K_SW_HALT 0x0005 3557997Ssaidi@eecs.umich.edu#define HLT_K_DBL_MCHK 0x0006 3567997Ssaidi@eecs.umich.edu#define HLT_K_MCHK_FROM_PAL 0x0007 3577997Ssaidi@eecs.umich.edu 3587997Ssaidi@eecs.umich.edu/* 3597997Ssaidi@eecs.umich.edu** Machine Check Codes: 3607997Ssaidi@eecs.umich.edu*/ 3617997Ssaidi@eecs.umich.edu 3627997Ssaidi@eecs.umich.edu#define MCHK_K_TPERR 0x0080 3637997Ssaidi@eecs.umich.edu#define MCHK_K_TCPERR 0x0082 3647997Ssaidi@eecs.umich.edu#define MCHK_K_HERR 0x0084 3657997Ssaidi@eecs.umich.edu#define MCHK_K_ECC_C 0x0086 3667997Ssaidi@eecs.umich.edu#define MCHK_K_ECC_NC 0x0088 3677997Ssaidi@eecs.umich.edu#define MCHK_K_UNKNOWN 0x008A 3687997Ssaidi@eecs.umich.edu#define MCHK_K_CACKSOFT 0x008C 3697997Ssaidi@eecs.umich.edu#define MCHK_K_BUGCHECK 0x008E 3707997Ssaidi@eecs.umich.edu#define MCHK_K_OS_BUGCHECK 0x0090 3717997Ssaidi@eecs.umich.edu#define MCHK_K_DCPERR 0x0092 3727997Ssaidi@eecs.umich.edu#define MCHK_K_ICPERR 0x0094 3737997Ssaidi@eecs.umich.edu#define MCHK_K_RETRY_IRD 0x0096 3747997Ssaidi@eecs.umich.edu#define MCHK_K_PROC_HERR 0x0098 3757997Ssaidi@eecs.umich.edu 3767997Ssaidi@eecs.umich.edu/* 3777997Ssaidi@eecs.umich.edu** System Machine Check Codes: 3787997Ssaidi@eecs.umich.edu*/ 3797997Ssaidi@eecs.umich.edu 3807997Ssaidi@eecs.umich.edu#define MCHK_K_READ_NXM 0x0200 3817997Ssaidi@eecs.umich.edu#define MCHK_K_SYS_HERR 0x0202 3827997Ssaidi@eecs.umich.edu 3837997Ssaidi@eecs.umich.edu/* 3847997Ssaidi@eecs.umich.edu** Machine Check Error Status Summary (MCES) Register Format 3857997Ssaidi@eecs.umich.edu** 3867997Ssaidi@eecs.umich.edu** Extent Size Name Function 3877997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 3887997Ssaidi@eecs.umich.edu** <0> 1 MIP Machine check in progress 3897997Ssaidi@eecs.umich.edu** <1> 1 SCE System correctable error in progress 3907997Ssaidi@eecs.umich.edu** <2> 1 PCE Processor correctable error in progress 3917997Ssaidi@eecs.umich.edu** <3> 1 DPC Disable PCE error reporting 3927997Ssaidi@eecs.umich.edu** <4> 1 DSC Disable SCE error reporting 3937997Ssaidi@eecs.umich.edu*/ 3947997Ssaidi@eecs.umich.edu 3957997Ssaidi@eecs.umich.edu#define MCES_V_MIP 0 3967997Ssaidi@eecs.umich.edu#define MCES_M_MIP (1<<MCES_V_MIP) 3977997Ssaidi@eecs.umich.edu#define MCES_V_SCE 1 3987997Ssaidi@eecs.umich.edu#define MCES_M_SCE (1<<MCES_V_SCE) 3997997Ssaidi@eecs.umich.edu#define MCES_V_PCE 2 4007997Ssaidi@eecs.umich.edu#define MCES_M_PCE (1<<MCES_V_PCE) 4017997Ssaidi@eecs.umich.edu#define MCES_V_DPC 3 4027997Ssaidi@eecs.umich.edu#define MCES_M_DPC (1<<MCES_V_DPC) 4037997Ssaidi@eecs.umich.edu#define MCES_V_DSC 4 4047997Ssaidi@eecs.umich.edu#define MCES_M_DSC (1<<MCES_V_DSC) 4057997Ssaidi@eecs.umich.edu 4067997Ssaidi@eecs.umich.edu#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ 4077997Ssaidi@eecs.umich.edu | MCES_M_DSC) 4087997Ssaidi@eecs.umich.edu 4097997Ssaidi@eecs.umich.edu/* 4107997Ssaidi@eecs.umich.edu** Who-Am-I (WHAMI) Register Format 4117997Ssaidi@eecs.umich.edu** 4127997Ssaidi@eecs.umich.edu** Extent Size Name Function 4137997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 4147997Ssaidi@eecs.umich.edu** <7:0> 8 ID Who-Am-I identifier 4157997Ssaidi@eecs.umich.edu** <15:8> 1 SWAP Swap PALcode flag - character 'S' 4167997Ssaidi@eecs.umich.edu*/ 4177997Ssaidi@eecs.umich.edu 4187997Ssaidi@eecs.umich.edu#define WHAMI_V_SWAP 8 4197997Ssaidi@eecs.umich.edu#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) 4207997Ssaidi@eecs.umich.edu#define WHAMI_V_ID 0 4217997Ssaidi@eecs.umich.edu#define WHAMI_M_ID 0xFF 4227997Ssaidi@eecs.umich.edu 4237997Ssaidi@eecs.umich.edu#define WHAMI_K_SWAP 0x53 /* Character 'S' */ 4247997Ssaidi@eecs.umich.edu 4257997Ssaidi@eecs.umich.edu/* 4267997Ssaidi@eecs.umich.edu** Conventional Register Usage Definitions 4277997Ssaidi@eecs.umich.edu** 4287997Ssaidi@eecs.umich.edu** Assembler temporary `at' is `AT' so it doesn't conflict with the 4297997Ssaidi@eecs.umich.edu** `.set at' assembler directive. 4307997Ssaidi@eecs.umich.edu*/ 4317997Ssaidi@eecs.umich.edu 4327997Ssaidi@eecs.umich.edu#define v0 $0 /* Function Return Value Register */ 4337997Ssaidi@eecs.umich.edu#define t0 $1 /* Scratch (Temporary) Registers ... */ 4347997Ssaidi@eecs.umich.edu#define t1 $2 4357997Ssaidi@eecs.umich.edu#define t2 $3 4367997Ssaidi@eecs.umich.edu#define t3 $4 4377997Ssaidi@eecs.umich.edu#define t4 $5 4387997Ssaidi@eecs.umich.edu#define t5 $6 4397997Ssaidi@eecs.umich.edu#define t6 $7 4407997Ssaidi@eecs.umich.edu#define t7 $8 4417997Ssaidi@eecs.umich.edu#define s0 $9 /* Saved (Non-Volatile) Registers ... */ 4427997Ssaidi@eecs.umich.edu#define s1 $10 4437997Ssaidi@eecs.umich.edu#define s2 $11 4447997Ssaidi@eecs.umich.edu#define s3 $12 4457997Ssaidi@eecs.umich.edu#define s4 $13 4467997Ssaidi@eecs.umich.edu#define s5 $14 4477997Ssaidi@eecs.umich.edu#define fp $15 /* Frame Pointer Register, Or S6 */ 4487997Ssaidi@eecs.umich.edu#define s6 $15 4497997Ssaidi@eecs.umich.edu#define a0 $16 /* Argument Registers ... */ 4507997Ssaidi@eecs.umich.edu#define a1 $17 4517997Ssaidi@eecs.umich.edu#define a2 $18 4527997Ssaidi@eecs.umich.edu#define a3 $19 4537997Ssaidi@eecs.umich.edu#define a4 $20 4547997Ssaidi@eecs.umich.edu#define a5 $21 4557997Ssaidi@eecs.umich.edu#define t8 $22 /* Scratch (Temporary) Registers ... */ 4567997Ssaidi@eecs.umich.edu#define t9 $23 4577997Ssaidi@eecs.umich.edu#define t10 $24 4587997Ssaidi@eecs.umich.edu#define t11 $25 4597997Ssaidi@eecs.umich.edu#define ra $26 /* Return Address Register */ 4607997Ssaidi@eecs.umich.edu#define pv $27 /* Procedure Value Register, Or T12 */ 4617997Ssaidi@eecs.umich.edu#define t12 $27 4627997Ssaidi@eecs.umich.edu#define AT $28 /* Assembler Temporary (Volatile) Register */ 4637997Ssaidi@eecs.umich.edu#define gp $29 /* Global Pointer Register */ 4647997Ssaidi@eecs.umich.edu#define sp $30 /* Stack Pointer Register */ 4657997Ssaidi@eecs.umich.edu#define zero $31 /* Zero Register */ 4667997Ssaidi@eecs.umich.edu 4677997Ssaidi@eecs.umich.edu/* 4687997Ssaidi@eecs.umich.edu** OSF/1 Unprivileged CALL_PAL Entry Offsets: 4697997Ssaidi@eecs.umich.edu** 4707997Ssaidi@eecs.umich.edu** Entry Name Offset (Hex) 4717997Ssaidi@eecs.umich.edu** 4727997Ssaidi@eecs.umich.edu** bpt 0080 4737997Ssaidi@eecs.umich.edu** bugchk 0081 4747997Ssaidi@eecs.umich.edu** callsys 0083 4757997Ssaidi@eecs.umich.edu** imb 0086 4767997Ssaidi@eecs.umich.edu** rdunique 009E 4777997Ssaidi@eecs.umich.edu** wrunique 009F 4787997Ssaidi@eecs.umich.edu** gentrap 00AA 4797997Ssaidi@eecs.umich.edu** dbgstop 00AD 4807997Ssaidi@eecs.umich.edu*/ 4817997Ssaidi@eecs.umich.edu 4827997Ssaidi@eecs.umich.edu#define UNPRIV 0x80 4837997Ssaidi@eecs.umich.edu#define PAL_BPT_ENTRY 0x80 4847997Ssaidi@eecs.umich.edu#define PAL_BUGCHK_ENTRY 0x81 4857997Ssaidi@eecs.umich.edu#define PAL_CALLSYS_ENTRY 0x83 4867997Ssaidi@eecs.umich.edu#define PAL_IMB_ENTRY 0x86 4877997Ssaidi@eecs.umich.edu#define PAL_RDUNIQUE_ENTRY 0x9E 4887997Ssaidi@eecs.umich.edu#define PAL_WRUNIQUE_ENTRY 0x9F 4897997Ssaidi@eecs.umich.edu#define PAL_GENTRAP_ENTRY 0xAA 4907997Ssaidi@eecs.umich.edu 4917997Ssaidi@eecs.umich.edu#if defined(KDEBUG) 4927997Ssaidi@eecs.umich.edu#define PAL_DBGSTOP_ENTRY 0xAD 4937997Ssaidi@eecs.umich.edu/* #define NUM_UNPRIV_CALL_PALS 10 */ 4947997Ssaidi@eecs.umich.edu#else 4957997Ssaidi@eecs.umich.edu/* #define NUM_UNPRIV_CALL_PALS 9 */ 4967997Ssaidi@eecs.umich.edu#endif /* KDEBUG */ 4977997Ssaidi@eecs.umich.edu 4987997Ssaidi@eecs.umich.edu/* 4997997Ssaidi@eecs.umich.edu** OSF/1 Privileged CALL_PAL Entry Offsets: 5007997Ssaidi@eecs.umich.edu** 5017997Ssaidi@eecs.umich.edu** Entry Name Offset (Hex) 5027997Ssaidi@eecs.umich.edu** 5037997Ssaidi@eecs.umich.edu** halt 0000 5047997Ssaidi@eecs.umich.edu** cflush 0001 5057997Ssaidi@eecs.umich.edu** draina 0002 5067997Ssaidi@eecs.umich.edu** cserve 0009 5077997Ssaidi@eecs.umich.edu** swppal 000A 5087997Ssaidi@eecs.umich.edu** rdmces 0010 5097997Ssaidi@eecs.umich.edu** wrmces 0011 5107997Ssaidi@eecs.umich.edu** wrfen 002B 5117997Ssaidi@eecs.umich.edu** wrvptptr 002D 5127997Ssaidi@eecs.umich.edu** swpctx 0030 5137997Ssaidi@eecs.umich.edu** wrval 0031 5147997Ssaidi@eecs.umich.edu** rdval 0032 5157997Ssaidi@eecs.umich.edu** tbi 0033 5167997Ssaidi@eecs.umich.edu** wrent 0034 5177997Ssaidi@eecs.umich.edu** swpipl 0035 5187997Ssaidi@eecs.umich.edu** rdps 0036 5197997Ssaidi@eecs.umich.edu** wrkgp 0037 5207997Ssaidi@eecs.umich.edu** wrusp 0038 5217997Ssaidi@eecs.umich.edu** rdusp 003A 5227997Ssaidi@eecs.umich.edu** whami 003C 5237997Ssaidi@eecs.umich.edu** retsys 003D 5247997Ssaidi@eecs.umich.edu** rti 003F 5257997Ssaidi@eecs.umich.edu*/ 5267997Ssaidi@eecs.umich.edu 5277997Ssaidi@eecs.umich.edu#define PAL_HALT_ENTRY 0x0000 5287997Ssaidi@eecs.umich.edu#define PAL_CFLUSH_ENTRY 0x0001 5297997Ssaidi@eecs.umich.edu#define PAL_DRAINA_ENTRY 0x0002 5307997Ssaidi@eecs.umich.edu#define PAL_CSERVE_ENTRY 0x0009 5317997Ssaidi@eecs.umich.edu#define PAL_SWPPAL_ENTRY 0x000A 5327997Ssaidi@eecs.umich.edu#define PAL_WRIPIR_ENTRY 0x000D 5337997Ssaidi@eecs.umich.edu#define PAL_RDMCES_ENTRY 0x0010 5347997Ssaidi@eecs.umich.edu#define PAL_WRMCES_ENTRY 0x0011 5357997Ssaidi@eecs.umich.edu#define PAL_WRFEN_ENTRY 0x002B 5367997Ssaidi@eecs.umich.edu#define PAL_WRVPTPTR_ENTRY 0x002D 5377997Ssaidi@eecs.umich.edu#define PAL_SWPCTX_ENTRY 0x0030 5387997Ssaidi@eecs.umich.edu#define PAL_WRVAL_ENTRY 0x0031 5397997Ssaidi@eecs.umich.edu#define PAL_RDVAL_ENTRY 0x0032 5407997Ssaidi@eecs.umich.edu#define PAL_TBI_ENTRY 0x0033 5417997Ssaidi@eecs.umich.edu#define PAL_WRENT_ENTRY 0x0034 5427997Ssaidi@eecs.umich.edu#define PAL_SWPIPL_ENTRY 0x0035 5437997Ssaidi@eecs.umich.edu#define PAL_RDPS_ENTRY 0x0036 5447997Ssaidi@eecs.umich.edu#define PAL_WRKGP_ENTRY 0x0037 5457997Ssaidi@eecs.umich.edu#define PAL_WRUSP_ENTRY 0x0038 5467997Ssaidi@eecs.umich.edu#define PAL_RDUSP_ENTRY 0x003A 5477997Ssaidi@eecs.umich.edu#define PAL_WHAMI_ENTRY 0x003C 5487997Ssaidi@eecs.umich.edu#define PAL_RETSYS_ENTRY 0x003D 5497997Ssaidi@eecs.umich.edu#define PAL_RTI_ENTRY 0x003F 5507997Ssaidi@eecs.umich.edu 5517997Ssaidi@eecs.umich.edu#define NUM_PRIV_CALL_PALS 23 5527997Ssaidi@eecs.umich.edu 5537997Ssaidi@eecs.umich.edu#endif 5547997Ssaidi@eecs.umich.edu 555