ev5_defs.h revision 8029
18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 1995 The Hewlett-Packard Development Company 38029Snate@binkert.org * All rights reserved. 48013Sbinkertn@umich.edu * 58029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 68029Snate@binkert.org * modification, are permitted provided that the following conditions are 78029Snate@binkert.org * met: redistributions of source code must retain the above copyright 88029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 98029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 108029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 118029Snate@binkert.org * documentation and/or other materials provided with the distribution; 128029Snate@binkert.org * neither the name of the copyright holders nor the names of its 138029Snate@binkert.org * contributors may be used to endorse or promote products derived from 148029Snate@binkert.org * this software without specific prior written permission. 158013Sbinkertn@umich.edu * 168029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278013Sbinkertn@umich.edu */ 288012Ssaidi@eecs.umich.edu 297997Ssaidi@eecs.umich.edu#ifndef EV5_DEFS_INCLUDED 307997Ssaidi@eecs.umich.edu#define EV5_DEFS_INCLUDED 1 317997Ssaidi@eecs.umich.edu 327997Ssaidi@eecs.umich.edu// adapted from the version emailed to lance..pb Nov/95 337997Ssaidi@eecs.umich.edu 348013Sbinkertn@umich.edu// In the definitions below, registers are annotated with one of the 358013Sbinkertn@umich.edu// following symbols: 367997Ssaidi@eecs.umich.edu// 378013Sbinkertn@umich.edu// RW - The register may be read and written 387997Ssaidi@eecs.umich.edu// RO - The register may only be read 397997Ssaidi@eecs.umich.edu// WO - The register may only be written 407997Ssaidi@eecs.umich.edu// 418013Sbinkertn@umich.edu// For RO and WO registers, all bits and fields within the register 428013Sbinkertn@umich.edu// are also read-only or write-only. For RW registers, each bit or 438013Sbinkertn@umich.edu// field within the register is annotated with one of the following: 447997Ssaidi@eecs.umich.edu// 457997Ssaidi@eecs.umich.edu// RW - The bit/field may be read and written 467997Ssaidi@eecs.umich.edu// RO - The bit/field may be read; writes are ignored 478013Sbinkertn@umich.edu// WO - The bit/field may be written; reads return an UNPREDICTABLE result 487997Ssaidi@eecs.umich.edu// WZ - The bit/field may be written; reads return a 0 497997Ssaidi@eecs.umich.edu// WC - The bit/field may be read; writes cause state to clear 508013Sbinkertn@umich.edu// RC - The bit/field may be read, which also causes state to clear; 518013Sbinkertn@umich.edu// writes are ignored 527997Ssaidi@eecs.umich.edu// Architecturally-defined (SRM) registers for EVMS 538013Sbinkertn@umich.edu 547997Ssaidi@eecs.umich.edu#define pt0 320 557997Ssaidi@eecs.umich.edu#define pt1 321 567997Ssaidi@eecs.umich.edu#define pt2 322 577997Ssaidi@eecs.umich.edu#define pt3 323 587997Ssaidi@eecs.umich.edu#define pt4 324 597997Ssaidi@eecs.umich.edu#define pt5 325 607997Ssaidi@eecs.umich.edu#define pt6 326 617997Ssaidi@eecs.umich.edu#define pt7 327 627997Ssaidi@eecs.umich.edu#define pt8 328 637997Ssaidi@eecs.umich.edu#define pt9 329 647997Ssaidi@eecs.umich.edu#define pt10 330 657997Ssaidi@eecs.umich.edu#define pt11 331 667997Ssaidi@eecs.umich.edu#define pt12 332 677997Ssaidi@eecs.umich.edu#define pt13 333 687997Ssaidi@eecs.umich.edu#define pt14 334 697997Ssaidi@eecs.umich.edu#define pt15 335 707997Ssaidi@eecs.umich.edu#define pt16 336 717997Ssaidi@eecs.umich.edu#define pt17 337 727997Ssaidi@eecs.umich.edu#define pt18 338 737997Ssaidi@eecs.umich.edu#define pt19 339 747997Ssaidi@eecs.umich.edu#define pt20 340 757997Ssaidi@eecs.umich.edu#define pt21 341 767997Ssaidi@eecs.umich.edu#define pt22 342 777997Ssaidi@eecs.umich.edu#define pt23 343 787997Ssaidi@eecs.umich.edu#define cbox_ipr_offset 16777200 797997Ssaidi@eecs.umich.edu#define sc_ctl 168 807997Ssaidi@eecs.umich.edu#define sc_stat 232 817997Ssaidi@eecs.umich.edu#define sc_addr 392 827997Ssaidi@eecs.umich.edu#define sc_addr_nm 392 837997Ssaidi@eecs.umich.edu#define sc_addr_fhm 392 847997Ssaidi@eecs.umich.edu#define bc_ctl 296 857997Ssaidi@eecs.umich.edu#define bc_config 456 867997Ssaidi@eecs.umich.edu#define ei_stat 360 877997Ssaidi@eecs.umich.edu#define ei_addr 328 887997Ssaidi@eecs.umich.edu#define fill_syn 104 897997Ssaidi@eecs.umich.edu#define bc_tag_addr 264 907997Ssaidi@eecs.umich.edu#define ld_lock 488 917997Ssaidi@eecs.umich.edu#define aster 266 927997Ssaidi@eecs.umich.edu#define astrr 265 937997Ssaidi@eecs.umich.edu#define exc_addr 267 947997Ssaidi@eecs.umich.edu#define exc_sum 268 957997Ssaidi@eecs.umich.edu#define exc_mask 269 967997Ssaidi@eecs.umich.edu#define hwint_clr 277 977997Ssaidi@eecs.umich.edu#define ic_flush_ctl 281 987997Ssaidi@eecs.umich.edu#define icperr_stat 282 997997Ssaidi@eecs.umich.edu#define ic_perr_stat 282 1007997Ssaidi@eecs.umich.edu#define ic_row_map 283 1017997Ssaidi@eecs.umich.edu#define icsr 280 1027997Ssaidi@eecs.umich.edu#define ifault_va_form 274 1037997Ssaidi@eecs.umich.edu#define intid 273 1047997Ssaidi@eecs.umich.edu#define ipl 272 1057997Ssaidi@eecs.umich.edu#define isr 256 1067997Ssaidi@eecs.umich.edu#define itb_is 263 1077997Ssaidi@eecs.umich.edu#define itb_asn 259 1087997Ssaidi@eecs.umich.edu#define itb_ia 261 1097997Ssaidi@eecs.umich.edu#define itb_iap 262 1107997Ssaidi@eecs.umich.edu#define itb_pte 258 1117997Ssaidi@eecs.umich.edu#define itb_pte_temp 260 1127997Ssaidi@eecs.umich.edu#define itb_tag 257 1137997Ssaidi@eecs.umich.edu#define ivptbr 275 1147997Ssaidi@eecs.umich.edu#define pal_base 270 1157997Ssaidi@eecs.umich.edu#define pmctr 284 1167997Ssaidi@eecs.umich.edu// this is not the register ps .. pb #define ps 271 1177997Ssaidi@eecs.umich.edu#define sirr 264 1187997Ssaidi@eecs.umich.edu#define sl_txmit 278 1197997Ssaidi@eecs.umich.edu#define sl_rcv 279 1207997Ssaidi@eecs.umich.edu#define alt_mode 524 1217997Ssaidi@eecs.umich.edu#define cc 525 1227997Ssaidi@eecs.umich.edu#define cc_ctl 526 1237997Ssaidi@eecs.umich.edu#define dc_flush 528 1247997Ssaidi@eecs.umich.edu#define dcperr_stat 530 1257997Ssaidi@eecs.umich.edu#define dc_test_ctl 531 1267997Ssaidi@eecs.umich.edu#define dc_test_tag 532 1277997Ssaidi@eecs.umich.edu#define dc_test_tag_temp 533 1287997Ssaidi@eecs.umich.edu#define dtb_asn 512 1297997Ssaidi@eecs.umich.edu#define dtb_cm 513 1307997Ssaidi@eecs.umich.edu#define dtb_ia 522 1317997Ssaidi@eecs.umich.edu#define dtb_iap 521 1327997Ssaidi@eecs.umich.edu#define dtb_is 523 1337997Ssaidi@eecs.umich.edu#define dtb_pte 515 1347997Ssaidi@eecs.umich.edu#define dtb_pte_temp 516 1357997Ssaidi@eecs.umich.edu#define dtb_tag 514 1367997Ssaidi@eecs.umich.edu#define mcsr 527 1377997Ssaidi@eecs.umich.edu#define dc_mode 534 1387997Ssaidi@eecs.umich.edu#define maf_mode 535 1397997Ssaidi@eecs.umich.edu#define mm_stat 517 1407997Ssaidi@eecs.umich.edu#define mvptbr 520 1417997Ssaidi@eecs.umich.edu#define va 518 1427997Ssaidi@eecs.umich.edu#define va_form 519 1437997Ssaidi@eecs.umich.edu#define ev5_srm__ps 0 1447997Ssaidi@eecs.umich.edu#define ev5_srm__pc 0 1457997Ssaidi@eecs.umich.edu#define ev5_srm__asten 0 1467997Ssaidi@eecs.umich.edu#define ev5_srm__astsr 0 1477997Ssaidi@eecs.umich.edu#define ev5_srm__ipir 0 1487997Ssaidi@eecs.umich.edu#define ev5_srm__ipl 0 1497997Ssaidi@eecs.umich.edu#define ev5_srm__mces 0 1507997Ssaidi@eecs.umich.edu#define ev5_srm__pcbb 0 1517997Ssaidi@eecs.umich.edu#define ev5_srm__prbr 0 1527997Ssaidi@eecs.umich.edu#define ev5_srm__ptbr 0 1537997Ssaidi@eecs.umich.edu#define ev5_srm__scbb 0 1547997Ssaidi@eecs.umich.edu#define ev5_srm__sirr 0 1557997Ssaidi@eecs.umich.edu#define ev5_srm__sisr 0 1567997Ssaidi@eecs.umich.edu#define ev5_srm__tbchk 0 1577997Ssaidi@eecs.umich.edu#define ev5_srm__tb1a 0 1587997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ap 0 1597997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ad 0 1607997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ai 0 1617997Ssaidi@eecs.umich.edu#define ev5_srm__tbis 0 1627997Ssaidi@eecs.umich.edu#define ev5_srm__ksp 0 1637997Ssaidi@eecs.umich.edu#define ev5_srm__esp 0 1647997Ssaidi@eecs.umich.edu#define ev5_srm__ssp 0 1657997Ssaidi@eecs.umich.edu#define ev5_srm__usp 0 1667997Ssaidi@eecs.umich.edu#define ev5_srm__vptb 0 1677997Ssaidi@eecs.umich.edu#define ev5_srm__whami 0 1687997Ssaidi@eecs.umich.edu#define ev5_srm__cc 0 1697997Ssaidi@eecs.umich.edu#define ev5_srm__unq 0 1707997Ssaidi@eecs.umich.edu// processor-specific iprs. 1717997Ssaidi@eecs.umich.edu#define ev5__sc_ctl 168 1727997Ssaidi@eecs.umich.edu#define ev5__sc_stat 232 1737997Ssaidi@eecs.umich.edu#define ev5__sc_addr 392 1747997Ssaidi@eecs.umich.edu#define ev5__bc_ctl 296 1757997Ssaidi@eecs.umich.edu#define ev5__bc_config 456 1767997Ssaidi@eecs.umich.edu#define bc_config_k_size_1mb 1 1777997Ssaidi@eecs.umich.edu#define bc_config_k_size_2mb 2 1787997Ssaidi@eecs.umich.edu#define bc_config_k_size_4mb 3 1797997Ssaidi@eecs.umich.edu#define bc_config_k_size_8mb 4 1807997Ssaidi@eecs.umich.edu#define bc_config_k_size_16mb 5 1817997Ssaidi@eecs.umich.edu#define bc_config_k_size_32mb 6 1827997Ssaidi@eecs.umich.edu#define bc_config_k_size_64mb 7 1837997Ssaidi@eecs.umich.edu#define ev5__ei_stat 360 1847997Ssaidi@eecs.umich.edu#define ev5__ei_addr 328 1857997Ssaidi@eecs.umich.edu#define ev5__fill_syn 104 1867997Ssaidi@eecs.umich.edu#define ev5__bc_tag_addr 264 1877997Ssaidi@eecs.umich.edu#define ev5__aster 266 1887997Ssaidi@eecs.umich.edu#define ev5__astrr 265 1897997Ssaidi@eecs.umich.edu#define ev5__exc_addr 267 1907997Ssaidi@eecs.umich.edu#define exc_addr_v_pa 2 1917997Ssaidi@eecs.umich.edu#define exc_addr_s_pa 62 1927997Ssaidi@eecs.umich.edu#define ev5__exc_sum 268 1937997Ssaidi@eecs.umich.edu#define ev5__exc_mask 269 1947997Ssaidi@eecs.umich.edu#define ev5__hwint_clr 277 1957997Ssaidi@eecs.umich.edu#define ev5__ic_flush_ctl 281 1967997Ssaidi@eecs.umich.edu#define ev5__icperr_stat 282 1977997Ssaidi@eecs.umich.edu#define ev5__ic_perr_stat 282 1987997Ssaidi@eecs.umich.edu#define ev5__ic_row_map 283 1997997Ssaidi@eecs.umich.edu#define ev5__icsr 280 2007997Ssaidi@eecs.umich.edu#define ev5__ifault_va_form 274 2017997Ssaidi@eecs.umich.edu#define ev5__ifault_va_form_nt 274 2027997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_v_vptb 30 2037997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_s_vptb 34 2047997Ssaidi@eecs.umich.edu#define ev5__intid 273 2057997Ssaidi@eecs.umich.edu#define ev5__ipl 272 2067997Ssaidi@eecs.umich.edu#define ev5__itb_is 263 2077997Ssaidi@eecs.umich.edu#define ev5__itb_asn 259 2087997Ssaidi@eecs.umich.edu#define ev5__itb_ia 261 2097997Ssaidi@eecs.umich.edu#define ev5__itb_iap 262 2107997Ssaidi@eecs.umich.edu#define ev5__itb_pte 258 2117997Ssaidi@eecs.umich.edu#define ev5__itb_pte_temp 260 2127997Ssaidi@eecs.umich.edu#define ev5__itb_tag 257 2137997Ssaidi@eecs.umich.edu#define ev5__ivptbr 275 2147997Ssaidi@eecs.umich.edu#define ivptbr_v_vptb 30 2157997Ssaidi@eecs.umich.edu#define ivptbr_s_vptb 34 2167997Ssaidi@eecs.umich.edu#define ev5__pal_base 270 2177997Ssaidi@eecs.umich.edu#define ev5__pmctr 284 2187997Ssaidi@eecs.umich.edu#define ev5__ps 271 2197997Ssaidi@eecs.umich.edu#define ev5__isr 256 2207997Ssaidi@eecs.umich.edu#define ev5__sirr 264 2217997Ssaidi@eecs.umich.edu#define ev5__sl_txmit 278 2227997Ssaidi@eecs.umich.edu#define ev5__sl_rcv 279 2237997Ssaidi@eecs.umich.edu#define ev5__alt_mode 524 2247997Ssaidi@eecs.umich.edu#define ev5__cc 525 2257997Ssaidi@eecs.umich.edu#define ev5__cc_ctl 526 2267997Ssaidi@eecs.umich.edu#define ev5__dc_flush 528 2277997Ssaidi@eecs.umich.edu#define ev5__dcperr_stat 530 2287997Ssaidi@eecs.umich.edu#define ev5__dc_test_ctl 531 2297997Ssaidi@eecs.umich.edu#define ev5__dc_test_tag 532 2307997Ssaidi@eecs.umich.edu#define ev5__dc_test_tag_temp 533 2317997Ssaidi@eecs.umich.edu#define ev5__dtb_asn 512 2327997Ssaidi@eecs.umich.edu#define ev5__dtb_cm 513 2337997Ssaidi@eecs.umich.edu#define ev5__dtb_ia 522 2347997Ssaidi@eecs.umich.edu#define ev5__dtb_iap 521 2357997Ssaidi@eecs.umich.edu#define ev5__dtb_is 523 2367997Ssaidi@eecs.umich.edu#define ev5__dtb_pte 515 2377997Ssaidi@eecs.umich.edu#define ev5__dtb_pte_temp 516 2387997Ssaidi@eecs.umich.edu#define ev5__dtb_tag 514 2397997Ssaidi@eecs.umich.edu#define ev5__mcsr 527 2407997Ssaidi@eecs.umich.edu#define ev5__dc_mode 534 2417997Ssaidi@eecs.umich.edu#define ev5__maf_mode 535 2427997Ssaidi@eecs.umich.edu#define ev5__mm_stat 517 2437997Ssaidi@eecs.umich.edu#define ev5__mvptbr 520 2447997Ssaidi@eecs.umich.edu#define ev5__va 518 2457997Ssaidi@eecs.umich.edu#define ev5__va_form 519 2467997Ssaidi@eecs.umich.edu#define ev5__va_form_nt 519 2477997Ssaidi@eecs.umich.edu#define va_form_nt_s_va 19 2487997Ssaidi@eecs.umich.edu#define va_form_nt_v_vptb 30 2497997Ssaidi@eecs.umich.edu#define va_form_nt_s_vptb 34 2507997Ssaidi@eecs.umich.edu#define ev5s_ev5_def 10 2517997Ssaidi@eecs.umich.edu#define ev5_def 0 2527997Ssaidi@eecs.umich.edu// cbox registers. 2537997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_fhit 0 2547997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_flush 1 2557997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_tag_stat 6 2567997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_tag_stat 2 2577997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_fb_dp 4 2587997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_fb_dp 8 2597997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_blk_size 12 2607997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_set_en 3 2617997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_set_en 13 2627997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_soft_repair 3 2637997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_soft_repair 16 2647997Ssaidi@eecs.umich.edu#define sc_stat_s_sc_tperr 3 2657997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_tperr 0 2667997Ssaidi@eecs.umich.edu#define sc_stat_s_sc_dperr 8 2677997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_dperr 3 2687997Ssaidi@eecs.umich.edu#define sc_stat_s_cbox_cmd 5 2697997Ssaidi@eecs.umich.edu#define sc_stat_v_cbox_cmd 11 2707997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_scnd_err 16 2717997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_sc_tag_parity 4 2727997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_stat_sb0 3 2737997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_stat_sb0 5 2747997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_stat_sb1 3 2757997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_stat_sb1 8 2767997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_ow_mod0 2 2777997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_ow_mod0 11 2787997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_ow_mod1 2 2797997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_ow_mod1 13 2807997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_lo 17 2817997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_lo 15 2827997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_hi 7 2837997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_hi 32 2847997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_enabled 0 2857997Ssaidi@eecs.umich.edu#define bc_ctl_v_alloc_cyc 1 2867997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_opt_cmd 2 2877997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_opt_cmd_mb 3 2887997Ssaidi@eecs.umich.edu#define bc_ctl_v_corr_fill_dat 4 2897997Ssaidi@eecs.umich.edu#define bc_ctl_v_vtm_first 5 2907997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_ecc_or_parity 6 2917997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_fhit 7 2927997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_tag_stat 5 2937997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_tag_stat 8 2947997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_bad_dat 2 2957997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_bad_dat 13 2967997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_dis_err 15 2977997Ssaidi@eecs.umich.edu#define bc_ctl_v_tl_pipe_latch 16 2987997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_wave_pipe 2 2997997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_wave_pipe 17 3007997Ssaidi@eecs.umich.edu#define bc_ctl_s_pm_mux_sel 6 3017997Ssaidi@eecs.umich.edu#define bc_ctl_v_pm_mux_sel 19 3027997Ssaidi@eecs.umich.edu#define bc_ctl_v_dbg_mux_sel 25 3037997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_baf_byp 26 3047997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_sc_vic_buf 27 3057997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_sys_addr_par 28 3067997Ssaidi@eecs.umich.edu#define bc_ctl_v_read_dirty_cln_shr 29 3077997Ssaidi@eecs.umich.edu#define bc_ctl_v_write_read_bubble 30 3087997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_wave_pipe_2 31 3097997Ssaidi@eecs.umich.edu#define bc_ctl_v_auto_dack 32 3107997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_byte_word 33 3117997Ssaidi@eecs.umich.edu#define bc_ctl_v_stclk_delay 34 3127997Ssaidi@eecs.umich.edu#define bc_ctl_v_write_under_miss 35 3137997Ssaidi@eecs.umich.edu#define bc_config_s_bc_size 3 3147997Ssaidi@eecs.umich.edu#define bc_config_v_bc_size 0 3157997Ssaidi@eecs.umich.edu#define bc_config_s_bc_rd_spd 4 3167997Ssaidi@eecs.umich.edu#define bc_config_v_bc_rd_spd 4 3177997Ssaidi@eecs.umich.edu#define bc_config_s_bc_wr_spd 4 3187997Ssaidi@eecs.umich.edu#define bc_config_v_bc_wr_spd 8 3197997Ssaidi@eecs.umich.edu#define bc_config_s_bc_rd_wr_spc 3 3207997Ssaidi@eecs.umich.edu#define bc_config_v_bc_rd_wr_spc 12 3217997Ssaidi@eecs.umich.edu#define bc_config_s_fill_we_offset 3 3227997Ssaidi@eecs.umich.edu#define bc_config_v_fill_we_offset 16 3237997Ssaidi@eecs.umich.edu#define bc_config_s_bc_we_ctl 9 3247997Ssaidi@eecs.umich.edu#define bc_config_v_bc_we_ctl 20 3257997Ssaidi@eecs.umich.edu// cbox registers, continued 3267997Ssaidi@eecs.umich.edu#define ei_stat_s_sys_id 4 3277997Ssaidi@eecs.umich.edu#define ei_stat_v_sys_id 24 3287997Ssaidi@eecs.umich.edu#define ei_stat_v_bc_tperr 28 3297997Ssaidi@eecs.umich.edu#define ei_stat_v_bc_tc_perr 29 3307997Ssaidi@eecs.umich.edu#define ei_stat_v_ei_es 30 3317997Ssaidi@eecs.umich.edu#define ei_stat_v_cor_ecc_err 31 3327997Ssaidi@eecs.umich.edu#define ei_stat_v_unc_ecc_err 32 3337997Ssaidi@eecs.umich.edu#define ei_stat_v_ei_par_err 33 3347997Ssaidi@eecs.umich.edu#define ei_stat_v_fil_ird 34 3357997Ssaidi@eecs.umich.edu#define ei_stat_v_seo_hrd_err 35 3367997Ssaidi@eecs.umich.edu// 3377997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_hit 12 3387997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_p 13 3397997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_d 14 3407997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_s 15 3417997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_v 16 3427997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tag_p 17 3437997Ssaidi@eecs.umich.edu#define bc_tag_addr_s_bc_tag 19 3447997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_bc_tag 20 3457997Ssaidi@eecs.umich.edu// ibox and icache registers. 3467997Ssaidi@eecs.umich.edu#define aster_v_kar 0 3477997Ssaidi@eecs.umich.edu#define aster_v_ear 1 3487997Ssaidi@eecs.umich.edu#define aster_v_sar 2 3497997Ssaidi@eecs.umich.edu#define aster_v_uar 3 3507997Ssaidi@eecs.umich.edu#define astrr_v_kar 0 3517997Ssaidi@eecs.umich.edu#define astrr_v_ear 1 3527997Ssaidi@eecs.umich.edu#define astrr_v_sar 2 3537997Ssaidi@eecs.umich.edu#define astrr_v_uar 3 3547997Ssaidi@eecs.umich.edu#define exc_addr_v_pal 0 3557997Ssaidi@eecs.umich.edu#define exc_sum_v_swc 10 3567997Ssaidi@eecs.umich.edu#define exc_sum_v_inv 11 3577997Ssaidi@eecs.umich.edu#define exc_sum_v_dze 12 3587997Ssaidi@eecs.umich.edu#define exc_sum_v_fov 13 3597997Ssaidi@eecs.umich.edu#define exc_sum_v_unf 14 3607997Ssaidi@eecs.umich.edu#define exc_sum_v_ine 15 3617997Ssaidi@eecs.umich.edu#define exc_sum_v_iov 16 3627997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc0c 27 3637997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc1c 28 3647997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc2c 29 3657997Ssaidi@eecs.umich.edu#define hwint_clr_v_crdc 32 3667997Ssaidi@eecs.umich.edu#define hwint_clr_v_slc 33 3677997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 3687997Ssaidi@eecs.umich.edu#define icperr_stat_v_dpe 11 3697997Ssaidi@eecs.umich.edu#define icperr_stat_v_tpe 12 3707997Ssaidi@eecs.umich.edu#define icperr_stat_v_tmr 13 3717997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_dpe 11 3727997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_tpe 12 3737997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_tmr 13 3747997Ssaidi@eecs.umich.edu#define icsr_v_pma 8 3757997Ssaidi@eecs.umich.edu#define icsr_v_pmp 9 3767997Ssaidi@eecs.umich.edu#define icsr_v_byt 17 3777997Ssaidi@eecs.umich.edu#define icsr_v_fmp 18 3787997Ssaidi@eecs.umich.edu#define icsr_v_im0 20 3797997Ssaidi@eecs.umich.edu#define icsr_v_im1 21 3807997Ssaidi@eecs.umich.edu#define icsr_v_im2 22 3817997Ssaidi@eecs.umich.edu#define icsr_v_im3 23 3827997Ssaidi@eecs.umich.edu#define icsr_v_tmm 24 3837997Ssaidi@eecs.umich.edu#define icsr_v_tmd 25 3847997Ssaidi@eecs.umich.edu#define icsr_v_fpe 26 3857997Ssaidi@eecs.umich.edu#define icsr_v_hwe 27 3867997Ssaidi@eecs.umich.edu#define icsr_s_spe 2 3877997Ssaidi@eecs.umich.edu#define icsr_v_spe 28 3887997Ssaidi@eecs.umich.edu#define icsr_v_sde 30 3897997Ssaidi@eecs.umich.edu#define icsr_v_crde 32 3907997Ssaidi@eecs.umich.edu#define icsr_v_sle 33 3917997Ssaidi@eecs.umich.edu#define icsr_v_fms 34 3927997Ssaidi@eecs.umich.edu#define icsr_v_fbt 35 3937997Ssaidi@eecs.umich.edu#define icsr_v_fbd 36 3947997Ssaidi@eecs.umich.edu#define icsr_v_dbs 37 3957997Ssaidi@eecs.umich.edu#define icsr_v_ista 38 3967997Ssaidi@eecs.umich.edu#define icsr_v_tst 39 3977997Ssaidi@eecs.umich.edu#define ifault_va_form_s_va 30 3987997Ssaidi@eecs.umich.edu#define ifault_va_form_v_va 3 3997997Ssaidi@eecs.umich.edu#define ifault_va_form_s_vptb 31 4007997Ssaidi@eecs.umich.edu#define ifault_va_form_v_vptb 33 4017997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_s_va 19 4027997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_v_va 3 4037997Ssaidi@eecs.umich.edu#define intid_s_intid 5 4047997Ssaidi@eecs.umich.edu#define intid_v_intid 0 4057997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 4067997Ssaidi@eecs.umich.edu#define ipl_s_ipl 5 4077997Ssaidi@eecs.umich.edu#define ipl_v_ipl 0 4087997Ssaidi@eecs.umich.edu#define itb_is_s_va 30 4097997Ssaidi@eecs.umich.edu#define itb_is_v_va 13 4107997Ssaidi@eecs.umich.edu#define itb_asn_s_asn 7 4117997Ssaidi@eecs.umich.edu#define itb_asn_v_asn 4 4127997Ssaidi@eecs.umich.edu#define itb_pte_v_asm 4 4137997Ssaidi@eecs.umich.edu#define itb_pte_s_gh 2 4147997Ssaidi@eecs.umich.edu#define itb_pte_v_gh 5 4157997Ssaidi@eecs.umich.edu#define itb_pte_v_kre 8 4167997Ssaidi@eecs.umich.edu#define itb_pte_v_ere 9 4177997Ssaidi@eecs.umich.edu#define itb_pte_v_sre 10 4187997Ssaidi@eecs.umich.edu#define itb_pte_v_ure 11 4197997Ssaidi@eecs.umich.edu#define itb_pte_s_pfn 27 4207997Ssaidi@eecs.umich.edu#define itb_pte_v_pfn 32 4217997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_asm 13 4227997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_kre 18 4237997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_ere 19 4247997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_sre 20 4257997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_ure 21 4267997Ssaidi@eecs.umich.edu#define itb_pte_temp_s_gh 3 4277997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_gh 29 4287997Ssaidi@eecs.umich.edu#define itb_pte_temp_s_pfn 27 4297997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_pfn 32 4307997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 4317997Ssaidi@eecs.umich.edu#define itb_tag_s_va 30 4327997Ssaidi@eecs.umich.edu#define itb_tag_v_va 13 4337997Ssaidi@eecs.umich.edu#define pal_base_s_pal_base 26 4347997Ssaidi@eecs.umich.edu#define pal_base_v_pal_base 14 4357997Ssaidi@eecs.umich.edu#define pmctr_s_sel2 4 4367997Ssaidi@eecs.umich.edu#define pmctr_v_sel2 0 4377997Ssaidi@eecs.umich.edu#define pmctr_s_sel1 4 4387997Ssaidi@eecs.umich.edu#define pmctr_v_sel1 4 4397997Ssaidi@eecs.umich.edu#define pmctr_v_killk 8 4407997Ssaidi@eecs.umich.edu#define pmctr_v_killp 9 4417997Ssaidi@eecs.umich.edu#define pmctr_s_ctl2 2 4427997Ssaidi@eecs.umich.edu#define pmctr_v_ctl2 10 4437997Ssaidi@eecs.umich.edu#define pmctr_s_ctl1 2 4447997Ssaidi@eecs.umich.edu#define pmctr_v_ctl1 12 4457997Ssaidi@eecs.umich.edu#define pmctr_s_ctl0 2 4467997Ssaidi@eecs.umich.edu#define pmctr_v_ctl0 14 4477997Ssaidi@eecs.umich.edu#define pmctr_s_ctr2 14 4487997Ssaidi@eecs.umich.edu#define pmctr_v_ctr2 16 4497997Ssaidi@eecs.umich.edu#define pmctr_v_killu 30 4507997Ssaidi@eecs.umich.edu#define pmctr_v_sel0 31 4517997Ssaidi@eecs.umich.edu#define pmctr_s_ctr1 16 4527997Ssaidi@eecs.umich.edu#define pmctr_v_ctr1 32 4537997Ssaidi@eecs.umich.edu#define pmctr_s_ctr0 16 4547997Ssaidi@eecs.umich.edu#define pmctr_v_ctr0 48 4557997Ssaidi@eecs.umich.edu#define ps_v_cm0 3 4567997Ssaidi@eecs.umich.edu#define ps_v_cm1 4 4577997Ssaidi@eecs.umich.edu#define isr_s_astrr 4 4587997Ssaidi@eecs.umich.edu#define isr_v_astrr 0 4597997Ssaidi@eecs.umich.edu#define isr_s_sisr 15 4607997Ssaidi@eecs.umich.edu#define isr_v_sisr 4 4617997Ssaidi@eecs.umich.edu#define isr_v_atr 19 4627997Ssaidi@eecs.umich.edu#define isr_v_i20 20 4637997Ssaidi@eecs.umich.edu#define isr_v_i21 21 4647997Ssaidi@eecs.umich.edu#define isr_v_i22 22 4657997Ssaidi@eecs.umich.edu#define isr_v_i23 23 4667997Ssaidi@eecs.umich.edu#define isr_v_pc0 27 4677997Ssaidi@eecs.umich.edu#define isr_v_pc1 28 4687997Ssaidi@eecs.umich.edu#define isr_v_pc2 29 4697997Ssaidi@eecs.umich.edu#define isr_v_pfl 30 4707997Ssaidi@eecs.umich.edu#define isr_v_mck 31 4717997Ssaidi@eecs.umich.edu#define isr_v_crd 32 4727997Ssaidi@eecs.umich.edu#define isr_v_sli 33 4737997Ssaidi@eecs.umich.edu#define isr_v_hlt 34 4747997Ssaidi@eecs.umich.edu#define sirr_s_sirr 15 4757997Ssaidi@eecs.umich.edu#define sirr_v_sirr 4 4767997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 4777997Ssaidi@eecs.umich.edu#define sl_txmit_v_tmt 7 4787997Ssaidi@eecs.umich.edu#define sl_rcv_v_rcv 6 4797997Ssaidi@eecs.umich.edu// mbox and dcache registers. 4807997Ssaidi@eecs.umich.edu#define alt_mode_v_am0 3 4817997Ssaidi@eecs.umich.edu#define alt_mode_v_am1 4 4827997Ssaidi@eecs.umich.edu#define cc_ctl_v_cc_ena 32 4837997Ssaidi@eecs.umich.edu#define dcperr_stat_v_seo 0 4847997Ssaidi@eecs.umich.edu#define dcperr_stat_v_lock 1 4857997Ssaidi@eecs.umich.edu#define dcperr_stat_v_dp0 2 4867997Ssaidi@eecs.umich.edu#define dcperr_stat_v_dp1 3 4877997Ssaidi@eecs.umich.edu#define dcperr_stat_v_tp0 4 4887997Ssaidi@eecs.umich.edu#define dcperr_stat_v_tp1 5 4897997Ssaidi@eecs.umich.edu// the following two registers are used exclusively for test and diagnostics. 4907997Ssaidi@eecs.umich.edu// they should not be referenced in normal operation. 4917997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_bank0 0 4927997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_bank1 1 4937997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_0 2 4947997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_index 10 4957997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_index 3 4967997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_fill_1 19 4977997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_1 13 4987997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_fill_2 32 4997997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_2 32 5007997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 5017997Ssaidi@eecs.umich.edu#define dc_test_tag_v_tag_par 2 5027997Ssaidi@eecs.umich.edu#define dc_test_tag_v_ow0 11 5037997Ssaidi@eecs.umich.edu#define dc_test_tag_v_ow1 12 5047997Ssaidi@eecs.umich.edu#define dc_test_tag_s_tag 26 5057997Ssaidi@eecs.umich.edu#define dc_test_tag_v_tag 13 5067997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_tag_par 2 5077997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d0p0 3 5087997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d0p1 4 5097997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d1p0 5 5107997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d1p1 6 5117997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_ow0 11 5127997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_ow1 12 5137997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_s_tag 26 5147997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_tag 13 5157997Ssaidi@eecs.umich.edu#define dtb_asn_s_asn 7 5167997Ssaidi@eecs.umich.edu#define dtb_asn_v_asn 57 5177997Ssaidi@eecs.umich.edu#define dtb_cm_v_cm0 3 5187997Ssaidi@eecs.umich.edu#define dtb_cm_v_cm1 4 5197997Ssaidi@eecs.umich.edu#define dtbis_s_va0 30 5207997Ssaidi@eecs.umich.edu#define dtbis_v_va0 13 5217997Ssaidi@eecs.umich.edu#define dtb_pte_v_for 1 5227997Ssaidi@eecs.umich.edu#define dtb_pte_v_fow 2 5237997Ssaidi@eecs.umich.edu#define dtb_pte_v_asm 4 5247997Ssaidi@eecs.umich.edu#define dtb_pte_s_gh 2 5257997Ssaidi@eecs.umich.edu#define dtb_pte_v_gh 5 5267997Ssaidi@eecs.umich.edu#define dtb_pte_v_kre 8 5277997Ssaidi@eecs.umich.edu#define dtb_pte_v_ere 9 5287997Ssaidi@eecs.umich.edu#define dtb_pte_v_sre 10 5297997Ssaidi@eecs.umich.edu#define dtb_pte_v_ure 11 5307997Ssaidi@eecs.umich.edu#define dtb_pte_v_kwe 12 5317997Ssaidi@eecs.umich.edu#define dtb_pte_v_ewe 13 5327997Ssaidi@eecs.umich.edu#define dtb_pte_v_swe 14 5337997Ssaidi@eecs.umich.edu#define dtb_pte_v_uwe 15 5347997Ssaidi@eecs.umich.edu#define dtb_pte_s_pfn 27 5357997Ssaidi@eecs.umich.edu#define dtb_pte_v_pfn 32 5367997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 5377997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_for 0 5387997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_fow 1 5397997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_kre 2 5407997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ere 3 5417997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_sre 4 5427997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ure 5 5437997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_kwe 6 5447997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ewe 7 5457997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_swe 8 5467997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_uwe 9 5477997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_asm 10 5487997Ssaidi@eecs.umich.edu#define dtb_pte_temp_s_fill_0 2 5497997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_fill_0 11 5507997Ssaidi@eecs.umich.edu#define dtb_pte_temp_s_pfn 27 5517997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_pfn 13 5527997Ssaidi@eecs.umich.edu#define dtb_tag_s_va 30 5537997Ssaidi@eecs.umich.edu#define dtb_tag_v_va 13 5547997Ssaidi@eecs.umich.edu// most mcsr bits are used for testability and diagnostics only. 5557997Ssaidi@eecs.umich.edu// for normal operation, they will be supported in the following configuration: 5567997Ssaidi@eecs.umich.edu// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, 5577997Ssaidi@eecs.umich.edu// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 5587997Ssaidi@eecs.umich.edu#define mcsr_v_big_endian 0 5597997Ssaidi@eecs.umich.edu#define mcsr_v_sp0 1 5607997Ssaidi@eecs.umich.edu#define mcsr_v_sp1 2 5617997Ssaidi@eecs.umich.edu#define mcsr_v_mbox_sel 3 5627997Ssaidi@eecs.umich.edu#define mcsr_v_e_big_endian 4 5637997Ssaidi@eecs.umich.edu#define mcsr_v_dbg_packet_sel 5 5647997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_ena 0 5657997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_fhit 1 5667997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_bad_parity 2 5677997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_perr_dis 3 5687997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_doa 4 5697997Ssaidi@eecs.umich.edu#define maf_mode_v_maf_nomerge 0 5707997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_flush_always 1 5717997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_nomerge 2 5727997Ssaidi@eecs.umich.edu#define maf_mode_v_io_nomerge 3 5737997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_cnt_disable 4 5747997Ssaidi@eecs.umich.edu#define maf_mode_v_maf_arb_disable 5 5757997Ssaidi@eecs.umich.edu#define maf_mode_v_dread_pending 6 5767997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_pending 7 5777997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 5787997Ssaidi@eecs.umich.edu#define mm_stat_v_wr 0 5797997Ssaidi@eecs.umich.edu#define mm_stat_v_acv 1 5807997Ssaidi@eecs.umich.edu#define mm_stat_v_for 2 5817997Ssaidi@eecs.umich.edu#define mm_stat_v_fow 3 5827997Ssaidi@eecs.umich.edu#define mm_stat_v_dtb_miss 4 5837997Ssaidi@eecs.umich.edu#define mm_stat_v_bad_va 5 5847997Ssaidi@eecs.umich.edu#define mm_stat_s_ra 5 5857997Ssaidi@eecs.umich.edu#define mm_stat_v_ra 6 5867997Ssaidi@eecs.umich.edu#define mm_stat_s_opcode 6 5877997Ssaidi@eecs.umich.edu#define mm_stat_v_opcode 11 5887997Ssaidi@eecs.umich.edu#define mvptbr_s_vptb 31 5897997Ssaidi@eecs.umich.edu#define mvptbr_v_vptb 33 5907997Ssaidi@eecs.umich.edu#define va_form_s_va 30 5917997Ssaidi@eecs.umich.edu#define va_form_v_va 3 5927997Ssaidi@eecs.umich.edu#define va_form_s_vptb 31 5937997Ssaidi@eecs.umich.edu#define va_form_v_vptb 33 5947997Ssaidi@eecs.umich.edu#define va_form_nt_s_va 19 5957997Ssaidi@eecs.umich.edu#define va_form_nt_v_va 3 5967997Ssaidi@eecs.umich.edu//.endm 5977997Ssaidi@eecs.umich.edu 5987997Ssaidi@eecs.umich.edu#endif 599