paljtoslave.S revision 8013
18012Ssaidi@eecs.umich.edu/* 28013Sbinkertn@umich.edu * Copyright (c) 2003, 2004 38013Sbinkertn@umich.edu * The Regents of The University of Michigan 48013Sbinkertn@umich.edu * All Rights Reserved 58013Sbinkertn@umich.edu * 68013Sbinkertn@umich.edu * This code is part of the M5 simulator, developed by Nathan Binkert, 78013Sbinkertn@umich.edu * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 88013Sbinkertn@umich.edu * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew 98013Sbinkertn@umich.edu * Schultz. 108013Sbinkertn@umich.edu * 118013Sbinkertn@umich.edu * Permission is granted to use, copy, create derivative works and 128013Sbinkertn@umich.edu * redistribute this software and such derivative works for any purpose, 138013Sbinkertn@umich.edu * so long as the copyright notice above, this grant of permission, and 148013Sbinkertn@umich.edu * the disclaimer below appear in all copies made; and so long as the 158013Sbinkertn@umich.edu * name of The University of Michigan is not used in any advertising or 168013Sbinkertn@umich.edu * publicity pertaining to the use or distribution of this software 178013Sbinkertn@umich.edu * without specific, written prior authorization. 188013Sbinkertn@umich.edu * 198013Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 208013Sbinkertn@umich.edu * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT 218013Sbinkertn@umich.edu * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR 228013Sbinkertn@umich.edu * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF 238013Sbinkertn@umich.edu * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF 248013Sbinkertn@umich.edu * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, 258013Sbinkertn@umich.edu * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL 268013Sbinkertn@umich.edu * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION 278013Sbinkertn@umich.edu * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER 288013Sbinkertn@umich.edu * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 298013Sbinkertn@umich.edu */ 308012Ssaidi@eecs.umich.edu 318013Sbinkertn@umich.edu/* 328013Sbinkertn@umich.edu * Copyright 1993 Hewlett-Packard Development Company, L.P. 338013Sbinkertn@umich.edu * 348013Sbinkertn@umich.edu * Permission is hereby granted, free of charge, to any person 358013Sbinkertn@umich.edu * obtaining a copy of this software and associated documentation 368013Sbinkertn@umich.edu * files (the "Software"), to deal in the Software without 378013Sbinkertn@umich.edu * restriction, including without limitation the rights to use, copy, 388013Sbinkertn@umich.edu * modify, merge, publish, distribute, sublicense, and/or sell copies 398013Sbinkertn@umich.edu * of the Software, and to permit persons to whom the Software is 408013Sbinkertn@umich.edu * furnished to do so, subject to the following conditions: 418013Sbinkertn@umich.edu * 428013Sbinkertn@umich.edu * The above copyright notice and this permission notice shall be 438013Sbinkertn@umich.edu * included in all copies or substantial portions of the Software. 448013Sbinkertn@umich.edu * 458013Sbinkertn@umich.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 468013Sbinkertn@umich.edu * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 478013Sbinkertn@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 488013Sbinkertn@umich.edu * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 498013Sbinkertn@umich.edu * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 508013Sbinkertn@umich.edu * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 518013Sbinkertn@umich.edu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 528013Sbinkertn@umich.edu * SOFTWARE. 538013Sbinkertn@umich.edu */ 548012Ssaidi@eecs.umich.edu 558013Sbinkertn@umich.edu#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 568013Sbinkertn@umich.edu#include "ev5_defs.h" 578013Sbinkertn@umich.edu#include "fromHudsonOsf.h" // OSF/1 specific definitions 588013Sbinkertn@umich.edu#include "fromHudsonMacros.h" // Global macro definitions 598012Ssaidi@eecs.umich.edu 608012Ssaidi@eecs.umich.edu/* 618013Sbinkertn@umich.edu * args: 628013Sbinkertn@umich.edu * a0: here 638013Sbinkertn@umich.edu * a1: boot location 648013Sbinkertn@umich.edu * a2: CSERVE_J_KTOPAL 658013Sbinkertn@umich.edu * a3: restrart_pv 668013Sbinkertn@umich.edu * a4: vptb 678013Sbinkertn@umich.edu * a5: my_rpb 688013Sbinkertn@umich.edu * 698013Sbinkertn@umich.edu * SRM Console Architecture III 3-26 708013Sbinkertn@umich.edu */ 718008Ssaidi@eecs.umich.edu 728008Ssaidi@eecs.umich.edu .global palJToSlave 738008Ssaidi@eecs.umich.edu .text 3 748008Ssaidi@eecs.umich.edupalJToSlave: 758008Ssaidi@eecs.umich.edu 768008Ssaidi@eecs.umich.edu ALIGN_BRANCH 778008Ssaidi@eecs.umich.edu 788008Ssaidi@eecs.umich.edu bis a3, zero, pv 798008Ssaidi@eecs.umich.edu bis zero, zero, t11 808008Ssaidi@eecs.umich.edu bis zero, zero, ra 818008Ssaidi@eecs.umich.edu 828008Ssaidi@eecs.umich.edu /* Point the Vptbr to a2 */ 838008Ssaidi@eecs.umich.edu 848008Ssaidi@eecs.umich.edu mtpr a4, mVptBr // Load Mbox copy 858008Ssaidi@eecs.umich.edu mtpr a4, iVptBr // Load Ibox copy 868008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 878008Ssaidi@eecs.umich.edu 888008Ssaidi@eecs.umich.edu /* Turn on superpage mapping in the mbox and icsr */ 898008Ssaidi@eecs.umich.edu lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 908008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 918013Sbinkertn@umich.edu mtpr t0, mcsr // Set the super page mode enable bit 928008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 938008Ssaidi@eecs.umich.edu 948008Ssaidi@eecs.umich.edu lda t0, 0(zero) 958008Ssaidi@eecs.umich.edu mtpr t0, dtbAsn 968008Ssaidi@eecs.umich.edu mtpr t0, itbAsn 978008Ssaidi@eecs.umich.edu 988008Ssaidi@eecs.umich.edu LDLI (t1,0x20000000) 998008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1008013Sbinkertn@umich.edu mfpr t0, icsr // Enable superpage mapping 1018008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1028008Ssaidi@eecs.umich.edu bis t0, t1, t0 1038008Ssaidi@eecs.umich.edu mtpr t0, icsr 1048008Ssaidi@eecs.umich.edu 1058013Sbinkertn@umich.edu STALL // Required stall to update chip ... 1068008Ssaidi@eecs.umich.edu STALL 1078008Ssaidi@eecs.umich.edu STALL 1088008Ssaidi@eecs.umich.edu STALL 1098008Ssaidi@eecs.umich.edu STALL 1108008Ssaidi@eecs.umich.edu 1118008Ssaidi@eecs.umich.edu ldq_p s0, PCB_Q_PTBR(a5) 1128013Sbinkertn@umich.edu sll s0, VA_S_OFF, s0 // Shift PTBR into position 1138008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1148013Sbinkertn@umich.edu mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 1158008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1168008Ssaidi@eecs.umich.edu ldq_p sp, PCB_Q_KSP(a5) 1178008Ssaidi@eecs.umich.edu 1188013Sbinkertn@umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1198013Sbinkertn@umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1208008Ssaidi@eecs.umich.edu 1218013Sbinkertn@umich.edu mtpr a1, excAddr // Load the dispatch address. 1228008Ssaidi@eecs.umich.edu 1238008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1248008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1258013Sbinkertn@umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1268013Sbinkertn@umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1278008Ssaidi@eecs.umich.edu br zero, 2f 1288008Ssaidi@eecs.umich.edu 1298008Ssaidi@eecs.umich.edu ALIGN_BLOCK 1308008Ssaidi@eecs.umich.edu 1318008Ssaidi@eecs.umich.edu2: NOP 1328013Sbinkertn@umich.edu mtpr zero, icFlush // Flush the icache. 1338008Ssaidi@eecs.umich.edu NOP 1348008Ssaidi@eecs.umich.edu NOP 1358008Ssaidi@eecs.umich.edu 1368013Sbinkertn@umich.edu NOP // Required NOPs ... 1-10 1378008Ssaidi@eecs.umich.edu NOP 1388008Ssaidi@eecs.umich.edu NOP 1398008Ssaidi@eecs.umich.edu NOP 1408008Ssaidi@eecs.umich.edu NOP 1418008Ssaidi@eecs.umich.edu NOP 1428008Ssaidi@eecs.umich.edu NOP 1438008Ssaidi@eecs.umich.edu NOP 1448008Ssaidi@eecs.umich.edu NOP 1458008Ssaidi@eecs.umich.edu NOP 1468008Ssaidi@eecs.umich.edu 1478013Sbinkertn@umich.edu NOP // Required NOPs ... 11-20 1488008Ssaidi@eecs.umich.edu NOP 1498008Ssaidi@eecs.umich.edu NOP 1508008Ssaidi@eecs.umich.edu NOP 1518008Ssaidi@eecs.umich.edu NOP 1528008Ssaidi@eecs.umich.edu NOP 1538008Ssaidi@eecs.umich.edu NOP 1548008Ssaidi@eecs.umich.edu NOP 1558008Ssaidi@eecs.umich.edu NOP 1568008Ssaidi@eecs.umich.edu NOP 1578008Ssaidi@eecs.umich.edu 1588013Sbinkertn@umich.edu NOP // Required NOPs ... 21-30 1598008Ssaidi@eecs.umich.edu NOP 1608008Ssaidi@eecs.umich.edu NOP 1618008Ssaidi@eecs.umich.edu NOP 1628008Ssaidi@eecs.umich.edu NOP 1638008Ssaidi@eecs.umich.edu NOP 1648008Ssaidi@eecs.umich.edu NOP 1658008Ssaidi@eecs.umich.edu NOP 1668008Ssaidi@eecs.umich.edu NOP 1678008Ssaidi@eecs.umich.edu NOP 1688008Ssaidi@eecs.umich.edu 1698013Sbinkertn@umich.edu NOP // Required NOPs ... 31-40 1708008Ssaidi@eecs.umich.edu NOP 1718008Ssaidi@eecs.umich.edu NOP 1728008Ssaidi@eecs.umich.edu NOP 1738008Ssaidi@eecs.umich.edu NOP 1748008Ssaidi@eecs.umich.edu NOP 1758008Ssaidi@eecs.umich.edu NOP 1768008Ssaidi@eecs.umich.edu NOP 1778008Ssaidi@eecs.umich.edu NOP 1788008Ssaidi@eecs.umich.edu NOP 1798008Ssaidi@eecs.umich.edu 1808013Sbinkertn@umich.edu NOP // Required NOPs ... 41-44 1818008Ssaidi@eecs.umich.edu NOP 1828008Ssaidi@eecs.umich.edu NOP 1838008Ssaidi@eecs.umich.edu NOP 1848008Ssaidi@eecs.umich.edu 1858013Sbinkertn@umich.edu hw_rei_stall // Dispatch to kernel 1868008Ssaidi@eecs.umich.edu 187