paljtoslave.S revision 8008
18008Ssaidi@eecs.umich.edu#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 28008Ssaidi@eecs.umich.edu#include "ev5_defs.h" 38008Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" // OSF/1 specific definitions 48008Ssaidi@eecs.umich.edu#include "fromHudsonMacros.h" // Global macro definitions 58008Ssaidi@eecs.umich.edu#include "ev5_impure.h" // Scratch & logout area data structures 68008Ssaidi@eecs.umich.edu#include "platform.h" // Platform specific definitions 78008Ssaidi@eecs.umich.edu 88008Ssaidi@eecs.umich.edu 98008Ssaidi@eecs.umich.edu .global palJToSlave 108008Ssaidi@eecs.umich.edu .text 3 118008Ssaidi@eecs.umich.edu 128008Ssaidi@eecs.umich.edu /* 138008Ssaidi@eecs.umich.edu * args: 148008Ssaidi@eecs.umich.edu a0: here 158008Ssaidi@eecs.umich.edu a1: boot location 168008Ssaidi@eecs.umich.edu a2: CSERVE_J_KTOPAL 178008Ssaidi@eecs.umich.edu a3: restrart_pv 188008Ssaidi@eecs.umich.edu a4: vptb 198008Ssaidi@eecs.umich.edu a5: my_rpb 208008Ssaidi@eecs.umich.edu 218008Ssaidi@eecs.umich.edu */ 228008Ssaidi@eecs.umich.edupalJToSlave: 238008Ssaidi@eecs.umich.edu 248008Ssaidi@eecs.umich.edu /* 258008Ssaidi@eecs.umich.edu * SRM Console Architecture III 3-26 268008Ssaidi@eecs.umich.edu */ 278008Ssaidi@eecs.umich.edu 288008Ssaidi@eecs.umich.edu ALIGN_BRANCH 298008Ssaidi@eecs.umich.edu 308008Ssaidi@eecs.umich.edu bis a3, zero, pv 318008Ssaidi@eecs.umich.edu bis zero, zero, t11 328008Ssaidi@eecs.umich.edu bis zero, zero, ra 338008Ssaidi@eecs.umich.edu 348008Ssaidi@eecs.umich.edu /* Point the Vptbr to a2 */ 358008Ssaidi@eecs.umich.edu 368008Ssaidi@eecs.umich.edu mtpr a4, mVptBr // Load Mbox copy 378008Ssaidi@eecs.umich.edu mtpr a4, iVptBr // Load Ibox copy 388008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 398008Ssaidi@eecs.umich.edu 408008Ssaidi@eecs.umich.edu /* Turn on superpage mapping in the mbox and icsr */ 418008Ssaidi@eecs.umich.edu lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 428008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 438008Ssaidi@eecs.umich.edu mtpr t0, mcsr // Set the super page mode enable bit 448008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 458008Ssaidi@eecs.umich.edu 468008Ssaidi@eecs.umich.edu lda t0, 0(zero) 478008Ssaidi@eecs.umich.edu mtpr t0, dtbAsn 488008Ssaidi@eecs.umich.edu mtpr t0, itbAsn 498008Ssaidi@eecs.umich.edu 508008Ssaidi@eecs.umich.edu LDLI (t1,0x20000000) 518008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 528008Ssaidi@eecs.umich.edu mfpr t0, icsr // Enable superpage mapping 538008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 548008Ssaidi@eecs.umich.edu bis t0, t1, t0 558008Ssaidi@eecs.umich.edu mtpr t0, icsr 568008Ssaidi@eecs.umich.edu 578008Ssaidi@eecs.umich.edu STALL // Required stall to update chip ... 588008Ssaidi@eecs.umich.edu STALL 598008Ssaidi@eecs.umich.edu STALL 608008Ssaidi@eecs.umich.edu STALL 618008Ssaidi@eecs.umich.edu STALL 628008Ssaidi@eecs.umich.edu 638008Ssaidi@eecs.umich.edu ldq_p s0, PCB_Q_PTBR(a5) 648008Ssaidi@eecs.umich.edu sll s0, VA_S_OFF, s0 // Shift PTBR into position 658008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 668008Ssaidi@eecs.umich.edu mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 678008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 688008Ssaidi@eecs.umich.edu ldq_p sp, PCB_Q_KSP(a5) 698008Ssaidi@eecs.umich.edu 708008Ssaidi@eecs.umich.edu //mtpr a0, excAddr // Load the dispatch address. 718008Ssaidi@eecs.umich.edu //STALL // don't dual issue the load with mtpr -pb 728008Ssaidi@eecs.umich.edu //bis a3, zero, a0 // first free PFN 738008Ssaidi@eecs.umich.edu // ldq_p a1, PCB_Q_PTBR(a5) // ptbr 748008Ssaidi@eecs.umich.edu 758008Ssaidi@eecs.umich.edu //ldq_p a2, 24(zero) // argc 768008Ssaidi@eecs.umich.edu //ldq_p a3, 32(zero) // argv 778008Ssaidi@eecs.umich.edu //ldq_p a4, 40(zero) // environ 788008Ssaidi@eecs.umich.edu //lda a5, 0(zero) // osf_param 798008Ssaidi@eecs.umich.edu //STALL // don't dual issue the load with mtpr -pb 808008Ssaidi@eecs.umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 818008Ssaidi@eecs.umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 828008Ssaidi@eecs.umich.edu 838008Ssaidi@eecs.umich.edu 848008Ssaidi@eecs.umich.edu mtpr a1, excAddr // Load the dispatch address. 858008Ssaidi@eecs.umich.edu 868008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 878008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 888008Ssaidi@eecs.umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 898008Ssaidi@eecs.umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 908008Ssaidi@eecs.umich.edu br zero, 2f 918008Ssaidi@eecs.umich.edu 928008Ssaidi@eecs.umich.edu ALIGN_BLOCK 938008Ssaidi@eecs.umich.edu 948008Ssaidi@eecs.umich.edu2: NOP 958008Ssaidi@eecs.umich.edu mtpr zero, icFlush // Flush the icache. 968008Ssaidi@eecs.umich.edu NOP 978008Ssaidi@eecs.umich.edu NOP 988008Ssaidi@eecs.umich.edu 998008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 1-10 1008008Ssaidi@eecs.umich.edu NOP 1018008Ssaidi@eecs.umich.edu NOP 1028008Ssaidi@eecs.umich.edu NOP 1038008Ssaidi@eecs.umich.edu NOP 1048008Ssaidi@eecs.umich.edu NOP 1058008Ssaidi@eecs.umich.edu NOP 1068008Ssaidi@eecs.umich.edu NOP 1078008Ssaidi@eecs.umich.edu NOP 1088008Ssaidi@eecs.umich.edu NOP 1098008Ssaidi@eecs.umich.edu 1108008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 11-20 1118008Ssaidi@eecs.umich.edu NOP 1128008Ssaidi@eecs.umich.edu NOP 1138008Ssaidi@eecs.umich.edu NOP 1148008Ssaidi@eecs.umich.edu NOP 1158008Ssaidi@eecs.umich.edu NOP 1168008Ssaidi@eecs.umich.edu NOP 1178008Ssaidi@eecs.umich.edu NOP 1188008Ssaidi@eecs.umich.edu NOP 1198008Ssaidi@eecs.umich.edu NOP 1208008Ssaidi@eecs.umich.edu 1218008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 21-30 1228008Ssaidi@eecs.umich.edu NOP 1238008Ssaidi@eecs.umich.edu NOP 1248008Ssaidi@eecs.umich.edu NOP 1258008Ssaidi@eecs.umich.edu NOP 1268008Ssaidi@eecs.umich.edu NOP 1278008Ssaidi@eecs.umich.edu NOP 1288008Ssaidi@eecs.umich.edu NOP 1298008Ssaidi@eecs.umich.edu NOP 1308008Ssaidi@eecs.umich.edu NOP 1318008Ssaidi@eecs.umich.edu 1328008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 31-40 1338008Ssaidi@eecs.umich.edu NOP 1348008Ssaidi@eecs.umich.edu NOP 1358008Ssaidi@eecs.umich.edu NOP 1368008Ssaidi@eecs.umich.edu NOP 1378008Ssaidi@eecs.umich.edu NOP 1388008Ssaidi@eecs.umich.edu NOP 1398008Ssaidi@eecs.umich.edu NOP 1408008Ssaidi@eecs.umich.edu NOP 1418008Ssaidi@eecs.umich.edu NOP 1428008Ssaidi@eecs.umich.edu 1438008Ssaidi@eecs.umich.edu 1448008Ssaidi@eecs.umich.edu 1458008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 41-44 1468008Ssaidi@eecs.umich.edu NOP 1478008Ssaidi@eecs.umich.edu NOP 1488008Ssaidi@eecs.umich.edu NOP 1498008Ssaidi@eecs.umich.edu 1508008Ssaidi@eecs.umich.edu hw_rei_stall // Dispatch to kernel 1518008Ssaidi@eecs.umich.edu 152