18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 2003-2004 The Regents of The University of Michigan 38029Snate@binkert.org * Copyright (c) 1993 The Hewlett-Packard Development Company 48029Snate@binkert.org * All rights reserved. 58013Sbinkertn@umich.edu * 68029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 78029Snate@binkert.org * modification, are permitted provided that the following conditions are 88029Snate@binkert.org * met: redistributions of source code must retain the above copyright 98029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 108029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 118029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 128029Snate@binkert.org * documentation and/or other materials provided with the distribution; 138029Snate@binkert.org * neither the name of the copyright holders nor the names of its 148029Snate@binkert.org * contributors may be used to endorse or promote products derived from 158029Snate@binkert.org * this software without specific prior written permission. 168013Sbinkertn@umich.edu * 178029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288013Sbinkertn@umich.edu */ 298012Ssaidi@eecs.umich.edu 308008Ssaidi@eecs.umich.edu#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 318008Ssaidi@eecs.umich.edu#include "ev5_defs.h" 328013Sbinkertn@umich.edu#include "fromHudsonOsf.h" // OSF/1 specific definitions 338013Sbinkertn@umich.edu#include "fromHudsonMacros.h" // Global macro definitions 348008Ssaidi@eecs.umich.edu 358008Ssaidi@eecs.umich.edu/* Jump to kernel 368013Sbinkertn@umich.edu * args: 378013Sbinkertn@umich.edu * Kernel address - a0 388013Sbinkertn@umich.edu * PCBB - a1 398013Sbinkertn@umich.edu * First free PFN - a3? 408013Sbinkertn@umich.edu * 418013Sbinkertn@umich.edu * Enable kseg addressing in ICSR 428013Sbinkertn@umich.edu * Enable kseg addressing in MCSR 438013Sbinkertn@umich.edu * Set VTBR -- Set to 1GB as per SRM, or maybe 8GB?? 448013Sbinkertn@umich.edu * Set PCBB -- pass pointer in arg 458013Sbinkertn@umich.edu * Set PTBR -- get it out of PCB 468013Sbinkertn@umich.edu * Set KSP -- get it out of PCB 478013Sbinkertn@umich.edu * 488013Sbinkertn@umich.edu * Jump to kernel address 498013Sbinkertn@umich.edu * 508013Sbinkertn@umich.edu * Kernel args- 518013Sbinkertn@umich.edu * s0 first free PFN 528013Sbinkertn@umich.edu * s1 ptbr 538013Sbinkertn@umich.edu * s2 argc 0 548013Sbinkertn@umich.edu * s3 argv NULL 558013Sbinkertn@umich.edu * s5 osf_param (sysconfigtab) NULL 568008Ssaidi@eecs.umich.edu */ 578008Ssaidi@eecs.umich.edu 588013Sbinkertn@umich.edu .global palJToKern 598013Sbinkertn@umich.edu .text 3 608013Sbinkertn@umich.edupalJToKern: 618008Ssaidi@eecs.umich.edu ALIGN_BRANCH 628008Ssaidi@eecs.umich.edu 638008Ssaidi@eecs.umich.edu ldq_p a0, 0(zero) 648008Ssaidi@eecs.umich.edu ldq_p a1, 8(zero) 658008Ssaidi@eecs.umich.edu ldq_p a3, 16(zero) 668008Ssaidi@eecs.umich.edu 678008Ssaidi@eecs.umich.edu /* Point the Vptbr at 8GB */ 688008Ssaidi@eecs.umich.edu lda t0, 0x1(zero) 698008Ssaidi@eecs.umich.edu sll t0, 33, t0 708008Ssaidi@eecs.umich.edu 718008Ssaidi@eecs.umich.edu mtpr t0, mVptBr // Load Mbox copy 728008Ssaidi@eecs.umich.edu mtpr t0, iVptBr // Load Ibox copy 738008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 748008Ssaidi@eecs.umich.edu 758008Ssaidi@eecs.umich.edu /* Turn on superpage mapping in the mbox and icsr */ 768008Ssaidi@eecs.umich.edu lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 778008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 788013Sbinkertn@umich.edu mtpr t0, mcsr // Set the super page mode enable bit 798008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 808008Ssaidi@eecs.umich.edu 818008Ssaidi@eecs.umich.edu lda t0, 0(zero) 828008Ssaidi@eecs.umich.edu mtpr t0, dtbAsn 838008Ssaidi@eecs.umich.edu mtpr t0, itbAsn 848008Ssaidi@eecs.umich.edu 858008Ssaidi@eecs.umich.edu LDLI (t1,0x20000000) 868008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 878013Sbinkertn@umich.edu mfpr t0, icsr // Enable superpage mapping 888008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 898008Ssaidi@eecs.umich.edu bis t0, t1, t0 908008Ssaidi@eecs.umich.edu mtpr t0, icsr 918008Ssaidi@eecs.umich.edu 928013Sbinkertn@umich.edu STALL // Required stall to update chip ... 938008Ssaidi@eecs.umich.edu STALL 948008Ssaidi@eecs.umich.edu STALL 958008Ssaidi@eecs.umich.edu STALL 968008Ssaidi@eecs.umich.edu STALL 978008Ssaidi@eecs.umich.edu 988008Ssaidi@eecs.umich.edu ldq_p s0, PCB_Q_PTBR(a1) 998013Sbinkertn@umich.edu sll s0, VA_S_OFF, s0 // Shift PTBR into position 1008008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1018013Sbinkertn@umich.edu mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 1028008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1038008Ssaidi@eecs.umich.edu ldq_p sp, PCB_Q_KSP(a1) 1048008Ssaidi@eecs.umich.edu 1058013Sbinkertn@umich.edu mtpr a0, excAddr // Load the dispatch address. 1068008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1078013Sbinkertn@umich.edu bis a3, zero, a0 // first free PFN 1088013Sbinkertn@umich.edu ldq_p a1, PCB_Q_PTBR(a1) // ptbr 1098013Sbinkertn@umich.edu ldq_p a2, 24(zero) // argc 1108013Sbinkertn@umich.edu ldq_p a3, 32(zero) // argv 1118013Sbinkertn@umich.edu ldq_p a4, 40(zero) // environ 1128013Sbinkertn@umich.edu lda a5, 0(zero) // osf_param 1138008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1148013Sbinkertn@umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1158013Sbinkertn@umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1168008Ssaidi@eecs.umich.edu br zero, 2f 1178008Ssaidi@eecs.umich.edu 1188008Ssaidi@eecs.umich.edu ALIGN_BLOCK 1198008Ssaidi@eecs.umich.edu 1208013Sbinkertn@umich.edu2: NOP 1218013Sbinkertn@umich.edu mtpr zero, icFlush // Flush the icache. 1228008Ssaidi@eecs.umich.edu NOP 1238008Ssaidi@eecs.umich.edu NOP 1248008Ssaidi@eecs.umich.edu 1258013Sbinkertn@umich.edu NOP // Required NOPs ... 1-10 1268008Ssaidi@eecs.umich.edu NOP 1278008Ssaidi@eecs.umich.edu NOP 1288008Ssaidi@eecs.umich.edu NOP 1298008Ssaidi@eecs.umich.edu NOP 1308008Ssaidi@eecs.umich.edu NOP 1318008Ssaidi@eecs.umich.edu NOP 1328008Ssaidi@eecs.umich.edu NOP 1338008Ssaidi@eecs.umich.edu NOP 1348008Ssaidi@eecs.umich.edu NOP 1358008Ssaidi@eecs.umich.edu 1368013Sbinkertn@umich.edu NOP // Required NOPs ... 11-20 1378008Ssaidi@eecs.umich.edu NOP 1388008Ssaidi@eecs.umich.edu NOP 1398008Ssaidi@eecs.umich.edu NOP 1408008Ssaidi@eecs.umich.edu NOP 1418008Ssaidi@eecs.umich.edu NOP 1428008Ssaidi@eecs.umich.edu NOP 1438008Ssaidi@eecs.umich.edu NOP 1448008Ssaidi@eecs.umich.edu NOP 1458008Ssaidi@eecs.umich.edu NOP 1468008Ssaidi@eecs.umich.edu 1478013Sbinkertn@umich.edu NOP // Required NOPs ... 21-30 1488008Ssaidi@eecs.umich.edu NOP 1498008Ssaidi@eecs.umich.edu NOP 1508008Ssaidi@eecs.umich.edu NOP 1518008Ssaidi@eecs.umich.edu NOP 1528008Ssaidi@eecs.umich.edu NOP 1538008Ssaidi@eecs.umich.edu NOP 1548008Ssaidi@eecs.umich.edu NOP 1558008Ssaidi@eecs.umich.edu NOP 1568008Ssaidi@eecs.umich.edu NOP 1578008Ssaidi@eecs.umich.edu 1588013Sbinkertn@umich.edu NOP // Required NOPs ... 31-40 1598008Ssaidi@eecs.umich.edu NOP 1608008Ssaidi@eecs.umich.edu NOP 1618008Ssaidi@eecs.umich.edu NOP 1628008Ssaidi@eecs.umich.edu NOP 1638008Ssaidi@eecs.umich.edu NOP 1648008Ssaidi@eecs.umich.edu NOP 1658008Ssaidi@eecs.umich.edu NOP 1668008Ssaidi@eecs.umich.edu NOP 1678008Ssaidi@eecs.umich.edu NOP 1688008Ssaidi@eecs.umich.edu 1698013Sbinkertn@umich.edu NOP // Required NOPs ... 41-44 1708008Ssaidi@eecs.umich.edu NOP 1718008Ssaidi@eecs.umich.edu NOP 1728008Ssaidi@eecs.umich.edu NOP 1738008Ssaidi@eecs.umich.edu 1748013Sbinkertn@umich.edu hw_rei_stall // Dispatch to kernel 175