dbmentry.S revision 8024:27ce7490bd3b 
1/*
2 * Copyright (c) 2003, 2004
3 * The Regents of The University of Michigan
4 * All Rights Reserved
5 *
6 * This code is part of the M5 simulator, developed by Nathan Binkert,
7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
9 * Schultz.
10 *
11 * Permission is granted to use, copy, create derivative works and
12 * redistribute this software and such derivative works for any purpose,
13 * so long as the copyright notice above, this grant of permission, and
14 * the disclaimer below appear in all copies made; and so long as the
15 * name of The University of Michigan is not used in any advertising or
16 * publicity pertaining to the use or distribution of this software
17 * without specific, written prior authorization.
18 *
19 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
20 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
21 * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
22 * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
24 * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
25 * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
26 * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
27 * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
28 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
29 */
30/*
31 * Copyright 1993 Hewlett-Packard Development Company, L.P.
32 *
33 * Permission is hereby granted, free of charge, to any person
34 * obtaining a copy of this software and associated documentation
35 * files (the "Software"), to deal in the Software without
36 * restriction, including without limitation the rights to use, copy,
37 * modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is
39 * furnished to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be
42 * included in all copies or substantial portions of the Software.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
45 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
46 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
48 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
49 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
50 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
51 * SOFTWARE.
52 */
53
54/*
55 * Debug Monitor Entry code
56 */
57#include "fromHudsonOsf.h"
58
59        .extern myAlphaAccess
60        .text
61
62/* return address and padding to octaword align */
63#define STARTFRM 16
64
65        .globl  _start
66        .ent    _start, 0
67_start:
68_entry:
69        br      t0, 2f			# get the current PC
702:	ldgp    gp, 0(t0)               # init gp
71
72/* Processor 0 start stack frame is begining of physical memory (0)
73   Other processors spin here waiting to get their stacks from
74   Processor 0, then they can progress as normal.
75*/
76        call_pal PAL_WHAMI_ENTRY
77        beq v0, cpuz
78        ldq  t3, m5AlphaAccess
79        addq t3,0x70,t3 # *** If offset in console alpha access struct changes
80                        # This must be changed as well!
81        bis  zero,8,t4
82        mulq t4,v0,t4
83        addq t3,t4,t3
84        ldah a0, 3(zero)  # load arg0 with 65536*3
85cpuwait: .long 0x6000002  # jsr quiesceNs
86        ldq  t4, 0(t3)
87        beq  t4, cpuwait
88        bis  t4,t4,sp
89
90
91cpuz:	bis	sp,sp,s0 /* save sp */
92
93slave:	lda	v0,(8*1024)(sp) /* end of page  */
94
95        subq	zero, 1, t0
96        sll	t0, 42, t0
97        bis	t0, v0, sp
98
99        lda     sp, -STARTFRM(sp)	# Create a stack frame
100        stq     ra, 0(sp)		# Place return address on the stack
101
102        .mask   0x84000000, -8
103        .frame  sp, STARTFRM, ra
104
105/*
106 *	Enable the Floating Point Unit
107 */
108        lda	a0, 1(zero)
109        call_pal PAL_WRFEN_ENTRY
110
111/*
112 *	Every good C program has a main()
113 */
114
115/* If stack pointer was 0, then this is CPU0*/
116        beq	s0,master
117
118        call_pal PAL_WHAMI_ENTRY
119        bis	v0,v0,a0
120        jsr	ra, SlaveLoop
121master:
122        jsr	ra, main
123
124
125
126/*
127 *	The Debug Monitor should never return.
128 *	However, just incase...
129 */
130        ldgp	gp, 0(ra)
131        bsr	zero, _exit
132
133.end	_start
134
135
136
137        .globl  _exit
138        .ent    _exit, 0
139_exit:
140
141        ldq     ra, 0(sp)		# restore return address
142        lda	sp, STARTFRM(sp)	# prune back the stack
143        ret	zero, (ra)		# Back from whence we came
144.end	_exit
145
146                .globl	cServe
147        .ent	cServe 2
148cServe:
149        .option	O1
150        .frame	sp, 0, ra
151        call_pal PAL_CSERVE_ENTRY
152        ret	zero, (ra)
153        .end	cServe
154
155        .globl	wrfen
156        .ent	wrfen 2
157wrfen:
158        .option	O1
159        .frame	sp, 0, ra
160        call_pal PAL_WRFEN_ENTRY
161        ret	zero, (ra)
162        .end	wrfen
163        .globl	consoleCallback
164        .ent	consoleCallback 2
165consoleCallback:
166        br      t0, 2f			# get the current PC
1672:	ldgp    gp, 0(t0)               # init gp
168        lda     sp,-64(sp)
169        stq     ra,0(sp)
170        jsr     CallBackDispatcher
171        ldq     ra,0(sp)
172        lda     sp,64(sp)
173        ret     zero,(ra)
174        .end    consoleCallback
175
176
177        .globl	consoleFixup
178        .ent	consoleFixup 2
179consoleFixup:
180        br      t0, 2f			# get the current PC
1812:	ldgp    gp, 0(t0)               # init gp
182        lda     sp,-64(sp)
183        stq     ra,0(sp)
184        jsr     CallBackFixup
185        ldq     ra,0(sp)
186        lda     sp,64(sp)
187        ret     zero,(ra)
188        .end    consoleFixup
189
190
191
192        .globl	SpinLock
193        .ent	SpinLock 2
194SpinLock:
1951:
196        ldq_l	a1,0(a0)		# interlock complete lock state
197        subl	ra,3,v0			# get calling addr[31:0] + 1
198        blbs	a1,2f			# branch if lock is busy
199        stq_c	v0,0(a0)		# attempt to acquire lock
200        beq	v0,2f			# branch if lost atomicity
201        mb				# ensure memory coherence
202        ret	zero,(ra)		# return to caller (v0 is 1)
2032:
204        br	zero,1b
205        .end	SpinLock
206
207        .globl	loadContext
208        .ent	loadContext 2
209loadContext:
210        .option	O1
211        .frame	sp, 0, ra
212        call_pal PAL_SWPCTX_ENTRY
213        ret	zero, (ra)
214        .end	loadContext
215
216
217        .globl	SlaveSpin          # Very carefully spin wait
218        .ent	SlaveSpin 2        # and swap context without
219SlaveSpin:                         # using any stack space
220        .option	O1
221        .frame	sp, 0, ra
222        mov a0, t0                 # cpu number
223        mov a1, t1                 # cpu rpb pointer (virtual)
224        mov a2, t2                 # what to spin on
225        ldah a0, 3(zero)  # load arg0 with 65536
226test:   .long 0x6000002  # jsr quiesceNs     # wait 65us*3
227        ldl  t3, 0(t2)
228        beq  t3, test
229        zapnot t1,0x1f,a0          # make rpb physical
230        call_pal PAL_SWPCTX_ENTRY  # switch to pcb
231        mov t0, a0                 # setup args for SlaveCmd
232        mov t1, a1
233        jsr SlaveCmd               # call SlaveCmd
234        ret	zero, (ra)         # Should never be reached
235        .end	SlaveSpin
236
237
238