dbmentry.S revision 8023:36c59449dc93 
1/*
2 * Copyright (c) 2003, 2004
3 * The Regents of The University of Michigan
4 * All Rights Reserved
5 *
6 * This code is part of the M5 simulator, developed by Nathan Binkert,
7 * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
8 * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
9 * Schultz.
10 *
11 * Permission is granted to use, copy, create derivative works and
12 * redistribute this software and such derivative works for any purpose,
13 * so long as the copyright notice above, this grant of permission, and
14 * the disclaimer below appear in all copies made; and so long as the
15 * name of The University of Michigan is not used in any advertising or
16 * publicity pertaining to the use or distribution of this software
17 * without specific, written prior authorization.
18 *
19 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
20 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
21 * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
22 * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
24 * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
25 * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
26 * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
27 * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
28 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
29 */
30/*
31 * Copyright 1993 Hewlett-Packard Development Company, L.P.
32 *
33 * Permission is hereby granted, free of charge, to any person
34 * obtaining a copy of this software and associated documentation
35 * files (the "Software"), to deal in the Software without
36 * restriction, including without limitation the rights to use, copy,
37 * modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is
39 * furnished to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be
42 * included in all copies or substantial portions of the Software.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
45 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
46 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
48 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
49 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
50 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
51 * SOFTWARE.
52 */
53
54/*
55 * Debug Monitor Entry code
56 */
57#include "fromHudsonOsf.h"
58
59        .extern myAlphaAccess
60        .text
61
62/* return address and padding to octaword align */
63#define STARTFRM 16
64
65        .globl  _start
66        .ent    _start, 0
67_start:
68_entry:
69        br      t0, 2f			# get the current PC
702:	ldgp    gp, 0(t0)               # init gp
71
72/* Processor 0 start stack frame is begining of physical memory (0)
73   Other processors spin here waiting to get their stacks from
74   Processor 0, then they can progress as normal.
75*/
76        call_pal PAL_WHAMI_ENTRY
77        beq v0, cpuz
78        ldq  t3, m5AlphaAccess
79        addq t3,0x70,t3 # *** If offset in console alpha access struct changes
80                        # This must be changed as well!
81        bis  zero,8,t4
82        mulq t4,v0,t4
83        addq t3,t4,t3
84cpuwait:   ldq  t4, 0(t3)
85        beq  t4, cpuwait
86        bis  t4,t4,sp
87
88
89cpuz:	bis	sp,sp,s0 /* save sp */
90
91slave:	lda	v0,(8*1024)(sp) /* end of page  */
92
93        subq	zero, 1, t0
94        sll	t0, 42, t0
95        bis	t0, v0, sp
96
97        lda     sp, -STARTFRM(sp)	# Create a stack frame
98        stq     ra, 0(sp)		# Place return address on the stack
99
100        .mask   0x84000000, -8
101        .frame  sp, STARTFRM, ra
102
103/*
104 *	Enable the Floating Point Unit
105 */
106        lda	a0, 1(zero)
107        call_pal PAL_WRFEN_ENTRY
108
109/*
110 *	Every good C program has a main()
111 */
112
113/* If stack pointer was 0, then this is CPU0*/
114        beq	s0,master
115
116        call_pal PAL_WHAMI_ENTRY
117        bis	v0,v0,a0
118        jsr	ra, SlaveLoop
119master:
120        jsr	ra, main
121
122
123
124/*
125 *	The Debug Monitor should never return.
126 *	However, just incase...
127 */
128        ldgp	gp, 0(ra)
129        bsr	zero, _exit
130
131.end	_start
132
133
134
135        .globl  _exit
136        .ent    _exit, 0
137_exit:
138
139        ldq     ra, 0(sp)		# restore return address
140        lda	sp, STARTFRM(sp)	# prune back the stack
141        ret	zero, (ra)		# Back from whence we came
142.end	_exit
143
144                .globl	cServe
145        .ent	cServe 2
146cServe:
147        .option	O1
148        .frame	sp, 0, ra
149        call_pal PAL_CSERVE_ENTRY
150        ret	zero, (ra)
151        .end	cServe
152
153        .globl	wrfen
154        .ent	wrfen 2
155wrfen:
156        .option	O1
157        .frame	sp, 0, ra
158        call_pal PAL_WRFEN_ENTRY
159        ret	zero, (ra)
160        .end	wrfen
161        .globl	consoleCallback
162        .ent	consoleCallback 2
163consoleCallback:
164        br      t0, 2f			# get the current PC
1652:	ldgp    gp, 0(t0)               # init gp
166        lda     sp,-64(sp)
167        stq     ra,0(sp)
168        jsr     CallBackDispatcher
169        ldq     ra,0(sp)
170        lda     sp,64(sp)
171        ret     zero,(ra)
172        .end    consoleCallback
173
174
175        .globl	consoleFixup
176        .ent	consoleFixup 2
177consoleFixup:
178        br      t0, 2f			# get the current PC
1792:	ldgp    gp, 0(t0)               # init gp
180        lda     sp,-64(sp)
181        stq     ra,0(sp)
182        jsr     CallBackFixup
183        ldq     ra,0(sp)
184        lda     sp,64(sp)
185        ret     zero,(ra)
186        .end    consoleFixup
187
188
189
190        .globl	SpinLock
191        .ent	SpinLock 2
192SpinLock:
1931:
194        ldq_l	a1,0(a0)		# interlock complete lock state
195        subl	ra,3,v0			# get calling addr[31:0] + 1
196        blbs	a1,2f			# branch if lock is busy
197        stq_c	v0,0(a0)		# attempt to acquire lock
198        beq	v0,2f			# branch if lost atomicity
199        mb				# ensure memory coherence
200        ret	zero,(ra)		# return to caller (v0 is 1)
2012:
202        br	zero,1b
203        .end	SpinLock
204
205        .globl	loadContext
206        .ent	loadContext 2
207loadContext:
208        .option	O1
209        .frame	sp, 0, ra
210        call_pal PAL_SWPCTX_ENTRY
211        ret	zero, (ra)
212        .end	loadContext
213
214
215        .globl	SlaveSpin          # Very carefully spin wait
216        .ent	SlaveSpin 2        # and swap context without
217SlaveSpin:                         # using any stack space
218        .option	O1
219        .frame	sp, 0, ra
220        mov a0, t0                 # cpu number
221        mov a1, t1                 # cpu rpb pointer (virtual)
222        mov a2, t2                 # what to spin on
223
224test:   ldl  t3, 0(t2)
225        beq  t3, test
226        zapnot t1,0x1f,a0          # make rpb physical
227        call_pal PAL_SWPCTX_ENTRY  # switch to pcb
228        mov t0, a0                 # setup args for SlaveCmd
229        mov t1, a1
230        jsr SlaveCmd               # call SlaveCmd
231        ret	zero, (ra)         # Should never be reached
232        .end	SlaveSpin
233
234
235