dbmentry.S revision 8008
18008Ssaidi@eecs.umich.edu 28008Ssaidi@eecs.umich.edu/* taken from ebfw/rom/dbmentry.s */ 38008Ssaidi@eecs.umich.edu 48008Ssaidi@eecs.umich.edu#define EB164 58008Ssaidi@eecs.umich.edu/*#ifndef LINT 68008Ssaidi@eecs.umich.edu.data 78008Ssaidi@eecs.umich.edu.asciiz "$Id: dbmentry.s,v 1.1.1.1 1997/10/30 23:27:12 verghese Exp $" 88008Ssaidi@eecs.umich.edu.text 98008Ssaidi@eecs.umich.edu#endif 108008Ssaidi@eecs.umich.edu*/ 118008Ssaidi@eecs.umich.edu/* 128008Ssaidi@eecs.umich.edu * Debug Monitor Entry code 138008Ssaidi@eecs.umich.edu */ 148008Ssaidi@eecs.umich.edu 158008Ssaidi@eecs.umich.edu#ifndef MAKEDEPEND 168008Ssaidi@eecs.umich.edu#include "ev5_impure.h" 178008Ssaidi@eecs.umich.edu#include "cserve.h" 188008Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" 198008Ssaidi@eecs.umich.edu#endif 208008Ssaidi@eecs.umich.edu 218008Ssaidi@eecs.umich.edu//#include "paldefs.h" 228008Ssaidi@eecs.umich.edu#include "regdefs.h" 238008Ssaidi@eecs.umich.edu#include "eb164.h" 248008Ssaidi@eecs.umich.edu//#include "ledcodes.h" 258008Ssaidi@eecs.umich.edu 268008Ssaidi@eecs.umich.edu .text 278008Ssaidi@eecs.umich.edu 288008Ssaidi@eecs.umich.edu/* return address and padding to octaword align */ 298008Ssaidi@eecs.umich.edu#define STARTFRM 16 308008Ssaidi@eecs.umich.edu 318008Ssaidi@eecs.umich.edu .globl __start 328008Ssaidi@eecs.umich.edu .ent __start, 0 338008Ssaidi@eecs.umich.edu__start: 348008Ssaidi@eecs.umich.edu_entry: 358008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 368008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 378008Ssaidi@eecs.umich.edu 388008Ssaidi@eecs.umich.edu 398008Ssaidi@eecs.umich.edu#ifdef original_xxm 408008Ssaidi@eecs.umich.edu lda a2, CSERVE_K_RD_IMPURE 418008Ssaidi@eecs.umich.edu call_pal PAL_CSERVE_ENTRY 428008Ssaidi@eecs.umich.edu lda v0, CNS_Q_BASE(v0) 438008Ssaidi@eecs.umich.edu 448008Ssaidi@eecs.umich.edu # Add KSEG offset to the impure area 458008Ssaidi@eecs.umich.edu subq zero, 1, t0 468008Ssaidi@eecs.umich.edu sll t0, 42, t0 478008Ssaidi@eecs.umich.edu addq t0, v0, v0 488008Ssaidi@eecs.umich.edu 498008Ssaidi@eecs.umich.edu lda t0, CNS_Q_SIGNATURE(v0) 508008Ssaidi@eecs.umich.edu bic t0, 0x07, t0 # Clear bottom 3 bits to avoid 518008Ssaidi@eecs.umich.edu # allignment errors if the 528008Ssaidi@eecs.umich.edu # impure area is total rubbish 538008Ssaidi@eecs.umich.edu ldq t0, 0x00(t0) 548008Ssaidi@eecs.umich.edu srl t0, 16, t0 # Shift signature into bottom 16 bits. 558008Ssaidi@eecs.umich.edu lda t6, 0xDECB(zero) # Load the expected valid signature. 568008Ssaidi@eecs.umich.edu zap t6, 0xFC, t6 # Clear the upper bits. 578008Ssaidi@eecs.umich.edu cmpeq t0, t6, t0 # Is this a valid signature? 588008Ssaidi@eecs.umich.edu beq t0, 1f # Not valid, don't trust input params. 598008Ssaidi@eecs.umich.edu 608008Ssaidi@eecs.umich.edu/* 618008Ssaidi@eecs.umich.edu * Init the stack at the first 8K boundary 628008Ssaidi@eecs.umich.edu * below the top of memory. 638008Ssaidi@eecs.umich.edu */ 648008Ssaidi@eecs.umich.edu lda t0, CNS_Q_MEM_SIZE(v0) 658008Ssaidi@eecs.umich.edu ldq t0, 0x00(t0) # Load memory size. 668008Ssaidi@eecs.umich.edu subq t0, 1, t0 # Last address in memory 678008Ssaidi@eecs.umich.edu srl t0, 13, t0 # Align to first 8KB boundary 688008Ssaidi@eecs.umich.edu sll t0, 13, sp # below the top of memory. 698008Ssaidi@eecs.umich.edu br zero, 2f 708008Ssaidi@eecs.umich.edu 718008Ssaidi@eecs.umich.edu/* 728008Ssaidi@eecs.umich.edu * If memory size was not passed in via the 738008Ssaidi@eecs.umich.edu * PALcode impure data use the system specific 748008Ssaidi@eecs.umich.edu * MINIMUM_SYSTEM_MEMORY definition. 758008Ssaidi@eecs.umich.edu */ 768008Ssaidi@eecs.umich.edu1: 778008Ssaidi@eecs.umich.edu lda sp, (MINIMUM_SYSTEM_MEMORY&0xffff)(zero) 788008Ssaidi@eecs.umich.edu ldah sp, ((MINIMUM_SYSTEM_MEMORY+0x8000)>>16)(sp) 798008Ssaidi@eecs.umich.edu lda t0, (8*1024)(zero) # Allow for 8KB guard page. 808008Ssaidi@eecs.umich.edu subq sp, t0, sp 818008Ssaidi@eecs.umich.edu 828008Ssaidi@eecs.umich.edu2: 838008Ssaidi@eecs.umich.edu 848008Ssaidi@eecs.umich.edu#endif /* original_xxm */ 858008Ssaidi@eecs.umich.edu 868008Ssaidi@eecs.umich.edu 878008Ssaidi@eecs.umich.edu /* 888008Ssaidi@eecs.umich.edu * SimOS. Stack pointer is start of a valid phys or KSEG page 898008Ssaidi@eecs.umich.edu */ 908008Ssaidi@eecs.umich.edu 918008Ssaidi@eecs.umich.edu bis sp,sp,s0 /* save sp */ 928008Ssaidi@eecs.umich.edu 938008Ssaidi@eecs.umich.eduslave: lda v0,(8*1024)(sp) /* end of page */ 948008Ssaidi@eecs.umich.edu 958008Ssaidi@eecs.umich.edu subq zero, 1, t0 968008Ssaidi@eecs.umich.edu sll t0, 42, t0 978008Ssaidi@eecs.umich.edu bis t0, v0, sp 988008Ssaidi@eecs.umich.edu 998008Ssaidi@eecs.umich.edu#ifdef original_xxm 1008008Ssaidi@eecs.umich.edu # Add KSEG offset to the stack pointer 1018008Ssaidi@eecs.umich.edu subq zero, 1, t0 1028008Ssaidi@eecs.umich.edu sll t0, 42, t0 1038008Ssaidi@eecs.umich.edu addq t0, sp, sp 1048008Ssaidi@eecs.umich.edu#endif 1058008Ssaidi@eecs.umich.edu 1068008Ssaidi@eecs.umich.edu lda sp, -STARTFRM(sp) # Create a stack frame 1078008Ssaidi@eecs.umich.edu stq ra, 0(sp) # Place return address on the stack 1088008Ssaidi@eecs.umich.edu 1098008Ssaidi@eecs.umich.edu .mask 0x84000000, -8 1108008Ssaidi@eecs.umich.edu .frame sp, STARTFRM, ra 1118008Ssaidi@eecs.umich.edu 1128008Ssaidi@eecs.umich.edu/* 1138008Ssaidi@eecs.umich.edu * Enable the Floating Point Unit 1148008Ssaidi@eecs.umich.edu */ 1158008Ssaidi@eecs.umich.edu lda a0, 1(zero) 1168008Ssaidi@eecs.umich.edu call_pal PAL_WRFEN_ENTRY 1178008Ssaidi@eecs.umich.edu 1188008Ssaidi@eecs.umich.edu/* 1198008Ssaidi@eecs.umich.edu * Every good C program has a main() 1208008Ssaidi@eecs.umich.edu */ 1218008Ssaidi@eecs.umich.edu 1228008Ssaidi@eecs.umich.edu beq s0,master 1238008Ssaidi@eecs.umich.edu 1248008Ssaidi@eecs.umich.edu call_pal PAL_WHAMI_ENTRY 1258008Ssaidi@eecs.umich.edu bis v0,v0,a0 1268008Ssaidi@eecs.umich.edu jsr ra, SlaveLoop 1278008Ssaidi@eecs.umich.edumaster: 1288008Ssaidi@eecs.umich.edu jsr ra, main 1298008Ssaidi@eecs.umich.edu 1308008Ssaidi@eecs.umich.edu 1318008Ssaidi@eecs.umich.edu 1328008Ssaidi@eecs.umich.edu/* 1338008Ssaidi@eecs.umich.edu * The Debug Monitor should never return. 1348008Ssaidi@eecs.umich.edu * However, just incase... 1358008Ssaidi@eecs.umich.edu */ 1368008Ssaidi@eecs.umich.edu ldgp gp, 0(ra) 1378008Ssaidi@eecs.umich.edu bsr zero, _exit 1388008Ssaidi@eecs.umich.edu 1398008Ssaidi@eecs.umich.edu.end __start 1408008Ssaidi@eecs.umich.edu 1418008Ssaidi@eecs.umich.edu 1428008Ssaidi@eecs.umich.edu 1438008Ssaidi@eecs.umich.edu .globl _exit 1448008Ssaidi@eecs.umich.edu .ent _exit, 0 1458008Ssaidi@eecs.umich.edu_exit: 1468008Ssaidi@eecs.umich.edu 1478008Ssaidi@eecs.umich.edu ldq ra, 0(sp) # restore return address 1488008Ssaidi@eecs.umich.edu lda sp, STARTFRM(sp) # prune back the stack 1498008Ssaidi@eecs.umich.edu ret zero, (ra) # Back from whence we came 1508008Ssaidi@eecs.umich.edu.end _exit 1518008Ssaidi@eecs.umich.edu 1528008Ssaidi@eecs.umich.edu .globl cServe 1538008Ssaidi@eecs.umich.edu .ent cServe 2 1548008Ssaidi@eecs.umich.educServe: 1558008Ssaidi@eecs.umich.edu .option O1 1568008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1578008Ssaidi@eecs.umich.edu call_pal PAL_CSERVE_ENTRY 1588008Ssaidi@eecs.umich.edu ret zero, (ra) 1598008Ssaidi@eecs.umich.edu .end cServe 1608008Ssaidi@eecs.umich.edu 1618008Ssaidi@eecs.umich.edu .globl wrfen 1628008Ssaidi@eecs.umich.edu .ent wrfen 2 1638008Ssaidi@eecs.umich.eduwrfen: 1648008Ssaidi@eecs.umich.edu .option O1 1658008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1668008Ssaidi@eecs.umich.edu call_pal PAL_WRFEN_ENTRY 1678008Ssaidi@eecs.umich.edu ret zero, (ra) 1688008Ssaidi@eecs.umich.edu .end wrfen 1698008Ssaidi@eecs.umich.edu .globl consoleCallback 1708008Ssaidi@eecs.umich.edu .ent consoleCallback 2 1718008Ssaidi@eecs.umich.educonsoleCallback: 1728008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 1738008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 1748008Ssaidi@eecs.umich.edu lda sp,-64(sp) 1758008Ssaidi@eecs.umich.edu stq ra,0(sp) 1768008Ssaidi@eecs.umich.edu jsr CallBackDispatcher 1778008Ssaidi@eecs.umich.edu ldq ra,0(sp) 1788008Ssaidi@eecs.umich.edu lda sp,64(sp) 1798008Ssaidi@eecs.umich.edu ret zero,(ra) 1808008Ssaidi@eecs.umich.edu .end consoleCallback 1818008Ssaidi@eecs.umich.edu 1828008Ssaidi@eecs.umich.edu 1838008Ssaidi@eecs.umich.edu .globl consoleFixup 1848008Ssaidi@eecs.umich.edu .ent consoleFixup 2 1858008Ssaidi@eecs.umich.educonsoleFixup: 1868008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 1878008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 1888008Ssaidi@eecs.umich.edu lda sp,-64(sp) 1898008Ssaidi@eecs.umich.edu stq ra,0(sp) 1908008Ssaidi@eecs.umich.edu jsr CallBackFixup 1918008Ssaidi@eecs.umich.edu ldq ra,0(sp) 1928008Ssaidi@eecs.umich.edu lda sp,64(sp) 1938008Ssaidi@eecs.umich.edu ret zero,(ra) 1948008Ssaidi@eecs.umich.edu .end consoleFixup 1958008Ssaidi@eecs.umich.edu 1968008Ssaidi@eecs.umich.edu 1978008Ssaidi@eecs.umich.edu 1988008Ssaidi@eecs.umich.edu .globl SpinLock 1998008Ssaidi@eecs.umich.edu .ent SpinLock 2 2008008Ssaidi@eecs.umich.eduSpinLock: 2018008Ssaidi@eecs.umich.edu1: 2028008Ssaidi@eecs.umich.edu ldq_l a1,0(a0) # interlock complete lock state 2038008Ssaidi@eecs.umich.edu subl ra,3,v0 # get calling addr[31:0] + 1 2048008Ssaidi@eecs.umich.edu blbs a1,2f # branch if lock is busy 2058008Ssaidi@eecs.umich.edu stq_c v0,0(a0) # attempt to acquire lock 2068008Ssaidi@eecs.umich.edu beq v0,2f # branch if lost atomicity 2078008Ssaidi@eecs.umich.edu mb # ensure memory coherence 2088008Ssaidi@eecs.umich.edu ret zero,(ra) # return to caller (v0 is 1) 2098008Ssaidi@eecs.umich.edu2: 2108008Ssaidi@eecs.umich.edu br zero,1b 2118008Ssaidi@eecs.umich.edu .end SpinLock 2128008Ssaidi@eecs.umich.edu 2138008Ssaidi@eecs.umich.edu .globl loadContext 2148008Ssaidi@eecs.umich.edu .ent loadContext 2 2158008Ssaidi@eecs.umich.eduloadContext: 2168008Ssaidi@eecs.umich.edu .option O1 2178008Ssaidi@eecs.umich.edu .frame sp, 0, ra 2188008Ssaidi@eecs.umich.edu call_pal PAL_SWPCTX_ENTRY 2198008Ssaidi@eecs.umich.edu ret zero, (ra) 2208008Ssaidi@eecs.umich.edu .end loadContext 2218008Ssaidi@eecs.umich.edu 2228008Ssaidi@eecs.umich.edu 2238008Ssaidi@eecs.umich.edu .globl SlaveSpin # Very carefully spin wait 2248008Ssaidi@eecs.umich.edu .ent SlaveSpin 2 # and swap context without 2258008Ssaidi@eecs.umich.eduSlaveSpin: # using any stack space 2268008Ssaidi@eecs.umich.edu .option O1 2278008Ssaidi@eecs.umich.edu .frame sp, 0, ra 2288008Ssaidi@eecs.umich.edu mov a0, t0 # cpu number 2298008Ssaidi@eecs.umich.edu mov a1, t1 # cpu rpb pointer (virtual) 2308008Ssaidi@eecs.umich.edu mov a2, t2 # what to spin on 2318008Ssaidi@eecs.umich.edu 2328008Ssaidi@eecs.umich.edutest: ldl t3, 0(t2) 2338008Ssaidi@eecs.umich.edu beq t3, test 2348008Ssaidi@eecs.umich.edu zapnot t1,0x1f,a0 # make rpb physical 2358008Ssaidi@eecs.umich.edu call_pal PAL_SWPCTX_ENTRY # switch to pcb 2368008Ssaidi@eecs.umich.edu mov t0, a0 # setup args for SlaveCmd 2378008Ssaidi@eecs.umich.edu mov t1, a1 2388008Ssaidi@eecs.umich.edu jsr SlaveCmd # call SlaveCmd 2398008Ssaidi@eecs.umich.edu ret zero, (ra) # Should never be reached 2408008Ssaidi@eecs.umich.edu .end SlaveSpin 2418008Ssaidi@eecs.umich.edu 2428008Ssaidi@eecs.umich.edu 243