main.cpp revision 12855:588919e0e4aa 
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21865SN/A
22865SN/A  main.cpp --
23865SN/A
24865SN/A  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25865SN/A
26865SN/A *****************************************************************************/
272665Ssaidi@eecs.umich.edu
282665Ssaidi@eecs.umich.edu/*****************************************************************************
292665Ssaidi@eecs.umich.edu
30865SN/A  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31865SN/A  changes you are making here.
3211793Sbrandon.potter@amd.com
3311793Sbrandon.potter@amd.com      Name, Affiliation, Date:
3412334Sgabeblack@google.com  Description of Modification:
356658Snate@binkert.org
36865SN/A *****************************************************************************/
37865SN/A
38865SN/A// Main routine
39865SN/A
405034Smilesck@eecs.umich.edu#include "systemc.h"
415034Smilesck@eecs.umich.edu#include "test.h"
421634SN/A#include "tb.h"
431634SN/A#include "monitor.h"
441634SN/A#include "define.h"
451634SN/A
461634SN/Aint sc_main(int ac, char *av[])
471634SN/A{
481634SN/A  sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
491149SN/A  sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
501149SN/A  sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
511149SN/A
521149SN/A  sc_signal<bool> reset_sig;
531149SN/A
541149SN/A  sc_signal<int> i1;
551149SN/A  sc_signal<int> i2;
561149SN/A  sc_signal<int> i3;
571149SN/A  sc_signal<int> i4;
581149SN/A  sc_signal<int> i5;
591149SN/A
60  sc_signal<bool> cont1;
61  sc_signal<bool> cont2;
62  sc_signal<bool> cont3;
63
64  sc_signal<int> o1;
65  sc_signal<int> o2;
66  sc_signal<int> o3;
67  sc_signal<int> o4;
68  sc_signal<int> o5;
69
70  test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
71	 cont1, cont2, cont3, o1, o2, o3, o4, o5);
72  tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
73	 cont1, cont2, cont3, o1, o2, o3, o4, o5);
74  monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
75	 cont1, cont2, cont3, o1, o2, o3, o4, o5);
76
77  // Simulation Run Control
78  sc_start();
79  return 0;
80}
81