SimpleLTTarget2.h revision 12922
16145SN/A/***************************************************************************** 26145SN/A 36145SN/A Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 46145SN/A more contributor license agreements. See the NOTICE file distributed 56145SN/A with this work for additional information regarding copyright ownership. 66145SN/A Accellera licenses this file to you under the Apache License, Version 2.0 76145SN/A (the "License"); you may not use this file except in compliance with the 86145SN/A License. You may obtain a copy of the License at 96145SN/A 106145SN/A http://www.apache.org/licenses/LICENSE-2.0 116145SN/A 126145SN/A Unless required by applicable law or agreed to in writing, software 136145SN/A distributed under the License is distributed on an "AS IS" BASIS, 146145SN/A WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 156145SN/A implied. See the License for the specific language governing 166145SN/A permissions and limitations under the License. 176145SN/A 186145SN/A *****************************************************************************/ 196145SN/A 206145SN/A#ifndef __SIMPLE_LT_TARGET2_H__ 216145SN/A#define __SIMPLE_LT_TARGET2_H__ 226145SN/A 236145SN/A#include "tlm.h" 246145SN/A#include "tlm_utils/passthrough_target_socket.h" 256145SN/A#include <cassert> 266145SN/A#include <vector> 276145SN/A 286145SN/Aclass SimpleLTTarget2 : public sc_core::sc_module 2910441Snilay@cs.wisc.edu{ 3010441Snilay@cs.wisc.edupublic: 316145SN/A typedef tlm::tlm_generic_payload transaction_type; 327455SN/A typedef tlm::tlm_phase phase_type; 336154SN/A typedef tlm::tlm_sync_enum sync_enum_type; 346154SN/A typedef tlm_utils::passthrough_target_socket<SimpleLTTarget2> target_socket_type; 356145SN/A 366145SN/A 377039SN/Apublic: 387039SN/A target_socket_type socket; 397039SN/A 407039SN/Apublic: 417039SN/A SimpleLTTarget2(sc_core::sc_module_name name) : 426145SN/A sc_core::sc_module(name), 436145SN/A socket("socket") 446145SN/A { 457055SN/A // register nb_transport method 467055SN/A socket.register_b_transport(this, &SimpleLTTarget2::myBTransport); 476467SN/A socket.register_nb_transport_fw(this, &SimpleLTTarget2::myNBTransport); 487039SN/A socket.register_get_direct_mem_ptr(this, &SimpleLTTarget2::myGetDMIPtr); 496467SN/A 506467SN/A // TODO: we don't register the transport_dbg callback here, so we 516467SN/A // can test if something bad happens 527039SN/A // REGISTER_DEBUGTRANSPORT(socket, transport_dbg, 0); 537039SN/A } 547039SN/A 557039SN/A void myBTransport(transaction_type& trans, 566145SN/A sc_core::sc_time& t) 577039SN/A { 5811025Snilay@cs.wisc.edu sc_dt::uint64 address = trans.get_address(); 596145SN/A assert(address < 400); 607039SN/A 617039SN/A unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr()); 627039SN/A if (trans.get_command() == tlm::TLM_WRITE_COMMAND) { 6311025Snilay@cs.wisc.edu std::cout << name() << ": Received write request: A = 0x" 646145SN/A << std::hex << (unsigned int)address 657039SN/A << ", D = 0x" << data << std::dec 6611025Snilay@cs.wisc.edu << " @ " << sc_core::sc_time_stamp() << std::endl; 676145SN/A 6811025Snilay@cs.wisc.edu *reinterpret_cast<unsigned int*>(&mMem[address]) = data; 696145SN/A t += sc_core::sc_time(10, sc_core::SC_NS); 707039SN/A 7111025Snilay@cs.wisc.edu } else { 726145SN/A std::cout << name() << ": Received read request: A = 0x" 737039SN/A << std::hex << (unsigned int)address << std::dec 7411025Snilay@cs.wisc.edu << " @ " << sc_core::sc_time_stamp() << std::endl; 7511025Snilay@cs.wisc.edu 766145SN/A data = *reinterpret_cast<unsigned int*>(&mMem[address]); 777039SN/A t += sc_core::sc_time(100, sc_core::SC_NS); 7811025Snilay@cs.wisc.edu } 7911025Snilay@cs.wisc.edu 806145SN/A trans.set_response_status(tlm::TLM_OK_RESPONSE); 817039SN/A 827055SN/A trans.set_dmi_allowed(true); 836145SN/A } 847039SN/A 857039SN/A sync_enum_type myNBTransport(transaction_type& trans, 867039SN/A phase_type& phase, 877039SN/A sc_core::sc_time& t) 886145SN/A { 897039SN/A assert(phase == tlm::BEGIN_REQ); 9011025Snilay@cs.wisc.edu 916145SN/A // Never blocks, so call b_transport implementation 926145SN/A myBTransport(trans, t); 936145SN/A // LT target 947055SN/A // - always return TLM_COMPLETED 957055SN/A // - not necessary to update phase (if TLM_COMPLETED is returned) 966145SN/A return tlm::TLM_COMPLETED; 977039SN/A } 987055SN/A 997039SN/A unsigned int transport_dbg(transaction_type& r) 1006145SN/A { 1016145SN/A if (r.get_address() >= 400) return 0; 1026145SN/A 1037039SN/A unsigned int tmp = (int)r.get_address(); 1046467SN/A unsigned int num_bytes; 1056145SN/A if (tmp + r.get_data_length() >= 400) { 1066145SN/A num_bytes = 400 - tmp; 1076145SN/A 1086145SN/A } else { 1096145SN/A num_bytes = r.get_data_length(); 1107039SN/A } 11111025Snilay@cs.wisc.edu if (r.is_read()) { 1126145SN/A for (unsigned int i = 0; i < num_bytes; ++i) { 11311025Snilay@cs.wisc.edu r.get_data_ptr()[i] = mMem[i + tmp]; 1146145SN/A } 1156145SN/A 1166145SN/A } else { 1177039SN/A for (unsigned int i = 0; i < num_bytes; ++i) { 11811025Snilay@cs.wisc.edu mMem[i + tmp] = r.get_data_ptr()[i]; 1196145SN/A } 1207039SN/A } 1216145SN/A return num_bytes; 1226145SN/A } 1236145SN/A 1246145SN/A bool myGetDMIPtr(transaction_type& trans, 1256145SN/A tlm::tlm_dmi& dmi_data) 1267039SN/A { 12711025Snilay@cs.wisc.edu sc_dt::uint64 address = trans.get_address(); 1286145SN/A if (address < 400) { 1297039SN/A dmi_data.allow_read_write(); 1308084SN/A dmi_data.set_start_address(0x0); 1317039SN/A dmi_data.set_end_address(399); 13211025Snilay@cs.wisc.edu dmi_data.set_dmi_ptr(mMem); 1336145SN/A dmi_data.set_read_latency(sc_core::sc_time(100, sc_core::SC_NS)); 1346145SN/A dmi_data.set_write_latency(sc_core::sc_time(10, sc_core::SC_NS)); 1356145SN/A return true; 1366145SN/A 1377039SN/A } else { 13811025Snilay@cs.wisc.edu // should not happen 1396145SN/A dmi_data.set_start_address(address); 14011025Snilay@cs.wisc.edu dmi_data.set_end_address(address); 1416145SN/A return false; 1426145SN/A 1436145SN/A } 1446145SN/A } 14511025Snilay@cs.wisc.eduprivate: 14611025Snilay@cs.wisc.edu unsigned char mMem[400]; 1476145SN/A}; 1487805SN/A 1497806SN/A#endif 1506145SN/A