ExplicitLTTarget.h revision 12922 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
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6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
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19
20#ifndef __EXPLICIT_LT_TARGET_H__
21#define __EXPLICIT_LT_TARGET_H__
22
23#include "tlm.h"
24#include "tlm_utils/simple_target_socket.h"
25//#include <systemc>
26#include <cassert>
27#include <vector>
28#include <queue>
29//#include <iostream>
30
31class ExplicitLTTarget : public sc_core::sc_module
32{
33public:
34  typedef tlm::tlm_generic_payload                 transaction_type;
35  typedef tlm::tlm_phase                           phase_type;
36  typedef tlm::tlm_sync_enum                       sync_enum_type;
37  typedef tlm_utils::simple_target_socket<ExplicitLTTarget>     target_socket_type;
38
39public:
40  target_socket_type socket;
41
42public:
43  SC_HAS_PROCESS(ExplicitLTTarget);
44  ExplicitLTTarget(sc_core::sc_module_name name) :
45    sc_core::sc_module(name),
46    socket("socket")
47  {
48    // register nb_transport method
49    socket.register_b_transport(this, &ExplicitLTTarget::myBTransport);
50    socket.register_transport_dbg(this, &ExplicitLTTarget::transport_dbg);
51  }
52
53  void myBTransport(transaction_type& trans, sc_core::sc_time& t)
54  {
55    sc_dt::uint64 address = trans.get_address();
56    assert(address < 400);
57
58    unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
59    if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
60      std::cout << name() << ": Received write request: A = 0x"
61                << std::hex << (unsigned int)address << ", D = 0x" << data
62                << std::dec << " @ " << sc_core::sc_time_stamp()
63                << std::endl;
64
65      *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
66
67      // Synchronization on demand (eg need to assert an interrupt)
68      // Wait for passed timing annotation + wait for an extra 50 ns
69      wait(t + sc_core::sc_time(50, sc_core::SC_NS));
70      t = sc_core::SC_ZERO_TIME;
71
72      // We are synchronized, we can read/write sc_signals, wait,...
73
74      *reinterpret_cast<unsigned int*>(trans.get_data_ptr()) =
75        *reinterpret_cast<unsigned int*>(&mMem[address]);
76
77    } else {
78      std::cout << name() << ": Received read request: A = 0x"
79                << std::hex << (unsigned int)address
80                << std::dec << " @ " << sc_core::sc_time_stamp()
81                << std::endl;
82
83      data = *reinterpret_cast<unsigned int*>(&mMem[address]);
84
85      // Finish transaction (use timing annotation)
86      t += sc_core::sc_time(100, sc_core::SC_NS);
87    }
88
89    trans.set_response_status(tlm::TLM_OK_RESPONSE);
90  }
91
92  unsigned int transport_dbg(transaction_type& r)
93  {
94    if (r.get_address() >= 400) return 0;
95
96    unsigned int tmp = (int)r.get_address();
97    unsigned int num_bytes;
98    if (tmp + r.get_data_length() >= 400) {
99      num_bytes = 400 - tmp;
100
101    } else {
102      num_bytes = r.get_data_length();
103    }
104    if (!r.is_read() && !r.is_write()) {
105      return 0;
106	}
107    if (r.is_read()) {
108      for (unsigned int i = 0; i < num_bytes; ++i) {
109        r.get_data_ptr()[i] = mMem[i + tmp];
110      }
111
112    } else {
113      for (unsigned int i = 0; i < num_bytes; ++i) {
114        mMem[i + tmp] = r.get_data_ptr()[i];
115      }
116    }
117    return num_bytes;
118  }
119
120private:
121  unsigned char mMem[400];
122};
123
124#endif
125