vptr.hh revision 1762
16145SN/A/* 26145SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 2910301Snilay@cs.wisc.edu#ifndef __ARCH_ALPHA_VPTR_HH__ 309171SN/A#define __ARCH_ALPHA_VPTR_HH__ 316145SN/A 326467SN/A#include "arch/alpha/vtophys.hh" 339507SN/A 346145SN/Aclass ExecContext; 357039SN/A 369465SN/Atemplate <class T> 379465SN/Aclass VPtr 387039SN/A{ 3911025Snilay@cs.wisc.edu public: 406145SN/A typedef T Type; 416145SN/A 427039SN/A private: 437039SN/A ExecContext *xc; 447039SN/A Addr ptr; 457455SN/A 467039SN/A public: 476145SN/A ExecContext *GetXC() const { return xc; } 487039SN/A Addr GetPointer() const { return ptr; } 497039SN/A 507039SN/A public: 517039SN/A explicit VPtr(ExecContext *_xc, Addr p = 0) : xc(_xc), ptr(p) { } 529465SN/A template <class U> 536145SN/A VPtr(const VPtr<U> &vp) : xc(vp.GetXC()), ptr(vp.GetPointer()) {} 546145SN/A ~VPtr() {} 5511025Snilay@cs.wisc.edu 567039SN/A bool operator!() const 576145SN/A { 587039SN/A return ptr == 0; 596145SN/A } 607039SN/A 617039SN/A VPtr<T> operator+(int offset) 627039SN/A { 637039SN/A VPtr<T> ptr(*this); 647039SN/A ptr += offset; 656145SN/A 666145SN/A return ptr; 677039SN/A } 6811025Snilay@cs.wisc.edu 696145SN/A const VPtr<T> &operator+=(int offset) 7011025Snilay@cs.wisc.edu { 717039SN/A ptr += offset; 727455SN/A assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T) 739499SN/A < AlphaISA::PageBytes); 749499SN/A 757455SN/A return *this; 767039SN/A } 779600SN/A 789600SN/A const VPtr<T> &operator=(Addr p) 797039SN/A { 806145SN/A assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes); 817039SN/A ptr = p; 827039SN/A 837039SN/A return *this; 847039SN/A } 856145SN/A 866145SN/A template <class U> 877039SN/A const VPtr<T> &operator=(const VPtr<U> &vp) 8811025Snilay@cs.wisc.edu { 896145SN/A xc = vp.GetXC(); 9011025Snilay@cs.wisc.edu ptr = vp.GetPointer(); 917455SN/A 927455SN/A return *this; 936145SN/A } 947039SN/A 957039SN/A operator T *() 967039SN/A { 977039SN/A void *addr = vtomem(xc, ptr, sizeof(T)); 986145SN/A return (T *)addr; 996145SN/A } 1007039SN/A 1017055SN/A T *operator->() 1026145SN/A { 1036145SN/A void *addr = vtomem(xc, ptr, sizeof(T)); 1046145SN/A return (T *)addr; 1057039SN/A } 1067039SN/A 1077039SN/A T &operator*() 1087455SN/A { 1097455SN/A void *addr = vtomem(xc, ptr, sizeof(T)); 1107039SN/A return *(T *)addr; 1117039SN/A } 1126145SN/A}; 1137455SN/A 1147455SN/A#endif // __ARCH_ALPHA_VPTR_HH__ 1156145SN/A