stat_control.cc revision 9848:a733a8eb6363
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Nathan Binkert 41 * Sascha Bischoff 42 */ 43 44// This file will contain default statistics for the simulator that 45// don't really belong to a specific simulator object 46 47#include <fstream> 48#include <iostream> 49#include <list> 50 51#include "base/callback.hh" 52#include "base/hostinfo.hh" 53#include "base/statistics.hh" 54#include "base/time.hh" 55#include "config/the_isa.hh" 56#if THE_ISA == NO_ISA 57#include "arch/noisa/cpu_dummy.hh" 58#else 59#include "cpu/base.hh" 60#endif 61 62#include "sim/eventq_impl.hh" 63#include "sim/stat_control.hh" 64 65using namespace std; 66 67Stats::Formula simSeconds; 68Stats::Value simTicks; 69Stats::Value finalTick; 70Stats::Value simFreq; 71 72namespace Stats { 73 74Time statTime(true); 75Tick startTick; 76 77Event *dumpEvent; 78 79struct SimTicksReset : public Callback 80{ 81 void process() 82 { 83 statTime.setTimer(); 84 startTick = curTick(); 85 } 86}; 87 88double 89statElapsedTime() 90{ 91 Time now; 92 now.setTimer(); 93 94 Time elapsed = now - statTime; 95 return elapsed; 96} 97 98Tick 99statElapsedTicks() 100{ 101 return curTick() - startTick; 102} 103 104Tick 105statFinalTick() 106{ 107 return curTick(); 108} 109 110SimTicksReset simTicksReset; 111 112struct Global 113{ 114 Stats::Formula hostInstRate; 115 Stats::Formula hostOpRate; 116 Stats::Formula hostTickRate; 117 Stats::Value hostMemory; 118 Stats::Value hostSeconds; 119 120 Stats::Value simInsts; 121 Stats::Value simOps; 122 123 Global(); 124}; 125 126Global::Global() 127{ 128 simInsts 129 .functor(BaseCPU::numSimulatedInsts) 130 .name("sim_insts") 131 .desc("Number of instructions simulated") 132 .precision(0) 133 .prereq(simInsts) 134 ; 135 136 simOps 137 .functor(BaseCPU::numSimulatedOps) 138 .name("sim_ops") 139 .desc("Number of ops (including micro ops) simulated") 140 .precision(0) 141 .prereq(simOps) 142 ; 143 144 simSeconds 145 .name("sim_seconds") 146 .desc("Number of seconds simulated") 147 ; 148 149 simFreq 150 .scalar(SimClock::Frequency) 151 .name("sim_freq") 152 .desc("Frequency of simulated ticks") 153 ; 154 155 simTicks 156 .functor(statElapsedTicks) 157 .name("sim_ticks") 158 .desc("Number of ticks simulated") 159 ; 160 161 finalTick 162 .functor(statFinalTick) 163 .name("final_tick") 164 .desc("Number of ticks from beginning of simulation \ 165(restored from checkpoints and never reset)") 166 ; 167 168 hostInstRate 169 .name("host_inst_rate") 170 .desc("Simulator instruction rate (inst/s)") 171 .precision(0) 172 .prereq(simInsts) 173 ; 174 175 hostOpRate 176 .name("host_op_rate") 177 .desc("Simulator op (including micro ops) rate (op/s)") 178 .precision(0) 179 .prereq(simOps) 180 ; 181 182 hostMemory 183 .functor(memUsage) 184 .name("host_mem_usage") 185 .desc("Number of bytes of host memory used") 186 .prereq(hostMemory) 187 ; 188 189 hostSeconds 190 .functor(statElapsedTime) 191 .name("host_seconds") 192 .desc("Real time elapsed on the host") 193 .precision(2) 194 ; 195 196 hostTickRate 197 .name("host_tick_rate") 198 .desc("Simulator tick rate (ticks/s)") 199 .precision(0) 200 ; 201 202 simSeconds = simTicks / simFreq; 203 hostInstRate = simInsts / hostSeconds; 204 hostOpRate = simOps / hostSeconds; 205 hostTickRate = simTicks / hostSeconds; 206 207 registerResetCallback(&simTicksReset); 208} 209 210void 211initSimStats() 212{ 213 static Global global; 214} 215 216/** 217 * Event to dump and/or reset the statistics. 218 */ 219class StatEvent : public Event 220{ 221 private: 222 bool dump; 223 bool reset; 224 Tick repeat; 225 226 public: 227 StatEvent(bool _dump, bool _reset, Tick _repeat) 228 : Event(Stat_Event_Pri, AutoDelete), 229 dump(_dump), reset(_reset), repeat(_repeat) 230 { 231 } 232 233 virtual void 234 process() 235 { 236 if (dump) 237 Stats::dump(); 238 239 if (reset) 240 Stats::reset(); 241 242 if (repeat) { 243 Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat); 244 } 245 } 246}; 247 248void 249schedStatEvent(bool dump, bool reset, Tick when, Tick repeat) 250{ 251 dumpEvent = new StatEvent(dump, reset, repeat); 252 mainEventQueue.schedule(dumpEvent, when); 253} 254 255void 256periodicStatDump(Tick period) 257{ 258 /* 259 * If the period is set to 0, then we do not want to dump periodically, 260 * thus we deschedule the event. Else, if the period is not 0, but the event 261 * has already been scheduled, we need to get rid of the old event before we 262 * create a new one, as the old event will no longer be moved forward in the 263 * event that we resume from a checkpoint. 264 */ 265 if (dumpEvent != NULL && (period == 0 || dumpEvent->scheduled())) { 266 // Event should AutoDelete, so we do not need to free it. 267 mainEventQueue.deschedule(dumpEvent); 268 } 269 270 /* 271 * If the period is not 0, we schedule the event. If this is called with a 272 * period that is less than the current tick, then we shift the first dump 273 * by curTick. This ensures that we do not schedule the event is the past. 274 */ 275 if (period != 0) { 276 // Schedule the event 277 if (period >= curTick()) { 278 schedStatEvent(true, true, (Tick)period, (Tick)period); 279 } else { 280 schedStatEvent(true, true, (Tick)period + curTick(), (Tick)period); 281 } 282 } 283} 284 285void 286updateEvents() 287{ 288 /* 289 * If the dumpEvent has been scheduled, but is scheduled in the past, then 290 * we need to shift the event to be at a valid point in time. Therefore, we 291 * shift the event by curTick. 292 */ 293 if (dumpEvent != NULL && 294 (dumpEvent->scheduled() && dumpEvent->when() < curTick())) { 295 // shift by curTick() and reschedule 296 Tick _when = dumpEvent->when(); 297 mainEventQueue.reschedule(dumpEvent, _when + curTick()); 298 } 299} 300 301} // namespace Stats 302