stat_control.cc revision 8834:21e8d54ecf07
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 */ 30 31// This file will contain default statistics for the simulator that 32// don't really belong to a specific simulator object 33 34#include <fstream> 35#include <iostream> 36#include <list> 37 38#include "base/callback.hh" 39#include "base/hostinfo.hh" 40#include "base/statistics.hh" 41#include "base/time.hh" 42#include "config/the_isa.hh" 43#if THE_ISA == NO_ISA 44#include "arch/noisa/cpu_dummy.hh" 45#else 46#include "cpu/base.hh" 47#endif 48 49#include "sim/eventq.hh" 50#include "sim/stat_control.hh" 51 52using namespace std; 53 54Stats::Formula simSeconds; 55Stats::Value simTicks; 56Stats::Value finalTick; 57Stats::Value simFreq; 58 59namespace Stats { 60 61Time statTime(true); 62Tick startTick; 63 64struct SimTicksReset : public Callback 65{ 66 void process() 67 { 68 statTime.setTimer(); 69 startTick = curTick(); 70 } 71}; 72 73double 74statElapsedTime() 75{ 76 Time now; 77 now.setTimer(); 78 79 Time elapsed = now - statTime; 80 return elapsed; 81} 82 83Tick 84statElapsedTicks() 85{ 86 return curTick() - startTick; 87} 88 89Tick 90statFinalTick() 91{ 92 return curTick(); 93} 94 95SimTicksReset simTicksReset; 96 97struct Global 98{ 99 Stats::Formula hostInstRate; 100 Stats::Formula hostOpRate; 101 Stats::Formula hostTickRate; 102 Stats::Value hostMemory; 103 Stats::Value hostSeconds; 104 105 Stats::Value simInsts; 106 Stats::Value simOps; 107 108 Global(); 109}; 110 111Global::Global() 112{ 113 simInsts 114 .functor(BaseCPU::numSimulatedInsts) 115 .name("sim_insts") 116 .desc("Number of instructions simulated") 117 .precision(0) 118 .prereq(simInsts) 119 ; 120 121 simOps 122 .functor(BaseCPU::numSimulatedOps) 123 .name("sim_ops") 124 .desc("Number of ops (including micro ops) simulated") 125 .precision(0) 126 .prereq(simOps) 127 ; 128 129 simSeconds 130 .name("sim_seconds") 131 .desc("Number of seconds simulated") 132 ; 133 134 simFreq 135 .scalar(SimClock::Frequency) 136 .name("sim_freq") 137 .desc("Frequency of simulated ticks") 138 ; 139 140 simTicks 141 .functor(statElapsedTicks) 142 .name("sim_ticks") 143 .desc("Number of ticks simulated") 144 ; 145 146 finalTick 147 .functor(statFinalTick) 148 .name("final_tick") 149 .desc("Number of ticks from beginning of simulation \ 150(restored from checkpoints and never reset)") 151 ; 152 153 hostInstRate 154 .name("host_inst_rate") 155 .desc("Simulator instruction rate (inst/s)") 156 .precision(0) 157 .prereq(simInsts) 158 ; 159 160 hostOpRate 161 .name("host_op_rate") 162 .desc("Simulator op (including micro ops) rate (op/s)") 163 .precision(0) 164 .prereq(simOps) 165 ; 166 167 hostMemory 168 .functor(memUsage) 169 .name("host_mem_usage") 170 .desc("Number of bytes of host memory used") 171 .prereq(hostMemory) 172 ; 173 174 hostSeconds 175 .functor(statElapsedTime) 176 .name("host_seconds") 177 .desc("Real time elapsed on the host") 178 .precision(2) 179 ; 180 181 hostTickRate 182 .name("host_tick_rate") 183 .desc("Simulator tick rate (ticks/s)") 184 .precision(0) 185 ; 186 187 simSeconds = simTicks / simFreq; 188 hostInstRate = simInsts / hostSeconds; 189 hostOpRate = simOps / hostSeconds; 190 hostTickRate = simTicks / hostSeconds; 191 192 registerResetCallback(&simTicksReset); 193} 194 195void 196initSimStats() 197{ 198 static Global global; 199} 200 201class StatEvent : public Event 202{ 203 private: 204 bool dump; 205 bool reset; 206 Tick repeat; 207 208 public: 209 StatEvent(bool _dump, bool _reset, Tick _repeat) 210 : Event(Stat_Event_Pri, AutoDelete), 211 dump(_dump), reset(_reset), repeat(_repeat) 212 { 213 } 214 215 virtual void 216 process() 217 { 218 if (dump) 219 Stats::dump(); 220 221 if (reset) 222 Stats::reset(); 223 224 if (repeat) { 225 Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat); 226 } 227 } 228}; 229 230void 231schedStatEvent(bool dump, bool reset, Tick when, Tick repeat) 232{ 233 Event *event = new StatEvent(dump, reset, repeat); 234 mainEventQueue.schedule(event, when); 235} 236 237} // namespace Stats 238