sim_object.hh revision 11168
15217Ssaidi@eecs.umich.edu/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2015 ARM Limited 39920Syasuko.eckert@amd.com * All rights reserved 49428SAndreas.Sandberg@ARM.com * 59428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139428SAndreas.Sandberg@ARM.com * 149428SAndreas.Sandberg@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 155217Ssaidi@eecs.umich.edu * Copyright (c) 2010 Advanced Micro Devices, Inc. 165217Ssaidi@eecs.umich.edu * All rights reserved. 175217Ssaidi@eecs.umich.edu * 185217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu * 295217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu * 415217Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 425217Ssaidi@eecs.umich.edu * Nathan Binkert 435217Ssaidi@eecs.umich.edu */ 4411793Sbrandon.potter@amd.com 4511793Sbrandon.potter@amd.com/* @file 4611627Smichael.lebeane@amd.com * User Console Definitions 475217Ssaidi@eecs.umich.edu */ 485217Ssaidi@eecs.umich.edu 496658Snate@binkert.org#ifndef __SIM_OBJECT_HH__ 509441SAndreas.Sandberg@ARM.com#define __SIM_OBJECT_HH__ 519441SAndreas.Sandberg@ARM.com 528232Snate@binkert.org#include <iostream> 5311627Smichael.lebeane@amd.com#include <list> 5411627Smichael.lebeane@amd.com#include <map> 559441SAndreas.Sandberg@ARM.com#include <string> 565217Ssaidi@eecs.umich.edu#include <vector> 575217Ssaidi@eecs.umich.edu 585217Ssaidi@eecs.umich.edu#include "enums/MemoryMode.hh" 595217Ssaidi@eecs.umich.edu#include "params/SimObject.hh" 605217Ssaidi@eecs.umich.edu#include "sim/drain.hh" 615217Ssaidi@eecs.umich.edu#include "sim/eventq_impl.hh" 625217Ssaidi@eecs.umich.edu#include "sim/serialize.hh" 635217Ssaidi@eecs.umich.edu 645217Ssaidi@eecs.umich.educlass BaseCPU; 655217Ssaidi@eecs.umich.educlass Event; 665217Ssaidi@eecs.umich.educlass ProbeManager; 675217Ssaidi@eecs.umich.edu/** 685217Ssaidi@eecs.umich.edu * Abstract superclass for simulation objects. Represents things that 695217Ssaidi@eecs.umich.edu * correspond to physical components and can be specified via the 705217Ssaidi@eecs.umich.edu * config file (CPUs, caches, etc.). 715217Ssaidi@eecs.umich.edu * 725217Ssaidi@eecs.umich.edu * SimObject initialization is controlled by the instantiate method in 735217Ssaidi@eecs.umich.edu * src/python/m5/simulate.py. There are slightly different 745217Ssaidi@eecs.umich.edu * initialization paths when starting the simulation afresh and when 755217Ssaidi@eecs.umich.edu * loading from a checkpoint. After instantiation and connecting 765217Ssaidi@eecs.umich.edu * ports, simulate.py initializes the object using the following call 775217Ssaidi@eecs.umich.edu * sequence: 785217Ssaidi@eecs.umich.edu * 7912109SRekai.GonzalezAlberquilla@arm.com * <ol> 8012109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::init() 8112109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::regStats() 8212109SRekai.GonzalezAlberquilla@arm.com * <li><ul> 8312109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::initState() if starting afresh. 8412109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::loadState() if restoring from a checkpoint. 8512109SRekai.GonzalezAlberquilla@arm.com * </ul> 8612109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::resetStats() 8712109SRekai.GonzalezAlberquilla@arm.com * <li>SimObject::startup() 8812109SRekai.GonzalezAlberquilla@arm.com * <li>Drainable::drainResume() if resuming from a checkpoint. 895217Ssaidi@eecs.umich.edu * </ol> 905217Ssaidi@eecs.umich.edu * 915217Ssaidi@eecs.umich.edu * @note Whenever a method is called on all objects in the simulator's 925217Ssaidi@eecs.umich.edu * object tree (e.g., init(), startup(), or loadState()), a pre-order 935217Ssaidi@eecs.umich.edu * depth-first traversal is performed (see descendants() in 945217Ssaidi@eecs.umich.edu * SimObject.py). This has the effect of calling the method on the 955217Ssaidi@eecs.umich.edu * parent node <i>before</i> its children. 965217Ssaidi@eecs.umich.edu */ 979920Syasuko.eckert@amd.comclass SimObject : public EventManager, public Serializable, public Drainable 989920Syasuko.eckert@amd.com{ 999920Syasuko.eckert@amd.com private: 1009920Syasuko.eckert@amd.com typedef std::vector<SimObject *> SimObjectList; 1019920Syasuko.eckert@amd.com 1029920Syasuko.eckert@amd.com /** List of all instantiated simulation objects. */ 1039920Syasuko.eckert@amd.com static SimObjectList simObjectList; 1049920Syasuko.eckert@amd.com 1057720Sgblack@eecs.umich.edu /** Manager coordinates hooking up probe points with listeners. */ 1067720Sgblack@eecs.umich.edu ProbeManager *probeManager; 1075712Shsul@eecs.umich.edu 1085712Shsul@eecs.umich.edu protected: 1095217Ssaidi@eecs.umich.edu /** Cached copy of the object parameters. */ 1105217Ssaidi@eecs.umich.edu const SimObjectParams *_params; 1115714Shsul@eecs.umich.edu 11211005Sandreas.sandberg@arm.com public: 11311005Sandreas.sandberg@arm.com typedef SimObjectParams Params; 11411005Sandreas.sandberg@arm.com const Params *params() const { return _params; } 1155714Shsul@eecs.umich.edu SimObject(const Params *_params); 1165714Shsul@eecs.umich.edu virtual ~SimObject(); 1175714Shsul@eecs.umich.edu 1185217Ssaidi@eecs.umich.edu public: 1199428SAndreas.Sandberg@ARM.com 1209428SAndreas.Sandberg@ARM.com virtual const std::string name() const { return params()->name; } 12111627Smichael.lebeane@amd.com 12211627Smichael.lebeane@amd.com /** 12311627Smichael.lebeane@amd.com * init() is called after all C++ SimObjects have been created and 12411627Smichael.lebeane@amd.com * all ports are connected. Initializations that are independent 12511627Smichael.lebeane@amd.com * of unserialization but rely on a fully instantiated and 12611627Smichael.lebeane@amd.com * connected SimObject graph should be done here. 12711627Smichael.lebeane@amd.com */ 12811627Smichael.lebeane@amd.com virtual void init(); 12911627Smichael.lebeane@amd.com 13011627Smichael.lebeane@amd.com /** 13111627Smichael.lebeane@amd.com * loadState() is called on each SimObject when restoring from a 13211627Smichael.lebeane@amd.com * checkpoint. The default implementation simply calls 13311627Smichael.lebeane@amd.com * unserialize() if there is a corresponding section in the 13411627Smichael.lebeane@amd.com * checkpoint. However, objects can override loadState() to get 13511627Smichael.lebeane@amd.com * other behaviors, e.g., doing other programmed initializations 13611627Smichael.lebeane@amd.com * after unserialize(), or complaining if no checkpoint section is 13711627Smichael.lebeane@amd.com * found. 13811627Smichael.lebeane@amd.com * 13911627Smichael.lebeane@amd.com * @param cp Checkpoint to restore the state from. 14011627Smichael.lebeane@amd.com */ 14111627Smichael.lebeane@amd.com virtual void loadState(CheckpointIn &cp); 14211627Smichael.lebeane@amd.com 14311627Smichael.lebeane@amd.com /** 14411627Smichael.lebeane@amd.com * initState() is called on each SimObject when *not* restoring 14511627Smichael.lebeane@amd.com * from a checkpoint. This provides a hook for state 14611627Smichael.lebeane@amd.com * initializations that are only required for a "cold start". 14711627Smichael.lebeane@amd.com */ 14811627Smichael.lebeane@amd.com virtual void initState(); 14911627Smichael.lebeane@amd.com 15011627Smichael.lebeane@amd.com /** 15111627Smichael.lebeane@amd.com * Register statistics for this object. 15211627Smichael.lebeane@amd.com */ 15311627Smichael.lebeane@amd.com virtual void regStats(); 15410905Sandreas.sandberg@arm.com 1559428SAndreas.Sandberg@ARM.com /** 1569428SAndreas.Sandberg@ARM.com * Reset statistics associated with this object. 1579428SAndreas.Sandberg@ARM.com */ 1589428SAndreas.Sandberg@ARM.com virtual void resetStats(); 1599428SAndreas.Sandberg@ARM.com 1609428SAndreas.Sandberg@ARM.com /** 1619428SAndreas.Sandberg@ARM.com * Register probe points for this object. 1629428SAndreas.Sandberg@ARM.com */ 16310905Sandreas.sandberg@arm.com virtual void regProbePoints(); 1649428SAndreas.Sandberg@ARM.com 16512109SRekai.GonzalezAlberquilla@arm.com /** 16612109SRekai.GonzalezAlberquilla@arm.com * Register probe listeners for this object. 16712109SRekai.GonzalezAlberquilla@arm.com */ 16812109SRekai.GonzalezAlberquilla@arm.com virtual void regProbeListeners(); 16912109SRekai.GonzalezAlberquilla@arm.com 17012109SRekai.GonzalezAlberquilla@arm.com /** 1719428SAndreas.Sandberg@ARM.com * Get the probe manager for this object. 1729428SAndreas.Sandberg@ARM.com */ 1739428SAndreas.Sandberg@ARM.com ProbeManager *getProbeManager(); 1749428SAndreas.Sandberg@ARM.com 1759428SAndreas.Sandberg@ARM.com /** 1769920Syasuko.eckert@amd.com * startup() is the final initialization call before simulation. 1779920Syasuko.eckert@amd.com * All state is initialized (including unserialized state, if any, 1789920Syasuko.eckert@amd.com * such as the curTick() value), so this is the appropriate place to 1799920Syasuko.eckert@amd.com * schedule initial event(s) for objects that need them. 1809920Syasuko.eckert@amd.com */ 1819920Syasuko.eckert@amd.com virtual void startup(); 1829920Syasuko.eckert@amd.com 18310905Sandreas.sandberg@arm.com /** 1849428SAndreas.Sandberg@ARM.com * Provide a default implementation of the drain interface for 1859428SAndreas.Sandberg@ARM.com * objects that don't need draining. 1869428SAndreas.Sandberg@ARM.com */ 1879428SAndreas.Sandberg@ARM.com DrainState drain() override { return DrainState::Drained; } 1889428SAndreas.Sandberg@ARM.com 18910905Sandreas.sandberg@arm.com /** 1909428SAndreas.Sandberg@ARM.com * Write back dirty buffers to memory using functional writes. 1919428SAndreas.Sandberg@ARM.com * 1929428SAndreas.Sandberg@ARM.com * After returning, an object implementing this method should have 1939428SAndreas.Sandberg@ARM.com * written all its dirty data back to memory. This method is 1949428SAndreas.Sandberg@ARM.com * typically used to prepare a system with caches for 1959428SAndreas.Sandberg@ARM.com * checkpointing. 19610905Sandreas.sandberg@arm.com */ 1979428SAndreas.Sandberg@ARM.com virtual void memWriteback() {}; 1989428SAndreas.Sandberg@ARM.com 1999428SAndreas.Sandberg@ARM.com /** 20012109SRekai.GonzalezAlberquilla@arm.com * Invalidate the contents of memory buffers. 20112109SRekai.GonzalezAlberquilla@arm.com * 20212109SRekai.GonzalezAlberquilla@arm.com * When the switching to hardware virtualized CPU models, we need 20312109SRekai.GonzalezAlberquilla@arm.com * to make sure that we don't have any cached state in the system 20412109SRekai.GonzalezAlberquilla@arm.com * that might become stale when we return. This method is used to 20512109SRekai.GonzalezAlberquilla@arm.com * flush all such state back to main memory. 2069428SAndreas.Sandberg@ARM.com * 2079428SAndreas.Sandberg@ARM.com * @warn This does <i>not</i> cause any dirty state to be written 2089428SAndreas.Sandberg@ARM.com * back to memory. 2099428SAndreas.Sandberg@ARM.com */ 2109428SAndreas.Sandberg@ARM.com virtual void memInvalidate() {}; 2119920Syasuko.eckert@amd.com 2129920Syasuko.eckert@amd.com void serialize(CheckpointOut &cp) const override {}; 2139920Syasuko.eckert@amd.com void unserialize(CheckpointIn &cp) override {}; 2149920Syasuko.eckert@amd.com 2159920Syasuko.eckert@amd.com /** 2169920Syasuko.eckert@amd.com * Serialize all SimObjects in the system. 2179920Syasuko.eckert@amd.com */ 2189428SAndreas.Sandberg@ARM.com static void serializeAll(CheckpointOut &cp); 21910905Sandreas.sandberg@arm.com 2209428SAndreas.Sandberg@ARM.com#ifdef DEBUG 2219428SAndreas.Sandberg@ARM.com public: 2229428SAndreas.Sandberg@ARM.com bool doDebugBreak; 2239428SAndreas.Sandberg@ARM.com static void debugObjectBreak(const std::string &objs); 2249441SAndreas.Sandberg@ARM.com#endif 2259441SAndreas.Sandberg@ARM.com 2269441SAndreas.Sandberg@ARM.com /** 2279441SAndreas.Sandberg@ARM.com * Find the SimObject with the given name and return a pointer to 2289441SAndreas.Sandberg@ARM.com * it. Primarily used for interactive debugging. Argument is 2299441SAndreas.Sandberg@ARM.com * char* rather than std::string to make it callable from gdb. 2309441SAndreas.Sandberg@ARM.com */ 2319441SAndreas.Sandberg@ARM.com static SimObject *find(const char *name); 2329441SAndreas.Sandberg@ARM.com}; 2339441SAndreas.Sandberg@ARM.com 2349441SAndreas.Sandberg@ARM.com/** 2359441SAndreas.Sandberg@ARM.com * Base class to wrap object resolving functionality. 2369441SAndreas.Sandberg@ARM.com * 2379441SAndreas.Sandberg@ARM.com * This can be provided to the serialization framework to allow it to 2389441SAndreas.Sandberg@ARM.com * map object names onto C++ objects. 2399441SAndreas.Sandberg@ARM.com */ 2409441SAndreas.Sandberg@ARM.comclass SimObjectResolver 2419441SAndreas.Sandberg@ARM.com{ 2429441SAndreas.Sandberg@ARM.com public: 2439441SAndreas.Sandberg@ARM.com virtual ~SimObjectResolver() { } 2449441SAndreas.Sandberg@ARM.com 2459441SAndreas.Sandberg@ARM.com // Find a SimObject given a full path name 2469441SAndreas.Sandberg@ARM.com virtual SimObject *resolveSimObject(const std::string &name) = 0; 2479441SAndreas.Sandberg@ARM.com}; 2489441SAndreas.Sandberg@ARM.com 2499441SAndreas.Sandberg@ARM.com#ifdef DEBUG 2509441SAndreas.Sandberg@ARM.comvoid debugObjectBreak(const char *objs); 2519441SAndreas.Sandberg@ARM.com#endif 2529441SAndreas.Sandberg@ARM.com 2539441SAndreas.Sandberg@ARM.com#endif // __SIM_OBJECT_HH__ 2549441SAndreas.Sandberg@ARM.com